radeonfb: misc cleanup of engine and dst cache handling

Fix a couple of incomplete tests of the chip families in the engine
init/reset code and proper initialization of the destination cache mode.
The result should better match what the latest X radeon driver does.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: David S. Miller <davem@davemloft.net>
Cc: Krzysztof Halasa <khc@pm.waw.pl>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

1 files changed, 4 insertions, 1 deletions

diff --git a/include/video/radeon.h b/include/video/radeon.h
index 099ffa5e5bee..1cd09cc5b169 100644
--- a/include/video/radeon.h
+++ b/include/video/radeon.h
@@ -386,7 +386,7 @@
 #define SC_BOTTOM_RIGHT                        0x16F0  
 #define SRC_SC_BOTTOM_RIGHT                    0x16F4  
 #define RB2D_DSTCACHE_MODE                     0x3428
-#define RB2D_DSTCACHE_CTLSTAT                  0x342C
+#define RB2D_DSTCACHE_CTLSTAT_broken           0x342C /* do not use */
 #define LVDS_GEN_CNTL                          0x02d0
 #define LVDS_PLL_CNTL                          0x02d4
 #define FP2_GEN_CNTL                           0x0288
@@ -532,6 +532,9 @@
 #define RB2D_DC_FLUSH_ALL                          (RB2D_DC_FLUSH_2D | RB2D_DC_FREE_2D)
 #define RB2D_DC_BUSY                               (1 << 31)
 
+/* DSTCACHE_MODE bits constants */
+#define RB2D_DC_AUTOFLUSH_ENABLE                   (1 << 8)
+#define RB2D_DC_DC_DISABLE_IGNORE_PE               (1 << 17)
 
 /* CRTC_GEN_CNTL bit constants */
 #define CRTC_DBL_SCAN_EN                           0x00000001