diff options
| author | Randy Dunlap <randy.dunlap@oracle.com> | 2009-03-31 18:25:02 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-04-01 11:59:26 -0400 |
| commit | d5cb78feee7b6631f578e12bda1e86eea7923637 (patch) | |
| tree | 7d47de49ab57b6ec5bbc49b0a3e32220acae5233 /include/video/radeon.h | |
| parent | 6e6fe42227e23a379d3c70f6ff257131399e4075 (diff) | |
atyfb: fix header file trailing whitespace
Fix trailing whitespace because quilt complained about it.
Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/video/radeon.h')
| -rw-r--r-- | include/video/radeon.h | 564 |
1 files changed, 282 insertions, 282 deletions
diff --git a/include/video/radeon.h b/include/video/radeon.h index e072b16b39ab..56b188abfb54 100644 --- a/include/video/radeon.h +++ b/include/video/radeon.h | |||
| @@ -5,12 +5,12 @@ | |||
| 5 | #define RADEON_REGSIZE 0x4000 | 5 | #define RADEON_REGSIZE 0x4000 |
| 6 | 6 | ||
| 7 | 7 | ||
| 8 | #define MM_INDEX 0x0000 | 8 | #define MM_INDEX 0x0000 |
| 9 | #define MM_DATA 0x0004 | 9 | #define MM_DATA 0x0004 |
| 10 | #define BUS_CNTL 0x0030 | 10 | #define BUS_CNTL 0x0030 |
| 11 | #define HI_STAT 0x004C | 11 | #define HI_STAT 0x004C |
| 12 | #define BUS_CNTL1 0x0034 | 12 | #define BUS_CNTL1 0x0034 |
| 13 | #define I2C_CNTL_1 0x0094 | 13 | #define I2C_CNTL_1 0x0094 |
| 14 | #define CNFG_CNTL 0x00E0 | 14 | #define CNFG_CNTL 0x00E0 |
| 15 | #define CNFG_MEMSIZE 0x00F8 | 15 | #define CNFG_MEMSIZE 0x00F8 |
| 16 | #define CNFG_APER_0_BASE 0x0100 | 16 | #define CNFG_APER_0_BASE 0x0100 |
| @@ -18,8 +18,8 @@ | |||
| 18 | #define CNFG_APER_SIZE 0x0108 | 18 | #define CNFG_APER_SIZE 0x0108 |
| 19 | #define CNFG_REG_1_BASE 0x010C | 19 | #define CNFG_REG_1_BASE 0x010C |
| 20 | #define CNFG_REG_APER_SIZE 0x0110 | 20 | #define CNFG_REG_APER_SIZE 0x0110 |
| 21 | #define PAD_AGPINPUT_DELAY 0x0164 | 21 | #define PAD_AGPINPUT_DELAY 0x0164 |
| 22 | #define PAD_CTLR_STRENGTH 0x0168 | 22 | #define PAD_CTLR_STRENGTH 0x0168 |
| 23 | #define PAD_CTLR_UPDATE 0x016C | 23 | #define PAD_CTLR_UPDATE 0x016C |
| 24 | #define PAD_CTLR_MISC 0x0aa0 | 24 | #define PAD_CTLR_MISC 0x0aa0 |
| 25 | #define AGP_CNTL 0x0174 | 25 | #define AGP_CNTL 0x0174 |
| @@ -27,171 +27,171 @@ | |||
| 27 | #define CAP0_TRIG_CNTL 0x0950 | 27 | #define CAP0_TRIG_CNTL 0x0950 |
| 28 | #define CAP1_TRIG_CNTL 0x09c0 | 28 | #define CAP1_TRIG_CNTL 0x09c0 |
| 29 | #define VIPH_CONTROL 0x0C40 | 29 | #define VIPH_CONTROL 0x0C40 |
| 30 | #define VENDOR_ID 0x0F00 | 30 | #define VENDOR_ID 0x0F00 |
| 31 | #define DEVICE_ID 0x0F02 | 31 | #define DEVICE_ID 0x0F02 |
| 32 | #define COMMAND 0x0F04 | 32 | #define COMMAND 0x0F04 |
| 33 | #define STATUS 0x0F06 | 33 | #define STATUS 0x0F06 |
| 34 | #define REVISION_ID 0x0F08 | 34 | #define REVISION_ID 0x0F08 |
| 35 | #define REGPROG_INF 0x0F09 | 35 | #define REGPROG_INF 0x0F09 |
| 36 | #define SUB_CLASS 0x0F0A | 36 | #define SUB_CLASS 0x0F0A |
| 37 | #define BASE_CODE 0x0F0B | 37 | #define BASE_CODE 0x0F0B |
| 38 | #define CACHE_LINE 0x0F0C | 38 | #define CACHE_LINE 0x0F0C |
| 39 | #define LATENCY 0x0F0D | 39 | #define LATENCY 0x0F0D |
| 40 | #define HEADER 0x0F0E | 40 | #define HEADER 0x0F0E |
| 41 | #define BIST 0x0F0F | 41 | #define BIST 0x0F0F |
| 42 | #define REG_MEM_BASE 0x0F10 | 42 | #define REG_MEM_BASE 0x0F10 |
| 43 | #define REG_IO_BASE 0x0F14 | 43 | #define REG_IO_BASE 0x0F14 |
| 44 | #define REG_REG_BASE 0x0F18 | 44 | #define REG_REG_BASE 0x0F18 |
| 45 | #define ADAPTER_ID 0x0F2C | 45 | #define ADAPTER_ID 0x0F2C |
| 46 | #define BIOS_ROM 0x0F30 | 46 | #define BIOS_ROM 0x0F30 |
| 47 | #define CAPABILITIES_PTR 0x0F34 | 47 | #define CAPABILITIES_PTR 0x0F34 |
| 48 | #define INTERRUPT_LINE 0x0F3C | 48 | #define INTERRUPT_LINE 0x0F3C |
| 49 | #define INTERRUPT_PIN 0x0F3D | 49 | #define INTERRUPT_PIN 0x0F3D |
| 50 | #define MIN_GRANT 0x0F3E | 50 | #define MIN_GRANT 0x0F3E |
| 51 | #define MAX_LATENCY 0x0F3F | 51 | #define MAX_LATENCY 0x0F3F |
| 52 | #define ADAPTER_ID_W 0x0F4C | 52 | #define ADAPTER_ID_W 0x0F4C |
| 53 | #define PMI_CAP_ID 0x0F50 | 53 | #define PMI_CAP_ID 0x0F50 |
| 54 | #define PMI_NXT_CAP_PTR 0x0F51 | 54 | #define PMI_NXT_CAP_PTR 0x0F51 |
| 55 | #define PMI_PMC_REG 0x0F52 | 55 | #define PMI_PMC_REG 0x0F52 |
| 56 | #define PM_STATUS 0x0F54 | 56 | #define PM_STATUS 0x0F54 |
| 57 | #define PMI_DATA 0x0F57 | 57 | #define PMI_DATA 0x0F57 |
| 58 | #define AGP_CAP_ID 0x0F58 | 58 | #define AGP_CAP_ID 0x0F58 |
| 59 | #define AGP_STATUS 0x0F5C | 59 | #define AGP_STATUS 0x0F5C |
| 60 | #define AGP_COMMAND 0x0F60 | 60 | #define AGP_COMMAND 0x0F60 |
| 61 | #define AIC_CTRL 0x01D0 | 61 | #define AIC_CTRL 0x01D0 |
| 62 | #define AIC_STAT 0x01D4 | 62 | #define AIC_STAT 0x01D4 |
| 63 | #define AIC_PT_BASE 0x01D8 | 63 | #define AIC_PT_BASE 0x01D8 |
| 64 | #define AIC_LO_ADDR 0x01DC | 64 | #define AIC_LO_ADDR 0x01DC |
| 65 | #define AIC_HI_ADDR 0x01E0 | 65 | #define AIC_HI_ADDR 0x01E0 |
| 66 | #define AIC_TLB_ADDR 0x01E4 | 66 | #define AIC_TLB_ADDR 0x01E4 |
| 67 | #define AIC_TLB_DATA 0x01E8 | 67 | #define AIC_TLB_DATA 0x01E8 |
| 68 | #define DAC_CNTL 0x0058 | 68 | #define DAC_CNTL 0x0058 |
| 69 | #define DAC_CNTL2 0x007c | 69 | #define DAC_CNTL2 0x007c |
| 70 | #define CRTC_GEN_CNTL 0x0050 | 70 | #define CRTC_GEN_CNTL 0x0050 |
| 71 | #define MEM_CNTL 0x0140 | 71 | #define MEM_CNTL 0x0140 |
| 72 | #define MC_CNTL 0x0140 | 72 | #define MC_CNTL 0x0140 |
| 73 | #define EXT_MEM_CNTL 0x0144 | 73 | #define EXT_MEM_CNTL 0x0144 |
| 74 | #define MC_TIMING_CNTL 0x0144 | 74 | #define MC_TIMING_CNTL 0x0144 |
| 75 | #define MC_AGP_LOCATION 0x014C | 75 | #define MC_AGP_LOCATION 0x014C |
| 76 | #define MEM_IO_CNTL_A0 0x0178 | 76 | #define MEM_IO_CNTL_A0 0x0178 |
| 77 | #define MEM_REFRESH_CNTL 0x0178 | 77 | #define MEM_REFRESH_CNTL 0x0178 |
| 78 | #define MEM_INIT_LATENCY_TIMER 0x0154 | 78 | #define MEM_INIT_LATENCY_TIMER 0x0154 |
| 79 | #define MC_INIT_GFX_LAT_TIMER 0x0154 | 79 | #define MC_INIT_GFX_LAT_TIMER 0x0154 |
| 80 | #define MEM_SDRAM_MODE_REG 0x0158 | 80 | #define MEM_SDRAM_MODE_REG 0x0158 |
| 81 | #define AGP_BASE 0x0170 | 81 | #define AGP_BASE 0x0170 |
| 82 | #define MEM_IO_CNTL_A1 0x017C | 82 | #define MEM_IO_CNTL_A1 0x017C |
| 83 | #define MC_READ_CNTL_AB 0x017C | 83 | #define MC_READ_CNTL_AB 0x017C |
| 84 | #define MEM_IO_CNTL_B0 0x0180 | 84 | #define MEM_IO_CNTL_B0 0x0180 |
| 85 | #define MC_INIT_MISC_LAT_TIMER 0x0180 | 85 | #define MC_INIT_MISC_LAT_TIMER 0x0180 |
| 86 | #define MEM_IO_CNTL_B1 0x0184 | 86 | #define MEM_IO_CNTL_B1 0x0184 |
| 87 | #define MC_IOPAD_CNTL 0x0184 | 87 | #define MC_IOPAD_CNTL 0x0184 |
| 88 | #define MC_DEBUG 0x0188 | 88 | #define MC_DEBUG 0x0188 |
| 89 | #define MC_STATUS 0x0150 | 89 | #define MC_STATUS 0x0150 |
| 90 | #define MEM_IO_OE_CNTL 0x018C | 90 | #define MEM_IO_OE_CNTL 0x018C |
| 91 | #define MC_CHIP_IO_OE_CNTL_AB 0x018C | 91 | #define MC_CHIP_IO_OE_CNTL_AB 0x018C |
| 92 | #define MC_FB_LOCATION 0x0148 | 92 | #define MC_FB_LOCATION 0x0148 |
| 93 | #define HOST_PATH_CNTL 0x0130 | 93 | #define HOST_PATH_CNTL 0x0130 |
| 94 | #define MEM_VGA_WP_SEL 0x0038 | 94 | #define MEM_VGA_WP_SEL 0x0038 |
| 95 | #define MEM_VGA_RP_SEL 0x003C | 95 | #define MEM_VGA_RP_SEL 0x003C |
| 96 | #define HDP_DEBUG 0x0138 | 96 | #define HDP_DEBUG 0x0138 |
| 97 | #define SW_SEMAPHORE 0x013C | 97 | #define SW_SEMAPHORE 0x013C |
| 98 | #define CRTC2_GEN_CNTL 0x03f8 | 98 | #define CRTC2_GEN_CNTL 0x03f8 |
| 99 | #define CRTC2_DISPLAY_BASE_ADDR 0x033c | 99 | #define CRTC2_DISPLAY_BASE_ADDR 0x033c |
| 100 | #define SURFACE_CNTL 0x0B00 | 100 | #define SURFACE_CNTL 0x0B00 |
| 101 | #define SURFACE0_LOWER_BOUND 0x0B04 | 101 | #define SURFACE0_LOWER_BOUND 0x0B04 |
| 102 | #define SURFACE1_LOWER_BOUND 0x0B14 | 102 | #define SURFACE1_LOWER_BOUND 0x0B14 |
| 103 | #define SURFACE2_LOWER_BOUND 0x0B24 | 103 | #define SURFACE2_LOWER_BOUND 0x0B24 |
| 104 | #define SURFACE3_LOWER_BOUND 0x0B34 | 104 | #define SURFACE3_LOWER_BOUND 0x0B34 |
| 105 | #define SURFACE4_LOWER_BOUND 0x0B44 | 105 | #define SURFACE4_LOWER_BOUND 0x0B44 |
| 106 | #define SURFACE5_LOWER_BOUND 0x0B54 | 106 | #define SURFACE5_LOWER_BOUND 0x0B54 |
| 107 | #define SURFACE6_LOWER_BOUND 0x0B64 | 107 | #define SURFACE6_LOWER_BOUND 0x0B64 |
| 108 | #define SURFACE7_LOWER_BOUND 0x0B74 | 108 | #define SURFACE7_LOWER_BOUND 0x0B74 |
| 109 | #define SURFACE0_UPPER_BOUND 0x0B08 | 109 | #define SURFACE0_UPPER_BOUND 0x0B08 |
| 110 | #define SURFACE1_UPPER_BOUND 0x0B18 | 110 | #define SURFACE1_UPPER_BOUND 0x0B18 |
| 111 | #define SURFACE2_UPPER_BOUND 0x0B28 | 111 | #define SURFACE2_UPPER_BOUND 0x0B28 |
| 112 | #define SURFACE3_UPPER_BOUND 0x0B38 | 112 | #define SURFACE3_UPPER_BOUND 0x0B38 |
| 113 | #define SURFACE4_UPPER_BOUND 0x0B48 | 113 | #define SURFACE4_UPPER_BOUND 0x0B48 |
| 114 | #define SURFACE5_UPPER_BOUND 0x0B58 | 114 | #define SURFACE5_UPPER_BOUND 0x0B58 |
| 115 | #define SURFACE6_UPPER_BOUND 0x0B68 | 115 | #define SURFACE6_UPPER_BOUND 0x0B68 |
| 116 | #define SURFACE7_UPPER_BOUND 0x0B78 | 116 | #define SURFACE7_UPPER_BOUND 0x0B78 |
| 117 | #define SURFACE0_INFO 0x0B0C | 117 | #define SURFACE0_INFO 0x0B0C |
| 118 | #define SURFACE1_INFO 0x0B1C | 118 | #define SURFACE1_INFO 0x0B1C |
| 119 | #define SURFACE2_INFO 0x0B2C | 119 | #define SURFACE2_INFO 0x0B2C |
| 120 | #define SURFACE3_INFO 0x0B3C | 120 | #define SURFACE3_INFO 0x0B3C |
| 121 | #define SURFACE4_INFO 0x0B4C | 121 | #define SURFACE4_INFO 0x0B4C |
| 122 | #define SURFACE5_INFO 0x0B5C | 122 | #define SURFACE5_INFO 0x0B5C |
| 123 | #define SURFACE6_INFO 0x0B6C | 123 | #define SURFACE6_INFO 0x0B6C |
| 124 | #define SURFACE7_INFO 0x0B7C | 124 | #define SURFACE7_INFO 0x0B7C |
| 125 | #define SURFACE_ACCESS_FLAGS 0x0BF8 | 125 | #define SURFACE_ACCESS_FLAGS 0x0BF8 |
| 126 | #define SURFACE_ACCESS_CLR 0x0BFC | 126 | #define SURFACE_ACCESS_CLR 0x0BFC |
| 127 | #define GEN_INT_CNTL 0x0040 | 127 | #define GEN_INT_CNTL 0x0040 |
| 128 | #define GEN_INT_STATUS 0x0044 | 128 | #define GEN_INT_STATUS 0x0044 |
| 129 | #define CRTC_EXT_CNTL 0x0054 | 129 | #define CRTC_EXT_CNTL 0x0054 |
| 130 | #define RB3D_CNTL 0x1C3C | 130 | #define RB3D_CNTL 0x1C3C |
| 131 | #define WAIT_UNTIL 0x1720 | 131 | #define WAIT_UNTIL 0x1720 |
| 132 | #define ISYNC_CNTL 0x1724 | 132 | #define ISYNC_CNTL 0x1724 |
| 133 | #define RBBM_GUICNTL 0x172C | 133 | #define RBBM_GUICNTL 0x172C |
| 134 | #define RBBM_STATUS 0x0E40 | 134 | #define RBBM_STATUS 0x0E40 |
| 135 | #define RBBM_STATUS_alt_1 0x1740 | 135 | #define RBBM_STATUS_alt_1 0x1740 |
| 136 | #define RBBM_CNTL 0x00EC | 136 | #define RBBM_CNTL 0x00EC |
| 137 | #define RBBM_CNTL_alt_1 0x0E44 | 137 | #define RBBM_CNTL_alt_1 0x0E44 |
| 138 | #define RBBM_SOFT_RESET 0x00F0 | 138 | #define RBBM_SOFT_RESET 0x00F0 |
| 139 | #define RBBM_SOFT_RESET_alt_1 0x0E48 | 139 | #define RBBM_SOFT_RESET_alt_1 0x0E48 |
| 140 | #define NQWAIT_UNTIL 0x0E50 | 140 | #define NQWAIT_UNTIL 0x0E50 |
| 141 | #define RBBM_DEBUG 0x0E6C | 141 | #define RBBM_DEBUG 0x0E6C |
| 142 | #define RBBM_CMDFIFO_ADDR 0x0E70 | 142 | #define RBBM_CMDFIFO_ADDR 0x0E70 |
| 143 | #define RBBM_CMDFIFO_DATAL 0x0E74 | 143 | #define RBBM_CMDFIFO_DATAL 0x0E74 |
| 144 | #define RBBM_CMDFIFO_DATAH 0x0E78 | 144 | #define RBBM_CMDFIFO_DATAH 0x0E78 |
| 145 | #define RBBM_CMDFIFO_STAT 0x0E7C | 145 | #define RBBM_CMDFIFO_STAT 0x0E7C |
| 146 | #define CRTC_STATUS 0x005C | 146 | #define CRTC_STATUS 0x005C |
| 147 | #define GPIO_VGA_DDC 0x0060 | 147 | #define GPIO_VGA_DDC 0x0060 |
| 148 | #define GPIO_DVI_DDC 0x0064 | 148 | #define GPIO_DVI_DDC 0x0064 |
| 149 | #define GPIO_MONID 0x0068 | 149 | #define GPIO_MONID 0x0068 |
| 150 | #define GPIO_CRT2_DDC 0x006c | 150 | #define GPIO_CRT2_DDC 0x006c |
| 151 | #define PALETTE_INDEX 0x00B0 | 151 | #define PALETTE_INDEX 0x00B0 |
| 152 | #define PALETTE_DATA 0x00B4 | 152 | #define PALETTE_DATA 0x00B4 |
| 153 | #define PALETTE_30_DATA 0x00B8 | 153 | #define PALETTE_30_DATA 0x00B8 |
| 154 | #define CRTC_H_TOTAL_DISP 0x0200 | 154 | #define CRTC_H_TOTAL_DISP 0x0200 |
| 155 | #define CRTC_H_SYNC_STRT_WID 0x0204 | 155 | #define CRTC_H_SYNC_STRT_WID 0x0204 |
| 156 | #define CRTC_V_TOTAL_DISP 0x0208 | 156 | #define CRTC_V_TOTAL_DISP 0x0208 |
| 157 | #define CRTC_V_SYNC_STRT_WID 0x020C | 157 | #define CRTC_V_SYNC_STRT_WID 0x020C |
| 158 | #define CRTC_VLINE_CRNT_VLINE 0x0210 | 158 | #define CRTC_VLINE_CRNT_VLINE 0x0210 |
| 159 | #define CRTC_CRNT_FRAME 0x0214 | 159 | #define CRTC_CRNT_FRAME 0x0214 |
| 160 | #define CRTC_GUI_TRIG_VLINE 0x0218 | 160 | #define CRTC_GUI_TRIG_VLINE 0x0218 |
| 161 | #define CRTC_DEBUG 0x021C | 161 | #define CRTC_DEBUG 0x021C |
| 162 | #define CRTC_OFFSET_RIGHT 0x0220 | 162 | #define CRTC_OFFSET_RIGHT 0x0220 |
| 163 | #define CRTC_OFFSET 0x0224 | 163 | #define CRTC_OFFSET 0x0224 |
| 164 | #define CRTC_OFFSET_CNTL 0x0228 | 164 | #define CRTC_OFFSET_CNTL 0x0228 |
| 165 | #define CRTC_PITCH 0x022C | 165 | #define CRTC_PITCH 0x022C |
| 166 | #define OVR_CLR 0x0230 | 166 | #define OVR_CLR 0x0230 |
| 167 | #define OVR_WID_LEFT_RIGHT 0x0234 | 167 | #define OVR_WID_LEFT_RIGHT 0x0234 |
| 168 | #define OVR_WID_TOP_BOTTOM 0x0238 | 168 | #define OVR_WID_TOP_BOTTOM 0x0238 |
| 169 | #define DISPLAY_BASE_ADDR 0x023C | 169 | #define DISPLAY_BASE_ADDR 0x023C |
| 170 | #define SNAPSHOT_VH_COUNTS 0x0240 | 170 | #define SNAPSHOT_VH_COUNTS 0x0240 |
| 171 | #define SNAPSHOT_F_COUNT 0x0244 | 171 | #define SNAPSHOT_F_COUNT 0x0244 |
| 172 | #define N_VIF_COUNT 0x0248 | 172 | #define N_VIF_COUNT 0x0248 |
| 173 | #define SNAPSHOT_VIF_COUNT 0x024C | 173 | #define SNAPSHOT_VIF_COUNT 0x024C |
| 174 | #define FP_CRTC_H_TOTAL_DISP 0x0250 | 174 | #define FP_CRTC_H_TOTAL_DISP 0x0250 |
| 175 | #define FP_CRTC_V_TOTAL_DISP 0x0254 | 175 | #define FP_CRTC_V_TOTAL_DISP 0x0254 |
| 176 | #define CRT_CRTC_H_SYNC_STRT_WID 0x0258 | 176 | #define CRT_CRTC_H_SYNC_STRT_WID 0x0258 |
| 177 | #define CRT_CRTC_V_SYNC_STRT_WID 0x025C | 177 | #define CRT_CRTC_V_SYNC_STRT_WID 0x025C |
| 178 | #define CUR_OFFSET 0x0260 | 178 | #define CUR_OFFSET 0x0260 |
| 179 | #define CUR_HORZ_VERT_POSN 0x0264 | 179 | #define CUR_HORZ_VERT_POSN 0x0264 |
| 180 | #define CUR_HORZ_VERT_OFF 0x0268 | 180 | #define CUR_HORZ_VERT_OFF 0x0268 |
| 181 | #define CUR_CLR0 0x026C | 181 | #define CUR_CLR0 0x026C |
| 182 | #define CUR_CLR1 0x0270 | 182 | #define CUR_CLR1 0x0270 |
| 183 | #define FP_HORZ_VERT_ACTIVE 0x0278 | 183 | #define FP_HORZ_VERT_ACTIVE 0x0278 |
| 184 | #define CRTC_MORE_CNTL 0x027C | 184 | #define CRTC_MORE_CNTL 0x027C |
| 185 | #define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) | 185 | #define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) |
| 186 | #define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) | 186 | #define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) |
| 187 | #define DAC_EXT_CNTL 0x0280 | 187 | #define DAC_EXT_CNTL 0x0280 |
| 188 | #define FP_GEN_CNTL 0x0284 | 188 | #define FP_GEN_CNTL 0x0284 |
| 189 | #define FP_HORZ_STRETCH 0x028C | 189 | #define FP_HORZ_STRETCH 0x028C |
| 190 | #define FP_VERT_STRETCH 0x0290 | 190 | #define FP_VERT_STRETCH 0x0290 |
| 191 | #define FP_H_SYNC_STRT_WID 0x02C4 | 191 | #define FP_H_SYNC_STRT_WID 0x02C4 |
| 192 | #define FP_V_SYNC_STRT_WID 0x02C8 | 192 | #define FP_V_SYNC_STRT_WID 0x02C8 |
| 193 | #define AUX_WINDOW_HORZ_CNTL 0x02D8 | 193 | #define AUX_WINDOW_HORZ_CNTL 0x02D8 |
| 194 | #define AUX_WINDOW_VERT_CNTL 0x02DC | 194 | #define AUX_WINDOW_VERT_CNTL 0x02DC |
| 195 | //#define DDA_CONFIG 0x02e0 | 195 | //#define DDA_CONFIG 0x02e0 |
| 196 | //#define DDA_ON_OFF 0x02e4 | 196 | //#define DDA_ON_OFF 0x02e4 |
| 197 | #define DVI_I2C_CNTL_1 0x02e4 | 197 | #define DVI_I2C_CNTL_1 0x02e4 |
| @@ -199,192 +199,192 @@ | |||
| 199 | #define GRPH2_BUFFER_CNTL 0x03F0 | 199 | #define GRPH2_BUFFER_CNTL 0x03F0 |
| 200 | #define VGA_BUFFER_CNTL 0x02F4 | 200 | #define VGA_BUFFER_CNTL 0x02F4 |
| 201 | #define OV0_Y_X_START 0x0400 | 201 | #define OV0_Y_X_START 0x0400 |
| 202 | #define OV0_Y_X_END 0x0404 | 202 | #define OV0_Y_X_END 0x0404 |
| 203 | #define OV0_PIPELINE_CNTL 0x0408 | 203 | #define OV0_PIPELINE_CNTL 0x0408 |
| 204 | #define OV0_REG_LOAD_CNTL 0x0410 | 204 | #define OV0_REG_LOAD_CNTL 0x0410 |
| 205 | #define OV0_SCALE_CNTL 0x0420 | 205 | #define OV0_SCALE_CNTL 0x0420 |
| 206 | #define OV0_V_INC 0x0424 | 206 | #define OV0_V_INC 0x0424 |
| 207 | #define OV0_P1_V_ACCUM_INIT 0x0428 | 207 | #define OV0_P1_V_ACCUM_INIT 0x0428 |
| 208 | #define OV0_P23_V_ACCUM_INIT 0x042C | 208 | #define OV0_P23_V_ACCUM_INIT 0x042C |
| 209 | #define OV0_P1_BLANK_LINES_AT_TOP 0x0430 | 209 | #define OV0_P1_BLANK_LINES_AT_TOP 0x0430 |
| 210 | #define OV0_P23_BLANK_LINES_AT_TOP 0x0434 | 210 | #define OV0_P23_BLANK_LINES_AT_TOP 0x0434 |
| 211 | #define OV0_BASE_ADDR 0x043C | 211 | #define OV0_BASE_ADDR 0x043C |
| 212 | #define OV0_VID_BUF0_BASE_ADRS 0x0440 | 212 | #define OV0_VID_BUF0_BASE_ADRS 0x0440 |
| 213 | #define OV0_VID_BUF1_BASE_ADRS 0x0444 | 213 | #define OV0_VID_BUF1_BASE_ADRS 0x0444 |
| 214 | #define OV0_VID_BUF2_BASE_ADRS 0x0448 | 214 | #define OV0_VID_BUF2_BASE_ADRS 0x0448 |
| 215 | #define OV0_VID_BUF3_BASE_ADRS 0x044C | 215 | #define OV0_VID_BUF3_BASE_ADRS 0x044C |
| 216 | #define OV0_VID_BUF4_BASE_ADRS 0x0450 | 216 | #define OV0_VID_BUF4_BASE_ADRS 0x0450 |
| 217 | #define OV0_VID_BUF5_BASE_ADRS 0x0454 | 217 | #define OV0_VID_BUF5_BASE_ADRS 0x0454 |
| 218 | #define OV0_VID_BUF_PITCH0_VALUE 0x0460 | 218 | #define OV0_VID_BUF_PITCH0_VALUE 0x0460 |
| 219 | #define OV0_VID_BUF_PITCH1_VALUE 0x0464 | 219 | #define OV0_VID_BUF_PITCH1_VALUE 0x0464 |
| 220 | #define OV0_AUTO_FLIP_CNTRL 0x0470 | 220 | #define OV0_AUTO_FLIP_CNTRL 0x0470 |
| 221 | #define OV0_DEINTERLACE_PATTERN 0x0474 | 221 | #define OV0_DEINTERLACE_PATTERN 0x0474 |
| 222 | #define OV0_SUBMIT_HISTORY 0x0478 | 222 | #define OV0_SUBMIT_HISTORY 0x0478 |
| 223 | #define OV0_H_INC 0x0480 | 223 | #define OV0_H_INC 0x0480 |
| 224 | #define OV0_STEP_BY 0x0484 | 224 | #define OV0_STEP_BY 0x0484 |
| 225 | #define OV0_P1_H_ACCUM_INIT 0x0488 | 225 | #define OV0_P1_H_ACCUM_INIT 0x0488 |
| 226 | #define OV0_P23_H_ACCUM_INIT 0x048C | 226 | #define OV0_P23_H_ACCUM_INIT 0x048C |
| 227 | #define OV0_P1_X_START_END 0x0494 | 227 | #define OV0_P1_X_START_END 0x0494 |
| 228 | #define OV0_P2_X_START_END 0x0498 | 228 | #define OV0_P2_X_START_END 0x0498 |
| 229 | #define OV0_P3_X_START_END 0x049C | 229 | #define OV0_P3_X_START_END 0x049C |
| 230 | #define OV0_FILTER_CNTL 0x04A0 | 230 | #define OV0_FILTER_CNTL 0x04A0 |
| 231 | #define OV0_FOUR_TAP_COEF_0 0x04B0 | 231 | #define OV0_FOUR_TAP_COEF_0 0x04B0 |
| 232 | #define OV0_FOUR_TAP_COEF_1 0x04B4 | 232 | #define OV0_FOUR_TAP_COEF_1 0x04B4 |
| 233 | #define OV0_FOUR_TAP_COEF_2 0x04B8 | 233 | #define OV0_FOUR_TAP_COEF_2 0x04B8 |
| 234 | #define OV0_FOUR_TAP_COEF_3 0x04BC | 234 | #define OV0_FOUR_TAP_COEF_3 0x04BC |
| 235 | #define OV0_FOUR_TAP_COEF_4 0x04C0 | 235 | #define OV0_FOUR_TAP_COEF_4 0x04C0 |
| 236 | #define OV0_FLAG_CNTRL 0x04DC | 236 | #define OV0_FLAG_CNTRL 0x04DC |
| 237 | #define OV0_SLICE_CNTL 0x04E0 | 237 | #define OV0_SLICE_CNTL 0x04E0 |
| 238 | #define OV0_VID_KEY_CLR_LOW 0x04E4 | 238 | #define OV0_VID_KEY_CLR_LOW 0x04E4 |
| 239 | #define OV0_VID_KEY_CLR_HIGH 0x04E8 | 239 | #define OV0_VID_KEY_CLR_HIGH 0x04E8 |
| 240 | #define OV0_GRPH_KEY_CLR_LOW 0x04EC | 240 | #define OV0_GRPH_KEY_CLR_LOW 0x04EC |
| 241 | #define OV0_GRPH_KEY_CLR_HIGH 0x04F0 | 241 | #define OV0_GRPH_KEY_CLR_HIGH 0x04F0 |
| 242 | #define OV0_KEY_CNTL 0x04F4 | 242 | #define OV0_KEY_CNTL 0x04F4 |
| 243 | #define OV0_TEST 0x04F8 | 243 | #define OV0_TEST 0x04F8 |
| 244 | #define SUBPIC_CNTL 0x0540 | 244 | #define SUBPIC_CNTL 0x0540 |
| 245 | #define SUBPIC_DEFCOLCON 0x0544 | 245 | #define SUBPIC_DEFCOLCON 0x0544 |
| 246 | #define SUBPIC_Y_X_START 0x054C | 246 | #define SUBPIC_Y_X_START 0x054C |
| 247 | #define SUBPIC_Y_X_END 0x0550 | 247 | #define SUBPIC_Y_X_END 0x0550 |
| 248 | #define SUBPIC_V_INC 0x0554 | 248 | #define SUBPIC_V_INC 0x0554 |
| 249 | #define SUBPIC_H_INC 0x0558 | 249 | #define SUBPIC_H_INC 0x0558 |
| 250 | #define SUBPIC_BUF0_OFFSET 0x055C | 250 | #define SUBPIC_BUF0_OFFSET 0x055C |
| 251 | #define SUBPIC_BUF1_OFFSET 0x0560 | 251 | #define SUBPIC_BUF1_OFFSET 0x0560 |
| 252 | #define SUBPIC_LC0_OFFSET 0x0564 | 252 | #define SUBPIC_LC0_OFFSET 0x0564 |
| 253 | #define SUBPIC_LC1_OFFSET 0x0568 | 253 | #define SUBPIC_LC1_OFFSET 0x0568 |
| 254 | #define SUBPIC_PITCH 0x056C | 254 | #define SUBPIC_PITCH 0x056C |
| 255 | #define SUBPIC_BTN_HLI_COLCON 0x0570 | 255 | #define SUBPIC_BTN_HLI_COLCON 0x0570 |
| 256 | #define SUBPIC_BTN_HLI_Y_X_START 0x0574 | 256 | #define SUBPIC_BTN_HLI_Y_X_START 0x0574 |
| 257 | #define SUBPIC_BTN_HLI_Y_X_END 0x0578 | 257 | #define SUBPIC_BTN_HLI_Y_X_END 0x0578 |
| 258 | #define SUBPIC_PALETTE_INDEX 0x057C | 258 | #define SUBPIC_PALETTE_INDEX 0x057C |
| 259 | #define SUBPIC_PALETTE_DATA 0x0580 | 259 | #define SUBPIC_PALETTE_DATA 0x0580 |
| 260 | #define SUBPIC_H_ACCUM_INIT 0x0584 | 260 | #define SUBPIC_H_ACCUM_INIT 0x0584 |
| 261 | #define SUBPIC_V_ACCUM_INIT 0x0588 | 261 | #define SUBPIC_V_ACCUM_INIT 0x0588 |
| 262 | #define DISP_MISC_CNTL 0x0D00 | 262 | #define DISP_MISC_CNTL 0x0D00 |
| 263 | #define DAC_MACRO_CNTL 0x0D04 | 263 | #define DAC_MACRO_CNTL 0x0D04 |
| 264 | #define DISP_PWR_MAN 0x0D08 | 264 | #define DISP_PWR_MAN 0x0D08 |
| 265 | #define DISP_TEST_DEBUG_CNTL 0x0D10 | 265 | #define DISP_TEST_DEBUG_CNTL 0x0D10 |
| 266 | #define DISP_HW_DEBUG 0x0D14 | 266 | #define DISP_HW_DEBUG 0x0D14 |
| 267 | #define DAC_CRC_SIG1 0x0D18 | 267 | #define DAC_CRC_SIG1 0x0D18 |
| 268 | #define DAC_CRC_SIG2 0x0D1C | 268 | #define DAC_CRC_SIG2 0x0D1C |
| 269 | #define OV0_LIN_TRANS_A 0x0D20 | 269 | #define OV0_LIN_TRANS_A 0x0D20 |
| 270 | #define OV0_LIN_TRANS_B 0x0D24 | 270 | #define OV0_LIN_TRANS_B 0x0D24 |
| 271 | #define OV0_LIN_TRANS_C 0x0D28 | 271 | #define OV0_LIN_TRANS_C 0x0D28 |
| 272 | #define OV0_LIN_TRANS_D 0x0D2C | 272 | #define OV0_LIN_TRANS_D 0x0D2C |
| 273 | #define OV0_LIN_TRANS_E 0x0D30 | 273 | #define OV0_LIN_TRANS_E 0x0D30 |
| 274 | #define OV0_LIN_TRANS_F 0x0D34 | 274 | #define OV0_LIN_TRANS_F 0x0D34 |
| 275 | #define OV0_GAMMA_0_F 0x0D40 | 275 | #define OV0_GAMMA_0_F 0x0D40 |
| 276 | #define OV0_GAMMA_10_1F 0x0D44 | 276 | #define OV0_GAMMA_10_1F 0x0D44 |
| 277 | #define OV0_GAMMA_20_3F 0x0D48 | 277 | #define OV0_GAMMA_20_3F 0x0D48 |
| 278 | #define OV0_GAMMA_40_7F 0x0D4C | 278 | #define OV0_GAMMA_40_7F 0x0D4C |
| 279 | #define OV0_GAMMA_380_3BF 0x0D50 | 279 | #define OV0_GAMMA_380_3BF 0x0D50 |
| 280 | #define OV0_GAMMA_3C0_3FF 0x0D54 | 280 | #define OV0_GAMMA_3C0_3FF 0x0D54 |
| 281 | #define DISP_MERGE_CNTL 0x0D60 | 281 | #define DISP_MERGE_CNTL 0x0D60 |
| 282 | #define DISP_OUTPUT_CNTL 0x0D64 | 282 | #define DISP_OUTPUT_CNTL 0x0D64 |
| 283 | #define DISP_LIN_TRANS_GRPH_A 0x0D80 | 283 | #define DISP_LIN_TRANS_GRPH_A 0x0D80 |
| 284 | #define DISP_LIN_TRANS_GRPH_B 0x0D84 | 284 | #define DISP_LIN_TRANS_GRPH_B 0x0D84 |
| 285 | #define DISP_LIN_TRANS_GRPH_C 0x0D88 | 285 | #define DISP_LIN_TRANS_GRPH_C 0x0D88 |
| 286 | #define DISP_LIN_TRANS_GRPH_D 0x0D8C | 286 | #define DISP_LIN_TRANS_GRPH_D 0x0D8C |
| 287 | #define DISP_LIN_TRANS_GRPH_E 0x0D90 | 287 | #define DISP_LIN_TRANS_GRPH_E 0x0D90 |
| 288 | #define DISP_LIN_TRANS_GRPH_F 0x0D94 | 288 | #define DISP_LIN_TRANS_GRPH_F 0x0D94 |
| 289 | #define DISP_LIN_TRANS_VID_A 0x0D98 | 289 | #define DISP_LIN_TRANS_VID_A 0x0D98 |
| 290 | #define DISP_LIN_TRANS_VID_B 0x0D9C | 290 | #define DISP_LIN_TRANS_VID_B 0x0D9C |
| 291 | #define DISP_LIN_TRANS_VID_C 0x0DA0 | 291 | #define DISP_LIN_TRANS_VID_C 0x0DA0 |
| 292 | #define DISP_LIN_TRANS_VID_D 0x0DA4 | 292 | #define DISP_LIN_TRANS_VID_D 0x0DA4 |
| 293 | #define DISP_LIN_TRANS_VID_E 0x0DA8 | 293 | #define DISP_LIN_TRANS_VID_E 0x0DA8 |
| 294 | #define DISP_LIN_TRANS_VID_F 0x0DAC | 294 | #define DISP_LIN_TRANS_VID_F 0x0DAC |
| 295 | #define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 | 295 | #define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 |
| 296 | #define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 | 296 | #define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 |
| 297 | #define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 | 297 | #define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 |
| 298 | #define RMX_HORZ_PHASE 0x0DBC | 298 | #define RMX_HORZ_PHASE 0x0DBC |
| 299 | #define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 | 299 | #define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 |
| 300 | #define DAC_BROAD_PULSE 0x0DC4 | 300 | #define DAC_BROAD_PULSE 0x0DC4 |
| 301 | #define DAC_SKEW_CLKS 0x0DC8 | 301 | #define DAC_SKEW_CLKS 0x0DC8 |
| 302 | #define DAC_INCR 0x0DCC | 302 | #define DAC_INCR 0x0DCC |
| 303 | #define DAC_NEG_SYNC_LEVEL 0x0DD0 | 303 | #define DAC_NEG_SYNC_LEVEL 0x0DD0 |
| 304 | #define DAC_POS_SYNC_LEVEL 0x0DD4 | 304 | #define DAC_POS_SYNC_LEVEL 0x0DD4 |
| 305 | #define DAC_BLANK_LEVEL 0x0DD8 | 305 | #define DAC_BLANK_LEVEL 0x0DD8 |
| 306 | #define CLOCK_CNTL_INDEX 0x0008 | 306 | #define CLOCK_CNTL_INDEX 0x0008 |
| 307 | #define CLOCK_CNTL_DATA 0x000C | 307 | #define CLOCK_CNTL_DATA 0x000C |
| 308 | #define CP_RB_CNTL 0x0704 | 308 | #define CP_RB_CNTL 0x0704 |
| 309 | #define CP_RB_BASE 0x0700 | 309 | #define CP_RB_BASE 0x0700 |
| 310 | #define CP_RB_RPTR_ADDR 0x070C | 310 | #define CP_RB_RPTR_ADDR 0x070C |
| 311 | #define CP_RB_RPTR 0x0710 | 311 | #define CP_RB_RPTR 0x0710 |
| 312 | #define CP_RB_WPTR 0x0714 | 312 | #define CP_RB_WPTR 0x0714 |
| 313 | #define CP_RB_WPTR_DELAY 0x0718 | 313 | #define CP_RB_WPTR_DELAY 0x0718 |
| 314 | #define CP_IB_BASE 0x0738 | 314 | #define CP_IB_BASE 0x0738 |
| 315 | #define CP_IB_BUFSZ 0x073C | 315 | #define CP_IB_BUFSZ 0x073C |
| 316 | #define SCRATCH_REG0 0x15E0 | 316 | #define SCRATCH_REG0 0x15E0 |
| 317 | #define GUI_SCRATCH_REG0 0x15E0 | 317 | #define GUI_SCRATCH_REG0 0x15E0 |
| 318 | #define SCRATCH_REG1 0x15E4 | 318 | #define SCRATCH_REG1 0x15E4 |
| 319 | #define GUI_SCRATCH_REG1 0x15E4 | 319 | #define GUI_SCRATCH_REG1 0x15E4 |
| 320 | #define SCRATCH_REG2 0x15E8 | 320 | #define SCRATCH_REG2 0x15E8 |
| 321 | #define GUI_SCRATCH_REG2 0x15E8 | 321 | #define GUI_SCRATCH_REG2 0x15E8 |
| 322 | #define SCRATCH_REG3 0x15EC | 322 | #define SCRATCH_REG3 0x15EC |
| 323 | #define GUI_SCRATCH_REG3 0x15EC | 323 | #define GUI_SCRATCH_REG3 0x15EC |
| 324 | #define SCRATCH_REG4 0x15F0 | 324 | #define SCRATCH_REG4 0x15F0 |
| 325 | #define GUI_SCRATCH_REG4 0x15F0 | 325 | #define GUI_SCRATCH_REG4 0x15F0 |
| 326 | #define SCRATCH_REG5 0x15F4 | 326 | #define SCRATCH_REG5 0x15F4 |
| 327 | #define GUI_SCRATCH_REG5 0x15F4 | 327 | #define GUI_SCRATCH_REG5 0x15F4 |
| 328 | #define SCRATCH_UMSK 0x0770 | 328 | #define SCRATCH_UMSK 0x0770 |
| 329 | #define SCRATCH_ADDR 0x0774 | 329 | #define SCRATCH_ADDR 0x0774 |
| 330 | #define DP_BRUSH_FRGD_CLR 0x147C | 330 | #define DP_BRUSH_FRGD_CLR 0x147C |
| 331 | #define DP_BRUSH_BKGD_CLR 0x1478 | 331 | #define DP_BRUSH_BKGD_CLR 0x1478 |
| 332 | #define DST_LINE_START 0x1600 | 332 | #define DST_LINE_START 0x1600 |
| 333 | #define DST_LINE_END 0x1604 | 333 | #define DST_LINE_END 0x1604 |
| 334 | #define SRC_OFFSET 0x15AC | 334 | #define SRC_OFFSET 0x15AC |
| 335 | #define SRC_PITCH 0x15B0 | 335 | #define SRC_PITCH 0x15B0 |
| 336 | #define SRC_TILE 0x1704 | 336 | #define SRC_TILE 0x1704 |
| 337 | #define SRC_PITCH_OFFSET 0x1428 | 337 | #define SRC_PITCH_OFFSET 0x1428 |
| 338 | #define SRC_X 0x1414 | 338 | #define SRC_X 0x1414 |
| 339 | #define SRC_Y 0x1418 | 339 | #define SRC_Y 0x1418 |
| 340 | #define SRC_X_Y 0x1590 | 340 | #define SRC_X_Y 0x1590 |
| 341 | #define SRC_Y_X 0x1434 | 341 | #define SRC_Y_X 0x1434 |
| 342 | #define DST_Y_X 0x1438 | 342 | #define DST_Y_X 0x1438 |
| 343 | #define DST_WIDTH_HEIGHT 0x1598 | 343 | #define DST_WIDTH_HEIGHT 0x1598 |
| 344 | #define DST_HEIGHT_WIDTH 0x143c | 344 | #define DST_HEIGHT_WIDTH 0x143c |
| 345 | #define DST_OFFSET 0x1404 | 345 | #define DST_OFFSET 0x1404 |
| 346 | #define SRC_CLUT_ADDRESS 0x1780 | 346 | #define SRC_CLUT_ADDRESS 0x1780 |
| 347 | #define SRC_CLUT_DATA 0x1784 | 347 | #define SRC_CLUT_DATA 0x1784 |
| 348 | #define SRC_CLUT_DATA_RD 0x1788 | 348 | #define SRC_CLUT_DATA_RD 0x1788 |
| 349 | #define HOST_DATA0 0x17C0 | 349 | #define HOST_DATA0 0x17C0 |
| 350 | #define HOST_DATA1 0x17C4 | 350 | #define HOST_DATA1 0x17C4 |
| 351 | #define HOST_DATA2 0x17C8 | 351 | #define HOST_DATA2 0x17C8 |
| 352 | #define HOST_DATA3 0x17CC | 352 | #define HOST_DATA3 0x17CC |
| 353 | #define HOST_DATA4 0x17D0 | 353 | #define HOST_DATA4 0x17D0 |
| 354 | #define HOST_DATA5 0x17D4 | 354 | #define HOST_DATA5 0x17D4 |
| 355 | #define HOST_DATA6 0x17D8 | 355 | #define HOST_DATA6 0x17D8 |
| 356 | #define HOST_DATA7 0x17DC | 356 | #define HOST_DATA7 0x17DC |
| 357 | #define HOST_DATA_LAST 0x17E0 | 357 | #define HOST_DATA_LAST 0x17E0 |
| 358 | #define DP_SRC_ENDIAN 0x15D4 | 358 | #define DP_SRC_ENDIAN 0x15D4 |
| 359 | #define DP_SRC_FRGD_CLR 0x15D8 | 359 | #define DP_SRC_FRGD_CLR 0x15D8 |
| 360 | #define DP_SRC_BKGD_CLR 0x15DC | 360 | #define DP_SRC_BKGD_CLR 0x15DC |
| 361 | #define SC_LEFT 0x1640 | 361 | #define SC_LEFT 0x1640 |
| 362 | #define SC_RIGHT 0x1644 | 362 | #define SC_RIGHT 0x1644 |
| 363 | #define SC_TOP 0x1648 | 363 | #define SC_TOP 0x1648 |
| 364 | #define SC_BOTTOM 0x164C | 364 | #define SC_BOTTOM 0x164C |
| 365 | #define SRC_SC_RIGHT 0x1654 | 365 | #define SRC_SC_RIGHT 0x1654 |
| 366 | #define SRC_SC_BOTTOM 0x165C | 366 | #define SRC_SC_BOTTOM 0x165C |
| 367 | #define DP_CNTL 0x16C0 | 367 | #define DP_CNTL 0x16C0 |
| 368 | #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 | 368 | #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 |
| 369 | #define DP_DATATYPE 0x16C4 | 369 | #define DP_DATATYPE 0x16C4 |
| 370 | #define DP_MIX 0x16C8 | 370 | #define DP_MIX 0x16C8 |
| 371 | #define DP_WRITE_MSK 0x16CC | 371 | #define DP_WRITE_MSK 0x16CC |
| 372 | #define DP_XOP 0x17F8 | 372 | #define DP_XOP 0x17F8 |
| 373 | #define CLR_CMP_CLR_SRC 0x15C4 | 373 | #define CLR_CMP_CLR_SRC 0x15C4 |
| 374 | #define CLR_CMP_CLR_DST 0x15C8 | 374 | #define CLR_CMP_CLR_DST 0x15C8 |
| 375 | #define CLR_CMP_CNTL 0x15C0 | 375 | #define CLR_CMP_CNTL 0x15C0 |
| 376 | #define CLR_CMP_MSK 0x15CC | 376 | #define CLR_CMP_MSK 0x15CC |
| 377 | #define DSTCACHE_MODE 0x1710 | 377 | #define DSTCACHE_MODE 0x1710 |
| 378 | #define DSTCACHE_CTLSTAT 0x1714 | 378 | #define DSTCACHE_CTLSTAT 0x1714 |
| 379 | #define DEFAULT_PITCH_OFFSET 0x16E0 | 379 | #define DEFAULT_PITCH_OFFSET 0x16E0 |
| 380 | #define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 | 380 | #define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 |
| 381 | #define DEFAULT_SC_TOP_LEFT 0x16EC | 381 | #define DEFAULT_SC_TOP_LEFT 0x16EC |
| 382 | #define SRC_PITCH_OFFSET 0x1428 | 382 | #define SRC_PITCH_OFFSET 0x1428 |
| 383 | #define DST_PITCH_OFFSET 0x142C | 383 | #define DST_PITCH_OFFSET 0x142C |
| 384 | #define DP_GUI_MASTER_CNTL 0x146C | 384 | #define DP_GUI_MASTER_CNTL 0x146C |
| 385 | #define SC_TOP_LEFT 0x16EC | 385 | #define SC_TOP_LEFT 0x16EC |
| 386 | #define SC_BOTTOM_RIGHT 0x16F0 | 386 | #define SC_BOTTOM_RIGHT 0x16F0 |
| 387 | #define SRC_SC_BOTTOM_RIGHT 0x16F4 | 387 | #define SRC_SC_BOTTOM_RIGHT 0x16F4 |
| 388 | #define RB2D_DSTCACHE_MODE 0x3428 | 388 | #define RB2D_DSTCACHE_MODE 0x3428 |
| 389 | #define RB2D_DSTCACHE_CTLSTAT_broken 0x342C /* do not use */ | 389 | #define RB2D_DSTCACHE_CTLSTAT_broken 0x342C /* do not use */ |
| 390 | #define LVDS_GEN_CNTL 0x02d0 | 390 | #define LVDS_GEN_CNTL 0x02d0 |
| @@ -686,7 +686,7 @@ | |||
| 686 | #define VERT_FP_LOOP_STRETCH (0x7 << 28) | 686 | #define VERT_FP_LOOP_STRETCH (0x7 << 28) |
| 687 | #define VERT_STRETCH_RESERVED 0xf1000000 | 687 | #define VERT_STRETCH_RESERVED 0xf1000000 |
| 688 | 688 | ||
| 689 | /* DAC_CNTL bit constants */ | 689 | /* DAC_CNTL bit constants */ |
| 690 | #define DAC_8BIT_EN 0x00000100 | 690 | #define DAC_8BIT_EN 0x00000100 |
| 691 | #define DAC_4BPP_PIX_ORDER 0x00000200 | 691 | #define DAC_4BPP_PIX_ORDER 0x00000200 |
| 692 | #define DAC_CRC_EN 0x00080000 | 692 | #define DAC_CRC_EN 0x00080000 |
| @@ -700,7 +700,7 @@ | |||
| 700 | #define DAC_CMP_EN (1 << 3) | 700 | #define DAC_CMP_EN (1 << 3) |
| 701 | #define DAC_CMP_OUTPUT (1 << 7) | 701 | #define DAC_CMP_OUTPUT (1 << 7) |
| 702 | 702 | ||
| 703 | /* DAC_CNTL2 bit constants */ | 703 | /* DAC_CNTL2 bit constants */ |
| 704 | #define DAC2_EXPAND_MODE (1 << 14) | 704 | #define DAC2_EXPAND_MODE (1 << 14) |
| 705 | #define DAC2_CMP_EN (1 << 7) | 705 | #define DAC2_CMP_EN (1 << 7) |
| 706 | #define DAC2_PALETTE_ACCESS_CNTL (1 << 5) | 706 | #define DAC2_PALETTE_ACCESS_CNTL (1 << 5) |