diff options
author | Rusty Russell <rusty@rustcorp.com.au> | 2013-05-28 22:22:22 -0400 |
---|---|---|
committer | Rusty Russell <rusty@rustcorp.com.au> | 2015-01-21 00:58:51 -0500 |
commit | 71d70c266c84c4e708bb36b20d0c0a29af42821c (patch) | |
tree | 79ca624c10d7cbf85309617379d9ea21e0357988 /include/uapi | |
parent | ff31d2e28549c84d53252b3c36b6f0ba18b78697 (diff) |
virtio-pci: define layout for virtio 1.0
Based on patches by Michael S. Tsirkin <mst@redhat.com>, but I found it
hard to follow so changed to use structures which are more
self-documenting.
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/uapi')
-rw-r--r-- | include/uapi/linux/virtio_pci.h | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/include/uapi/linux/virtio_pci.h b/include/uapi/linux/virtio_pci.h index 509d630f04f4..4e054235358f 100644 --- a/include/uapi/linux/virtio_pci.h +++ b/include/uapi/linux/virtio_pci.h | |||
@@ -99,4 +99,66 @@ | |||
99 | /* Vector value used to disable MSI for queue */ | 99 | /* Vector value used to disable MSI for queue */ |
100 | #define VIRTIO_MSI_NO_VECTOR 0xffff | 100 | #define VIRTIO_MSI_NO_VECTOR 0xffff |
101 | 101 | ||
102 | #ifndef VIRTIO_PCI_NO_MODERN | ||
103 | |||
104 | /* IDs for different capabilities. Must all exist. */ | ||
105 | |||
106 | /* Common configuration */ | ||
107 | #define VIRTIO_PCI_CAP_COMMON_CFG 1 | ||
108 | /* Notifications */ | ||
109 | #define VIRTIO_PCI_CAP_NOTIFY_CFG 2 | ||
110 | /* ISR access */ | ||
111 | #define VIRTIO_PCI_CAP_ISR_CFG 3 | ||
112 | /* Device specific confiuration */ | ||
113 | #define VIRTIO_PCI_CAP_DEVICE_CFG 4 | ||
114 | |||
115 | /* This is the PCI capability header: */ | ||
116 | struct virtio_pci_cap { | ||
117 | __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ | ||
118 | __u8 cap_next; /* Generic PCI field: next ptr. */ | ||
119 | __u8 cap_len; /* Generic PCI field: capability length */ | ||
120 | __u8 type_and_bar; /* Upper 3 bits: bar. | ||
121 | * Lower 3 is VIRTIO_PCI_CAP_*_CFG. */ | ||
122 | __le32 offset; /* Offset within bar. */ | ||
123 | __le32 length; /* Length. */ | ||
124 | }; | ||
125 | |||
126 | #define VIRTIO_PCI_CAP_BAR_SHIFT 5 | ||
127 | #define VIRTIO_PCI_CAP_BAR_MASK 0x7 | ||
128 | #define VIRTIO_PCI_CAP_TYPE_SHIFT 0 | ||
129 | #define VIRTIO_PCI_CAP_TYPE_MASK 0x7 | ||
130 | |||
131 | struct virtio_pci_notify_cap { | ||
132 | struct virtio_pci_cap cap; | ||
133 | __le32 notify_off_multiplier; /* Multiplier for queue_notify_off. */ | ||
134 | }; | ||
135 | |||
136 | /* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */ | ||
137 | struct virtio_pci_common_cfg { | ||
138 | /* About the whole device. */ | ||
139 | __le32 device_feature_select; /* read-write */ | ||
140 | __le32 device_feature; /* read-only */ | ||
141 | __le32 guest_feature_select; /* read-write */ | ||
142 | __le32 guest_feature; /* read-write */ | ||
143 | __le16 msix_config; /* read-write */ | ||
144 | __le16 num_queues; /* read-only */ | ||
145 | __u8 device_status; /* read-write */ | ||
146 | __u8 config_generation; /* read-only */ | ||
147 | |||
148 | /* About a specific virtqueue. */ | ||
149 | __le16 queue_select; /* read-write */ | ||
150 | __le16 queue_size; /* read-write, power of 2. */ | ||
151 | __le16 queue_msix_vector; /* read-write */ | ||
152 | __le16 queue_enable; /* read-write */ | ||
153 | __le16 queue_notify_off; /* read-only */ | ||
154 | __le32 queue_desc_lo; /* read-write */ | ||
155 | __le32 queue_desc_hi; /* read-write */ | ||
156 | __le32 queue_avail_lo; /* read-write */ | ||
157 | __le32 queue_avail_hi; /* read-write */ | ||
158 | __le32 queue_used_lo; /* read-write */ | ||
159 | __le32 queue_used_hi; /* read-write */ | ||
160 | }; | ||
161 | |||
162 | #endif /* VIRTIO_PCI_NO_MODERN */ | ||
163 | |||
102 | #endif | 164 | #endif |