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authorDave Airlie <airlied@redhat.com>2015-04-13 03:28:57 -0400
committerDave Airlie <airlied@redhat.com>2015-04-13 03:28:57 -0400
commit1d2add28edd268a8290801ccf46b37f6d5239cdb (patch)
tree534e967b692f816434c00de0893e1089d425ae92 /include/uapi
parentbb1dc08c94ead1b98e750caf535422f79363c1a2 (diff)
parent5e501ed7253b369a8a9ec553c35238a3d6808f28 (diff)
Merge tag 'imx-drm-next-2015-03-31' of git://git.pengutronix.de/git/pza/linux into drm-next
imx-drm changes to use media bus formats and LDB drm_panel support - Add media bus formats needed by imx-drm - Switch to use media bus formats to describe the pixel format on the internal parallel bus between display interface and encoders - Some preparations for TV Output via TVEv2 on i.MX5 - Add drm_panel support to the i.MX LVDS driver, allow to determine the bus pixel format from the panel descriptor. * tag 'imx-drm-next-2015-03-31' of git://git.pengutronix.de/git/pza/linux: drm/imx: imx-ldb: allow to determine bus format from the connected panel drm/imx: imx-ldb: reset display clock input when disabling LVDS drm/imx: imx-ldb: add drm_panel support drm/imx: consolidate bus format variable names drm/imx: switch to use media bus formats Add RGB666_1X24_CPADHI media bus format Add YUV8_1X24 media bus format Add BGR888_1X24 and GBR888_1X24 media bus formats Add LVDS RGB media bus formats Add RGB444_1X12 and RGB565_1X16 media bus formats drm/imx: ipuv3-crtc: Allow to divide DI clock from TVEv2 drm/imx: Add support for interlaced scanout
Diffstat (limited to 'include/uapi')
-rw-r--r--include/uapi/linux/media-bus-format.h13
1 files changed, 11 insertions, 2 deletions
diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h
index 23b40908be30..83ea46f4be51 100644
--- a/include/uapi/linux/media-bus-format.h
+++ b/include/uapi/linux/media-bus-format.h
@@ -33,22 +33,30 @@
33 33
34#define MEDIA_BUS_FMT_FIXED 0x0001 34#define MEDIA_BUS_FMT_FIXED 0x0001
35 35
36/* RGB - next is 0x100e */ 36/* RGB - next is 0x1016 */
37#define MEDIA_BUS_FMT_RGB444_1X12 0x100e
37#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 38#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
38#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 39#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
39#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003 40#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003
40#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004 41#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004
42#define MEDIA_BUS_FMT_RGB565_1X16 0x100f
41#define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005 43#define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005
42#define MEDIA_BUS_FMT_BGR565_2X8_LE 0x1006 44#define MEDIA_BUS_FMT_BGR565_2X8_LE 0x1006
43#define MEDIA_BUS_FMT_RGB565_2X8_BE 0x1007 45#define MEDIA_BUS_FMT_RGB565_2X8_BE 0x1007
44#define MEDIA_BUS_FMT_RGB565_2X8_LE 0x1008 46#define MEDIA_BUS_FMT_RGB565_2X8_LE 0x1008
45#define MEDIA_BUS_FMT_RGB666_1X18 0x1009 47#define MEDIA_BUS_FMT_RGB666_1X18 0x1009
48#define MEDIA_BUS_FMT_RGB666_1X24_CPADHI 0x1015
49#define MEDIA_BUS_FMT_RGB666_1X7X3_SPWG 0x1010
50#define MEDIA_BUS_FMT_BGR888_1X24 0x1013
51#define MEDIA_BUS_FMT_GBR888_1X24 0x1014
46#define MEDIA_BUS_FMT_RGB888_1X24 0x100a 52#define MEDIA_BUS_FMT_RGB888_1X24 0x100a
47#define MEDIA_BUS_FMT_RGB888_2X12_BE 0x100b 53#define MEDIA_BUS_FMT_RGB888_2X12_BE 0x100b
48#define MEDIA_BUS_FMT_RGB888_2X12_LE 0x100c 54#define MEDIA_BUS_FMT_RGB888_2X12_LE 0x100c
55#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011
56#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012
49#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d 57#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d
50 58
51/* YUV (including grey) - next is 0x2024 */ 59/* YUV (including grey) - next is 0x2025 */
52#define MEDIA_BUS_FMT_Y8_1X8 0x2001 60#define MEDIA_BUS_FMT_Y8_1X8 0x2001
53#define MEDIA_BUS_FMT_UV8_1X8 0x2015 61#define MEDIA_BUS_FMT_UV8_1X8 0x2015
54#define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002 62#define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002
@@ -74,6 +82,7 @@
74#define MEDIA_BUS_FMT_VYUY10_1X20 0x201b 82#define MEDIA_BUS_FMT_VYUY10_1X20 0x201b
75#define MEDIA_BUS_FMT_YUYV10_1X20 0x200d 83#define MEDIA_BUS_FMT_YUYV10_1X20 0x200d
76#define MEDIA_BUS_FMT_YVYU10_1X20 0x200e 84#define MEDIA_BUS_FMT_YVYU10_1X20 0x200e
85#define MEDIA_BUS_FMT_YUV8_1X24 0x2024
77#define MEDIA_BUS_FMT_YUV10_1X30 0x2016 86#define MEDIA_BUS_FMT_YUV10_1X30 0x2016
78#define MEDIA_BUS_FMT_AYUV8_1X32 0x2017 87#define MEDIA_BUS_FMT_AYUV8_1X32 0x2017
79#define MEDIA_BUS_FMT_UYVY12_2X12 0x201c 88#define MEDIA_BUS_FMT_UYVY12_2X12 0x201c