drm/exynos: add ipp subsystem

This patch adds Image Post Processing(IPP) support for exynos drm driver.

IPP supports image scaler/rotator and input/output DMA operations
using IPP subsystem framework to control FIMC, Rotator and GSC hardware
and supports some user interfaces for user side.

And each IPP-based drivers support Memory to Memory operations
with various converting. And in case of FIMC hardware, it also supports
Writeback and Display output operations through local path.

Features:
- Memory to Memory operation support.
- Various pixel formats support.
- Image scaling support.
- Color Space Conversion support.
- Image crop operation support.
- Rotate operation support to 90, 180 or 270 degree.
- Flip operation support to vertical, horizontal or both.
- Writeback operation support to display blended image of FIMD fifo on screen

A summary to IPP Subsystem operations:
First of all, user should get property capabilities from IPP subsystem
and set these properties to hardware registers for desired operations.
The properties could be pixel format, position, rotation degree and
flip operation.

And next, user should set source and destination buffer data using
DRM_EXYNOS_IPP_QUEUE_BUF ioctl command with gem handles to source and
destinition buffers.

And next, user can control user-desired hardware with desired operations
such as play, stop, pause and resume controls.

And finally, user can aware of dma operation completion and also get
destination buffer that it contains user-desried result through dequeue
command.

IOCTL commands:
- DRM_EXYNOS_IPP_GET_PROPERTY
  . get ipp driver capabilitis and id.
- DRM_EXYNOS_IPP_SET_PROPERTY
  . set format, position, rotation, flip to source and destination buffers
- DRM_EXYNOS_IPP_QUEUE_BUF
  . enqueue/dequeue buffer and make event list.
- DRM_EXYNOS_IPP_CMD_CTRL
  . play/stop/pause/resume control.

Event:
- DRM_EXYNOS_IPP_EVENT
  . a event to notify dma operation completion to user side.

Basic control flow:
Open -> Get properties -> User choose desired IPP sub driver(FIMC, Rotator
or GSCALER) -> Set Property -> Create gem handle -> Enqueue to source and
destination buffers -> Command control(Play) -> Event is notified to User
-> User gets destinition buffer complated -> (Enqueue to source and
destination buffers -> Event is notified to User) * N -> Queue/Dequeue to
source and destination buffers -> Command control(Stop) -> Free gem handle
-> Close

Changelog v1 ~ v5:
- added comments, code fixups and cleanups.

Signed-off-by: Eunchul Kim <chulspro.kim@samsung.com>
Signed-off-by: Jinyoung Jeon <jy0.jeon@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

1 files changed, 190 insertions, 0 deletions

diff --git a/include/uapi/drm/exynos_drm.h b/include/uapi/drm/exynos_drm.h
index 49f010f2b27f..e7f52c334005 100644
--- a/include/uapi/drm/exynos_drm.h
+++ b/include/uapi/drm/exynos_drm.h
@@ -163,6 +163,170 @@ struct drm_exynos_g2d_exec {
         __u64                                   async;
 };
 
+enum drm_exynos_ops_id {
+        EXYNOS_DRM_OPS_SRC,
+        EXYNOS_DRM_OPS_DST,
+        EXYNOS_DRM_OPS_MAX,
+};
+
+struct drm_exynos_sz {
+        __u32   hsize;
+        __u32   vsize;
+};
+
+struct drm_exynos_pos {
+        __u32   x;
+        __u32   y;
+        __u32   w;
+        __u32   h;
+};
+
+enum drm_exynos_flip {
+        EXYNOS_DRM_FLIP_NONE = (0 << 0),
+        EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
+        EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
+};
+
+enum drm_exynos_degree {
+        EXYNOS_DRM_DEGREE_0,
+        EXYNOS_DRM_DEGREE_90,
+        EXYNOS_DRM_DEGREE_180,
+        EXYNOS_DRM_DEGREE_270,
+};
+
+enum drm_exynos_planer {
+        EXYNOS_DRM_PLANAR_Y,
+        EXYNOS_DRM_PLANAR_CB,
+        EXYNOS_DRM_PLANAR_CR,
+        EXYNOS_DRM_PLANAR_MAX,
+};
+
+/**
+ * A structure for ipp supported property list.
+ *
+ * @version: version of this structure.
+ * @ipp_id: id of ipp driver.
+ * @count: count of ipp driver.
+ * @writeback: flag of writeback supporting.
+ * @flip: flag of flip supporting.
+ * @degree: flag of degree information.
+ * @csc: flag of csc supporting.
+ * @crop: flag of crop supporting.
+ * @scale: flag of scale supporting.
+ * @refresh_min: min hz of refresh.
+ * @refresh_max: max hz of refresh.
+ * @crop_min: crop min resolution.
+ * @crop_max: crop max resolution.
+ * @scale_min: scale min resolution.
+ * @scale_max: scale max resolution.
+ */
+struct drm_exynos_ipp_prop_list {
+        __u32   version;
+        __u32   ipp_id;
+        __u32   count;
+        __u32   writeback;
+        __u32   flip;
+        __u32   degree;
+        __u32   csc;
+        __u32   crop;
+        __u32   scale;
+        __u32   refresh_min;
+        __u32   refresh_max;
+        __u32   reserved;
+        struct drm_exynos_sz    crop_min;
+        struct drm_exynos_sz    crop_max;
+        struct drm_exynos_sz    scale_min;
+        struct drm_exynos_sz    scale_max;
+};
+
+/**
+ * A structure for ipp config.
+ *
+ * @ops_id: property of operation directions.
+ * @flip: property of mirror, flip.
+ * @degree: property of rotation degree.
+ * @fmt: property of image format.
+ * @sz: property of image size.
+ * @pos: property of image position(src-cropped,dst-scaler).
+ */
+struct drm_exynos_ipp_config {
+        enum drm_exynos_ops_id ops_id;
+        enum drm_exynos_flip    flip;
+        enum drm_exynos_degree  degree;
+        __u32   fmt;
+        struct drm_exynos_sz    sz;
+        struct drm_exynos_pos   pos;
+};
+
+enum drm_exynos_ipp_cmd {
+        IPP_CMD_NONE,
+        IPP_CMD_M2M,
+        IPP_CMD_WB,
+        IPP_CMD_OUTPUT,
+        IPP_CMD_MAX,
+};
+
+/**
+ * A structure for ipp property.
+ *
+ * @config: source, destination config.
+ * @cmd: definition of command.
+ * @ipp_id: id of ipp driver.
+ * @prop_id: id of property.
+ * @refresh_rate: refresh rate.
+ */
+struct drm_exynos_ipp_property {
+        struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
+        enum drm_exynos_ipp_cmd cmd;
+        __u32   ipp_id;
+        __u32   prop_id;
+        __u32   refresh_rate;
+};
+
+enum drm_exynos_ipp_buf_type {
+        IPP_BUF_ENQUEUE,
+        IPP_BUF_DEQUEUE,
+};
+
+/**
+ * A structure for ipp buffer operations.
+ *
+ * @ops_id: operation directions.
+ * @buf_type: definition of buffer.
+ * @prop_id: id of property.
+ * @buf_id: id of buffer.
+ * @handle: Y, Cb, Cr each planar handle.
+ * @user_data: user data.
+ */
+struct drm_exynos_ipp_queue_buf {
+        enum drm_exynos_ops_id  ops_id;
+        enum drm_exynos_ipp_buf_type    buf_type;
+        __u32   prop_id;
+        __u32   buf_id;
+        __u32   handle[EXYNOS_DRM_PLANAR_MAX];
+        __u32   reserved;
+        __u64   user_data;
+};
+
+enum drm_exynos_ipp_ctrl {
+        IPP_CTRL_PLAY,
+        IPP_CTRL_STOP,
+        IPP_CTRL_PAUSE,
+        IPP_CTRL_RESUME,
+        IPP_CTRL_MAX,
+};
+
+/**
+ * A structure for ipp start/stop operations.
+ *
+ * @prop_id: id of property.
+ * @ctrl: definition of control.
+ */
+struct drm_exynos_ipp_cmd_ctrl {
+        __u32   prop_id;
+        enum drm_exynos_ipp_ctrl        ctrl;
+};
+
 #define DRM_EXYNOS_GEM_CREATE           0x00
 #define DRM_EXYNOS_GEM_MAP_OFFSET       0x01
 #define DRM_EXYNOS_GEM_MMAP             0x02
@@ -175,6 +339,12 @@ struct drm_exynos_g2d_exec {
 #define DRM_EXYNOS_G2D_SET_CMDLIST      0x21
 #define DRM_EXYNOS_G2D_EXEC             0x22
 
+/* IPP - Image Post Processing */
+#define DRM_EXYNOS_IPP_GET_PROPERTY     0x30
+#define DRM_EXYNOS_IPP_SET_PROPERTY     0x31
+#define DRM_EXYNOS_IPP_QUEUE_BUF        0x32
+#define DRM_EXYNOS_IPP_CMD_CTRL 0x33
+
 #define DRM_IOCTL_EXYNOS_GEM_CREATE             DRM_IOWR(DRM_COMMAND_BASE + \
                 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
 
@@ -197,8 +367,18 @@ struct drm_exynos_g2d_exec {
 #define DRM_IOCTL_EXYNOS_G2D_EXEC               DRM_IOWR(DRM_COMMAND_BASE + \
                 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
 
+#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY       DRM_IOWR(DRM_COMMAND_BASE + \
+                DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
+#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY       DRM_IOWR(DRM_COMMAND_BASE + \
+                DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
+#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF  DRM_IOWR(DRM_COMMAND_BASE + \
+                DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
+#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL           DRM_IOWR(DRM_COMMAND_BASE + \
+                DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
+
 /* EXYNOS specific events */
 #define DRM_EXYNOS_G2D_EVENT            0x80000000
+#define DRM_EXYNOS_IPP_EVENT            0x80000001
 
 struct drm_exynos_g2d_event {
         struct drm_event        base;
@@ -209,4 +389,14 @@ struct drm_exynos_g2d_event {
         __u32                   reserved;
 };
 
+struct drm_exynos_ipp_event {
+        struct drm_event        base;
+        __u64                   user_data;
+        __u32                   tv_sec;
+        __u32                   tv_usec;
+        __u32                   prop_id;
+        __u32                   reserved;
+        __u32                   buf_id[EXYNOS_DRM_OPS_MAX];
+};
+
 #endif /* _UAPI_EXYNOS_DRM_H_ */