diff options
author | Takashi Iwai <tiwai@suse.de> | 2012-07-19 02:21:40 -0400 |
---|---|---|
committer | Takashi Iwai <tiwai@suse.de> | 2012-07-19 02:21:57 -0400 |
commit | 1558eb838ff502faafacf26b6a711dbaae796009 (patch) | |
tree | 8049ea20a214033369725ed58b8b4a3ca4110887 /include/sound | |
parent | 4609ed6b1f0ab9f11a9d0361573b53d9d057c440 (diff) | |
parent | 81fcb170852d58d7ebd8101a8ef970c82056426e (diff) |
Merge branch 'topic/pm-convert' into for-next
This merges the changes for converting to new PM ops for platform
and some other drivers.
Also move some header files to local places from the public
include/sound.
Diffstat (limited to 'include/sound')
-rw-r--r-- | include/sound/cs46xx.h | 1745 | ||||
-rw-r--r-- | include/sound/cs46xx_dsp_scb_types.h | 1213 | ||||
-rw-r--r-- | include/sound/cs46xx_dsp_spos.h | 234 | ||||
-rw-r--r-- | include/sound/cs46xx_dsp_task_types.h | 252 | ||||
-rw-r--r-- | include/sound/trident.h | 445 | ||||
-rw-r--r-- | include/sound/vx_core.h | 2 | ||||
-rw-r--r-- | include/sound/ymfpci.h | 390 |
7 files changed, 1 insertions, 4280 deletions
diff --git a/include/sound/cs46xx.h b/include/sound/cs46xx.h deleted file mode 100644 index e3005a674a24..000000000000 --- a/include/sound/cs46xx.h +++ /dev/null | |||
@@ -1,1745 +0,0 @@ | |||
1 | #ifndef __SOUND_CS46XX_H | ||
2 | #define __SOUND_CS46XX_H | ||
3 | |||
4 | /* | ||
5 | * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, | ||
6 | * Cirrus Logic, Inc. | ||
7 | * Definitions for Cirrus Logic CS46xx chips | ||
8 | * | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * This program is distributed in the hope that it will be useful, | ||
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
18 | * GNU General Public License for more details. | ||
19 | * | ||
20 | * You should have received a copy of the GNU General Public License | ||
21 | * along with this program; if not, write to the Free Software | ||
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
23 | * | ||
24 | */ | ||
25 | |||
26 | #include "pcm.h" | ||
27 | #include "pcm-indirect.h" | ||
28 | #include "rawmidi.h" | ||
29 | #include "ac97_codec.h" | ||
30 | #include "cs46xx_dsp_spos.h" | ||
31 | |||
32 | /* | ||
33 | * Direct registers | ||
34 | */ | ||
35 | |||
36 | /* | ||
37 | * The following define the offsets of the registers accessed via base address | ||
38 | * register zero on the CS46xx part. | ||
39 | */ | ||
40 | #define BA0_HISR 0x00000000 | ||
41 | #define BA0_HSR0 0x00000004 | ||
42 | #define BA0_HICR 0x00000008 | ||
43 | #define BA0_DMSR 0x00000100 | ||
44 | #define BA0_HSAR 0x00000110 | ||
45 | #define BA0_HDAR 0x00000114 | ||
46 | #define BA0_HDMR 0x00000118 | ||
47 | #define BA0_HDCR 0x0000011C | ||
48 | #define BA0_PFMC 0x00000200 | ||
49 | #define BA0_PFCV1 0x00000204 | ||
50 | #define BA0_PFCV2 0x00000208 | ||
51 | #define BA0_PCICFG00 0x00000300 | ||
52 | #define BA0_PCICFG04 0x00000304 | ||
53 | #define BA0_PCICFG08 0x00000308 | ||
54 | #define BA0_PCICFG0C 0x0000030C | ||
55 | #define BA0_PCICFG10 0x00000310 | ||
56 | #define BA0_PCICFG14 0x00000314 | ||
57 | #define BA0_PCICFG18 0x00000318 | ||
58 | #define BA0_PCICFG1C 0x0000031C | ||
59 | #define BA0_PCICFG20 0x00000320 | ||
60 | #define BA0_PCICFG24 0x00000324 | ||
61 | #define BA0_PCICFG28 0x00000328 | ||
62 | #define BA0_PCICFG2C 0x0000032C | ||
63 | #define BA0_PCICFG30 0x00000330 | ||
64 | #define BA0_PCICFG34 0x00000334 | ||
65 | #define BA0_PCICFG38 0x00000338 | ||
66 | #define BA0_PCICFG3C 0x0000033C | ||
67 | #define BA0_CLKCR1 0x00000400 | ||
68 | #define BA0_CLKCR2 0x00000404 | ||
69 | #define BA0_PLLM 0x00000408 | ||
70 | #define BA0_PLLCC 0x0000040C | ||
71 | #define BA0_FRR 0x00000410 | ||
72 | #define BA0_CFL1 0x00000414 | ||
73 | #define BA0_CFL2 0x00000418 | ||
74 | #define BA0_SERMC1 0x00000420 | ||
75 | #define BA0_SERMC2 0x00000424 | ||
76 | #define BA0_SERC1 0x00000428 | ||
77 | #define BA0_SERC2 0x0000042C | ||
78 | #define BA0_SERC3 0x00000430 | ||
79 | #define BA0_SERC4 0x00000434 | ||
80 | #define BA0_SERC5 0x00000438 | ||
81 | #define BA0_SERBSP 0x0000043C | ||
82 | #define BA0_SERBST 0x00000440 | ||
83 | #define BA0_SERBCM 0x00000444 | ||
84 | #define BA0_SERBAD 0x00000448 | ||
85 | #define BA0_SERBCF 0x0000044C | ||
86 | #define BA0_SERBWP 0x00000450 | ||
87 | #define BA0_SERBRP 0x00000454 | ||
88 | #ifndef NO_CS4612 | ||
89 | #define BA0_ASER_FADDR 0x00000458 | ||
90 | #endif | ||
91 | #define BA0_ACCTL 0x00000460 | ||
92 | #define BA0_ACSTS 0x00000464 | ||
93 | #define BA0_ACOSV 0x00000468 | ||
94 | #define BA0_ACCAD 0x0000046C | ||
95 | #define BA0_ACCDA 0x00000470 | ||
96 | #define BA0_ACISV 0x00000474 | ||
97 | #define BA0_ACSAD 0x00000478 | ||
98 | #define BA0_ACSDA 0x0000047C | ||
99 | #define BA0_JSPT 0x00000480 | ||
100 | #define BA0_JSCTL 0x00000484 | ||
101 | #define BA0_JSC1 0x00000488 | ||
102 | #define BA0_JSC2 0x0000048C | ||
103 | #define BA0_MIDCR 0x00000490 | ||
104 | #define BA0_MIDSR 0x00000494 | ||
105 | #define BA0_MIDWP 0x00000498 | ||
106 | #define BA0_MIDRP 0x0000049C | ||
107 | #define BA0_JSIO 0x000004A0 | ||
108 | #ifndef NO_CS4612 | ||
109 | #define BA0_ASER_MASTER 0x000004A4 | ||
110 | #endif | ||
111 | #define BA0_CFGI 0x000004B0 | ||
112 | #define BA0_SSVID 0x000004B4 | ||
113 | #define BA0_GPIOR 0x000004B8 | ||
114 | #ifndef NO_CS4612 | ||
115 | #define BA0_EGPIODR 0x000004BC | ||
116 | #define BA0_EGPIOPTR 0x000004C0 | ||
117 | #define BA0_EGPIOTR 0x000004C4 | ||
118 | #define BA0_EGPIOWR 0x000004C8 | ||
119 | #define BA0_EGPIOSR 0x000004CC | ||
120 | #define BA0_SERC6 0x000004D0 | ||
121 | #define BA0_SERC7 0x000004D4 | ||
122 | #define BA0_SERACC 0x000004D8 | ||
123 | #define BA0_ACCTL2 0x000004E0 | ||
124 | #define BA0_ACSTS2 0x000004E4 | ||
125 | #define BA0_ACOSV2 0x000004E8 | ||
126 | #define BA0_ACCAD2 0x000004EC | ||
127 | #define BA0_ACCDA2 0x000004F0 | ||
128 | #define BA0_ACISV2 0x000004F4 | ||
129 | #define BA0_ACSAD2 0x000004F8 | ||
130 | #define BA0_ACSDA2 0x000004FC | ||
131 | #define BA0_IOTAC0 0x00000500 | ||
132 | #define BA0_IOTAC1 0x00000504 | ||
133 | #define BA0_IOTAC2 0x00000508 | ||
134 | #define BA0_IOTAC3 0x0000050C | ||
135 | #define BA0_IOTAC4 0x00000510 | ||
136 | #define BA0_IOTAC5 0x00000514 | ||
137 | #define BA0_IOTAC6 0x00000518 | ||
138 | #define BA0_IOTAC7 0x0000051C | ||
139 | #define BA0_IOTAC8 0x00000520 | ||
140 | #define BA0_IOTAC9 0x00000524 | ||
141 | #define BA0_IOTAC10 0x00000528 | ||
142 | #define BA0_IOTAC11 0x0000052C | ||
143 | #define BA0_IOTFR0 0x00000540 | ||
144 | #define BA0_IOTFR1 0x00000544 | ||
145 | #define BA0_IOTFR2 0x00000548 | ||
146 | #define BA0_IOTFR3 0x0000054C | ||
147 | #define BA0_IOTFR4 0x00000550 | ||
148 | #define BA0_IOTFR5 0x00000554 | ||
149 | #define BA0_IOTFR6 0x00000558 | ||
150 | #define BA0_IOTFR7 0x0000055C | ||
151 | #define BA0_IOTFIFO 0x00000580 | ||
152 | #define BA0_IOTRRD 0x00000584 | ||
153 | #define BA0_IOTFP 0x00000588 | ||
154 | #define BA0_IOTCR 0x0000058C | ||
155 | #define BA0_DPCID 0x00000590 | ||
156 | #define BA0_DPCIA 0x00000594 | ||
157 | #define BA0_DPCIC 0x00000598 | ||
158 | #define BA0_PCPCIR 0x00000600 | ||
159 | #define BA0_PCPCIG 0x00000604 | ||
160 | #define BA0_PCPCIEN 0x00000608 | ||
161 | #define BA0_EPCIPMC 0x00000610 | ||
162 | #endif | ||
163 | |||
164 | /* | ||
165 | * The following define the offsets of the registers and memories accessed via | ||
166 | * base address register one on the CS46xx part. | ||
167 | */ | ||
168 | #define BA1_SP_DMEM0 0x00000000 | ||
169 | #define BA1_SP_DMEM1 0x00010000 | ||
170 | #define BA1_SP_PMEM 0x00020000 | ||
171 | #define BA1_SP_REG 0x00030000 | ||
172 | #define BA1_SPCR 0x00030000 | ||
173 | #define BA1_DREG 0x00030004 | ||
174 | #define BA1_DSRWP 0x00030008 | ||
175 | #define BA1_TWPR 0x0003000C | ||
176 | #define BA1_SPWR 0x00030010 | ||
177 | #define BA1_SPIR 0x00030014 | ||
178 | #define BA1_FGR1 0x00030020 | ||
179 | #define BA1_SPCS 0x00030028 | ||
180 | #define BA1_SDSR 0x0003002C | ||
181 | #define BA1_FRMT 0x00030030 | ||
182 | #define BA1_FRCC 0x00030034 | ||
183 | #define BA1_FRSC 0x00030038 | ||
184 | #define BA1_OMNI_MEM 0x000E0000 | ||
185 | |||
186 | |||
187 | /* | ||
188 | * The following defines are for the flags in the host interrupt status | ||
189 | * register. | ||
190 | */ | ||
191 | #define HISR_VC_MASK 0x0000FFFF | ||
192 | #define HISR_VC0 0x00000001 | ||
193 | #define HISR_VC1 0x00000002 | ||
194 | #define HISR_VC2 0x00000004 | ||
195 | #define HISR_VC3 0x00000008 | ||
196 | #define HISR_VC4 0x00000010 | ||
197 | #define HISR_VC5 0x00000020 | ||
198 | #define HISR_VC6 0x00000040 | ||
199 | #define HISR_VC7 0x00000080 | ||
200 | #define HISR_VC8 0x00000100 | ||
201 | #define HISR_VC9 0x00000200 | ||
202 | #define HISR_VC10 0x00000400 | ||
203 | #define HISR_VC11 0x00000800 | ||
204 | #define HISR_VC12 0x00001000 | ||
205 | #define HISR_VC13 0x00002000 | ||
206 | #define HISR_VC14 0x00004000 | ||
207 | #define HISR_VC15 0x00008000 | ||
208 | #define HISR_INT0 0x00010000 | ||
209 | #define HISR_INT1 0x00020000 | ||
210 | #define HISR_DMAI 0x00040000 | ||
211 | #define HISR_FROVR 0x00080000 | ||
212 | #define HISR_MIDI 0x00100000 | ||
213 | #ifdef NO_CS4612 | ||
214 | #define HISR_RESERVED 0x0FE00000 | ||
215 | #else | ||
216 | #define HISR_SBINT 0x00200000 | ||
217 | #define HISR_RESERVED 0x0FC00000 | ||
218 | #endif | ||
219 | #define HISR_H0P 0x40000000 | ||
220 | #define HISR_INTENA 0x80000000 | ||
221 | |||
222 | /* | ||
223 | * The following defines are for the flags in the host signal register 0. | ||
224 | */ | ||
225 | #define HSR0_VC_MASK 0xFFFFFFFF | ||
226 | #define HSR0_VC16 0x00000001 | ||
227 | #define HSR0_VC17 0x00000002 | ||
228 | #define HSR0_VC18 0x00000004 | ||
229 | #define HSR0_VC19 0x00000008 | ||
230 | #define HSR0_VC20 0x00000010 | ||
231 | #define HSR0_VC21 0x00000020 | ||
232 | #define HSR0_VC22 0x00000040 | ||
233 | #define HSR0_VC23 0x00000080 | ||
234 | #define HSR0_VC24 0x00000100 | ||
235 | #define HSR0_VC25 0x00000200 | ||
236 | #define HSR0_VC26 0x00000400 | ||
237 | #define HSR0_VC27 0x00000800 | ||
238 | #define HSR0_VC28 0x00001000 | ||
239 | #define HSR0_VC29 0x00002000 | ||
240 | #define HSR0_VC30 0x00004000 | ||
241 | #define HSR0_VC31 0x00008000 | ||
242 | #define HSR0_VC32 0x00010000 | ||
243 | #define HSR0_VC33 0x00020000 | ||
244 | #define HSR0_VC34 0x00040000 | ||
245 | #define HSR0_VC35 0x00080000 | ||
246 | #define HSR0_VC36 0x00100000 | ||
247 | #define HSR0_VC37 0x00200000 | ||
248 | #define HSR0_VC38 0x00400000 | ||
249 | #define HSR0_VC39 0x00800000 | ||
250 | #define HSR0_VC40 0x01000000 | ||
251 | #define HSR0_VC41 0x02000000 | ||
252 | #define HSR0_VC42 0x04000000 | ||
253 | #define HSR0_VC43 0x08000000 | ||
254 | #define HSR0_VC44 0x10000000 | ||
255 | #define HSR0_VC45 0x20000000 | ||
256 | #define HSR0_VC46 0x40000000 | ||
257 | #define HSR0_VC47 0x80000000 | ||
258 | |||
259 | /* | ||
260 | * The following defines are for the flags in the host interrupt control | ||
261 | * register. | ||
262 | */ | ||
263 | #define HICR_IEV 0x00000001 | ||
264 | #define HICR_CHGM 0x00000002 | ||
265 | |||
266 | /* | ||
267 | * The following defines are for the flags in the DMA status register. | ||
268 | */ | ||
269 | #define DMSR_HP 0x00000001 | ||
270 | #define DMSR_HR 0x00000002 | ||
271 | #define DMSR_SP 0x00000004 | ||
272 | #define DMSR_SR 0x00000008 | ||
273 | |||
274 | /* | ||
275 | * The following defines are for the flags in the host DMA source address | ||
276 | * register. | ||
277 | */ | ||
278 | #define HSAR_HOST_ADDR_MASK 0xFFFFFFFF | ||
279 | #define HSAR_DSP_ADDR_MASK 0x0000FFFF | ||
280 | #define HSAR_MEMID_MASK 0x000F0000 | ||
281 | #define HSAR_MEMID_SP_DMEM0 0x00000000 | ||
282 | #define HSAR_MEMID_SP_DMEM1 0x00010000 | ||
283 | #define HSAR_MEMID_SP_PMEM 0x00020000 | ||
284 | #define HSAR_MEMID_SP_DEBUG 0x00030000 | ||
285 | #define HSAR_MEMID_OMNI_MEM 0x000E0000 | ||
286 | #define HSAR_END 0x40000000 | ||
287 | #define HSAR_ERR 0x80000000 | ||
288 | |||
289 | /* | ||
290 | * The following defines are for the flags in the host DMA destination address | ||
291 | * register. | ||
292 | */ | ||
293 | #define HDAR_HOST_ADDR_MASK 0xFFFFFFFF | ||
294 | #define HDAR_DSP_ADDR_MASK 0x0000FFFF | ||
295 | #define HDAR_MEMID_MASK 0x000F0000 | ||
296 | #define HDAR_MEMID_SP_DMEM0 0x00000000 | ||
297 | #define HDAR_MEMID_SP_DMEM1 0x00010000 | ||
298 | #define HDAR_MEMID_SP_PMEM 0x00020000 | ||
299 | #define HDAR_MEMID_SP_DEBUG 0x00030000 | ||
300 | #define HDAR_MEMID_OMNI_MEM 0x000E0000 | ||
301 | #define HDAR_END 0x40000000 | ||
302 | #define HDAR_ERR 0x80000000 | ||
303 | |||
304 | /* | ||
305 | * The following defines are for the flags in the host DMA control register. | ||
306 | */ | ||
307 | #define HDMR_AC_MASK 0x0000F000 | ||
308 | #define HDMR_AC_8_16 0x00001000 | ||
309 | #define HDMR_AC_M_S 0x00002000 | ||
310 | #define HDMR_AC_B_L 0x00004000 | ||
311 | #define HDMR_AC_S_U 0x00008000 | ||
312 | |||
313 | /* | ||
314 | * The following defines are for the flags in the host DMA control register. | ||
315 | */ | ||
316 | #define HDCR_COUNT_MASK 0x000003FF | ||
317 | #define HDCR_DONE 0x00004000 | ||
318 | #define HDCR_OPT 0x00008000 | ||
319 | #define HDCR_WBD 0x00400000 | ||
320 | #define HDCR_WBS 0x00800000 | ||
321 | #define HDCR_DMS_MASK 0x07000000 | ||
322 | #define HDCR_DMS_LINEAR 0x00000000 | ||
323 | #define HDCR_DMS_16_DWORDS 0x01000000 | ||
324 | #define HDCR_DMS_32_DWORDS 0x02000000 | ||
325 | #define HDCR_DMS_64_DWORDS 0x03000000 | ||
326 | #define HDCR_DMS_128_DWORDS 0x04000000 | ||
327 | #define HDCR_DMS_256_DWORDS 0x05000000 | ||
328 | #define HDCR_DMS_512_DWORDS 0x06000000 | ||
329 | #define HDCR_DMS_1024_DWORDS 0x07000000 | ||
330 | #define HDCR_DH 0x08000000 | ||
331 | #define HDCR_SMS_MASK 0x70000000 | ||
332 | #define HDCR_SMS_LINEAR 0x00000000 | ||
333 | #define HDCR_SMS_16_DWORDS 0x10000000 | ||
334 | #define HDCR_SMS_32_DWORDS 0x20000000 | ||
335 | #define HDCR_SMS_64_DWORDS 0x30000000 | ||
336 | #define HDCR_SMS_128_DWORDS 0x40000000 | ||
337 | #define HDCR_SMS_256_DWORDS 0x50000000 | ||
338 | #define HDCR_SMS_512_DWORDS 0x60000000 | ||
339 | #define HDCR_SMS_1024_DWORDS 0x70000000 | ||
340 | #define HDCR_SH 0x80000000 | ||
341 | #define HDCR_COUNT_SHIFT 0 | ||
342 | |||
343 | /* | ||
344 | * The following defines are for the flags in the performance monitor control | ||
345 | * register. | ||
346 | */ | ||
347 | #define PFMC_C1SS_MASK 0x0000001F | ||
348 | #define PFMC_C1EV 0x00000020 | ||
349 | #define PFMC_C1RS 0x00008000 | ||
350 | #define PFMC_C2SS_MASK 0x001F0000 | ||
351 | #define PFMC_C2EV 0x00200000 | ||
352 | #define PFMC_C2RS 0x80000000 | ||
353 | #define PFMC_C1SS_SHIFT 0 | ||
354 | #define PFMC_C2SS_SHIFT 16 | ||
355 | #define PFMC_BUS_GRANT 0 | ||
356 | #define PFMC_GRANT_AFTER_REQ 1 | ||
357 | #define PFMC_TRANSACTION 2 | ||
358 | #define PFMC_DWORD_TRANSFER 3 | ||
359 | #define PFMC_SLAVE_READ 4 | ||
360 | #define PFMC_SLAVE_WRITE 5 | ||
361 | #define PFMC_PREEMPTION 6 | ||
362 | #define PFMC_DISCONNECT_RETRY 7 | ||
363 | #define PFMC_INTERRUPT 8 | ||
364 | #define PFMC_BUS_OWNERSHIP 9 | ||
365 | #define PFMC_TRANSACTION_LAG 10 | ||
366 | #define PFMC_PCI_CLOCK 11 | ||
367 | #define PFMC_SERIAL_CLOCK 12 | ||
368 | #define PFMC_SP_CLOCK 13 | ||
369 | |||
370 | /* | ||
371 | * The following defines are for the flags in the performance counter value 1 | ||
372 | * register. | ||
373 | */ | ||
374 | #define PFCV1_PC1V_MASK 0xFFFFFFFF | ||
375 | #define PFCV1_PC1V_SHIFT 0 | ||
376 | |||
377 | /* | ||
378 | * The following defines are for the flags in the performance counter value 2 | ||
379 | * register. | ||
380 | */ | ||
381 | #define PFCV2_PC2V_MASK 0xFFFFFFFF | ||
382 | #define PFCV2_PC2V_SHIFT 0 | ||
383 | |||
384 | /* | ||
385 | * The following defines are for the flags in the clock control register 1. | ||
386 | */ | ||
387 | #define CLKCR1_OSCS 0x00000001 | ||
388 | #define CLKCR1_OSCP 0x00000002 | ||
389 | #define CLKCR1_PLLSS_MASK 0x0000000C | ||
390 | #define CLKCR1_PLLSS_SERIAL 0x00000000 | ||
391 | #define CLKCR1_PLLSS_CRYSTAL 0x00000004 | ||
392 | #define CLKCR1_PLLSS_PCI 0x00000008 | ||
393 | #define CLKCR1_PLLSS_RESERVED 0x0000000C | ||
394 | #define CLKCR1_PLLP 0x00000010 | ||
395 | #define CLKCR1_SWCE 0x00000020 | ||
396 | #define CLKCR1_PLLOS 0x00000040 | ||
397 | |||
398 | /* | ||
399 | * The following defines are for the flags in the clock control register 2. | ||
400 | */ | ||
401 | #define CLKCR2_PDIVS_MASK 0x0000000F | ||
402 | #define CLKCR2_PDIVS_1 0x00000001 | ||
403 | #define CLKCR2_PDIVS_2 0x00000002 | ||
404 | #define CLKCR2_PDIVS_4 0x00000004 | ||
405 | #define CLKCR2_PDIVS_7 0x00000007 | ||
406 | #define CLKCR2_PDIVS_8 0x00000008 | ||
407 | #define CLKCR2_PDIVS_16 0x00000000 | ||
408 | |||
409 | /* | ||
410 | * The following defines are for the flags in the PLL multiplier register. | ||
411 | */ | ||
412 | #define PLLM_MASK 0x000000FF | ||
413 | #define PLLM_SHIFT 0 | ||
414 | |||
415 | /* | ||
416 | * The following defines are for the flags in the PLL capacitor coefficient | ||
417 | * register. | ||
418 | */ | ||
419 | #define PLLCC_CDR_MASK 0x00000007 | ||
420 | #ifndef NO_CS4610 | ||
421 | #define PLLCC_CDR_240_350_MHZ 0x00000000 | ||
422 | #define PLLCC_CDR_184_265_MHZ 0x00000001 | ||
423 | #define PLLCC_CDR_144_205_MHZ 0x00000002 | ||
424 | #define PLLCC_CDR_111_160_MHZ 0x00000003 | ||
425 | #define PLLCC_CDR_87_123_MHZ 0x00000004 | ||
426 | #define PLLCC_CDR_67_96_MHZ 0x00000005 | ||
427 | #define PLLCC_CDR_52_74_MHZ 0x00000006 | ||
428 | #define PLLCC_CDR_45_58_MHZ 0x00000007 | ||
429 | #endif | ||
430 | #ifndef NO_CS4612 | ||
431 | #define PLLCC_CDR_271_398_MHZ 0x00000000 | ||
432 | #define PLLCC_CDR_227_330_MHZ 0x00000001 | ||
433 | #define PLLCC_CDR_167_239_MHZ 0x00000002 | ||
434 | #define PLLCC_CDR_150_215_MHZ 0x00000003 | ||
435 | #define PLLCC_CDR_107_154_MHZ 0x00000004 | ||
436 | #define PLLCC_CDR_98_140_MHZ 0x00000005 | ||
437 | #define PLLCC_CDR_73_104_MHZ 0x00000006 | ||
438 | #define PLLCC_CDR_63_90_MHZ 0x00000007 | ||
439 | #endif | ||
440 | #define PLLCC_LPF_MASK 0x000000F8 | ||
441 | #ifndef NO_CS4610 | ||
442 | #define PLLCC_LPF_23850_60000_KHZ 0x00000000 | ||
443 | #define PLLCC_LPF_7960_26290_KHZ 0x00000008 | ||
444 | #define PLLCC_LPF_4160_10980_KHZ 0x00000018 | ||
445 | #define PLLCC_LPF_1740_4580_KHZ 0x00000038 | ||
446 | #define PLLCC_LPF_724_1910_KHZ 0x00000078 | ||
447 | #define PLLCC_LPF_317_798_KHZ 0x000000F8 | ||
448 | #endif | ||
449 | #ifndef NO_CS4612 | ||
450 | #define PLLCC_LPF_25580_64530_KHZ 0x00000000 | ||
451 | #define PLLCC_LPF_14360_37270_KHZ 0x00000008 | ||
452 | #define PLLCC_LPF_6100_16020_KHZ 0x00000018 | ||
453 | #define PLLCC_LPF_2540_6690_KHZ 0x00000038 | ||
454 | #define PLLCC_LPF_1050_2780_KHZ 0x00000078 | ||
455 | #define PLLCC_LPF_450_1160_KHZ 0x000000F8 | ||
456 | #endif | ||
457 | |||
458 | /* | ||
459 | * The following defines are for the flags in the feature reporting register. | ||
460 | */ | ||
461 | #define FRR_FAB_MASK 0x00000003 | ||
462 | #define FRR_MASK_MASK 0x0000001C | ||
463 | #ifdef NO_CS4612 | ||
464 | #define FRR_CFOP_MASK 0x000000E0 | ||
465 | #else | ||
466 | #define FRR_CFOP_MASK 0x00000FE0 | ||
467 | #endif | ||
468 | #define FRR_CFOP_NOT_DVD 0x00000020 | ||
469 | #define FRR_CFOP_A3D 0x00000040 | ||
470 | #define FRR_CFOP_128_PIN 0x00000080 | ||
471 | #ifndef NO_CS4612 | ||
472 | #define FRR_CFOP_CS4280 0x00000800 | ||
473 | #endif | ||
474 | #define FRR_FAB_SHIFT 0 | ||
475 | #define FRR_MASK_SHIFT 2 | ||
476 | #define FRR_CFOP_SHIFT 5 | ||
477 | |||
478 | /* | ||
479 | * The following defines are for the flags in the configuration load 1 | ||
480 | * register. | ||
481 | */ | ||
482 | #define CFL1_CLOCK_SOURCE_MASK 0x00000003 | ||
483 | #define CFL1_CLOCK_SOURCE_CS423X 0x00000000 | ||
484 | #define CFL1_CLOCK_SOURCE_AC97 0x00000001 | ||
485 | #define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002 | ||
486 | #define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003 | ||
487 | #define CFL1_VALID_DATA_MASK 0x000000FF | ||
488 | |||
489 | /* | ||
490 | * The following defines are for the flags in the configuration load 2 | ||
491 | * register. | ||
492 | */ | ||
493 | #define CFL2_VALID_DATA_MASK 0x000000FF | ||
494 | |||
495 | /* | ||
496 | * The following defines are for the flags in the serial port master control | ||
497 | * register 1. | ||
498 | */ | ||
499 | #define SERMC1_MSPE 0x00000001 | ||
500 | #define SERMC1_PTC_MASK 0x0000000E | ||
501 | #define SERMC1_PTC_CS423X 0x00000000 | ||
502 | #define SERMC1_PTC_AC97 0x00000002 | ||
503 | #define SERMC1_PTC_DAC 0x00000004 | ||
504 | #define SERMC1_PLB 0x00000010 | ||
505 | #define SERMC1_XLB 0x00000020 | ||
506 | |||
507 | /* | ||
508 | * The following defines are for the flags in the serial port master control | ||
509 | * register 2. | ||
510 | */ | ||
511 | #define SERMC2_LROE 0x00000001 | ||
512 | #define SERMC2_MCOE 0x00000002 | ||
513 | #define SERMC2_MCDIV 0x00000004 | ||
514 | |||
515 | /* | ||
516 | * The following defines are for the flags in the serial port 1 configuration | ||
517 | * register. | ||
518 | */ | ||
519 | #define SERC1_SO1EN 0x00000001 | ||
520 | #define SERC1_SO1F_MASK 0x0000000E | ||
521 | #define SERC1_SO1F_CS423X 0x00000000 | ||
522 | #define SERC1_SO1F_AC97 0x00000002 | ||
523 | #define SERC1_SO1F_DAC 0x00000004 | ||
524 | #define SERC1_SO1F_SPDIF 0x00000006 | ||
525 | |||
526 | /* | ||
527 | * The following defines are for the flags in the serial port 2 configuration | ||
528 | * register. | ||
529 | */ | ||
530 | #define SERC2_SI1EN 0x00000001 | ||
531 | #define SERC2_SI1F_MASK 0x0000000E | ||
532 | #define SERC2_SI1F_CS423X 0x00000000 | ||
533 | #define SERC2_SI1F_AC97 0x00000002 | ||
534 | #define SERC2_SI1F_ADC 0x00000004 | ||
535 | #define SERC2_SI1F_SPDIF 0x00000006 | ||
536 | |||
537 | /* | ||
538 | * The following defines are for the flags in the serial port 3 configuration | ||
539 | * register. | ||
540 | */ | ||
541 | #define SERC3_SO2EN 0x00000001 | ||
542 | #define SERC3_SO2F_MASK 0x00000006 | ||
543 | #define SERC3_SO2F_DAC 0x00000000 | ||
544 | #define SERC3_SO2F_SPDIF 0x00000002 | ||
545 | |||
546 | /* | ||
547 | * The following defines are for the flags in the serial port 4 configuration | ||
548 | * register. | ||
549 | */ | ||
550 | #define SERC4_SO3EN 0x00000001 | ||
551 | #define SERC4_SO3F_MASK 0x00000006 | ||
552 | #define SERC4_SO3F_DAC 0x00000000 | ||
553 | #define SERC4_SO3F_SPDIF 0x00000002 | ||
554 | |||
555 | /* | ||
556 | * The following defines are for the flags in the serial port 5 configuration | ||
557 | * register. | ||
558 | */ | ||
559 | #define SERC5_SI2EN 0x00000001 | ||
560 | #define SERC5_SI2F_MASK 0x00000006 | ||
561 | #define SERC5_SI2F_ADC 0x00000000 | ||
562 | #define SERC5_SI2F_SPDIF 0x00000002 | ||
563 | |||
564 | /* | ||
565 | * The following defines are for the flags in the serial port backdoor sample | ||
566 | * pointer register. | ||
567 | */ | ||
568 | #define SERBSP_FSP_MASK 0x0000000F | ||
569 | #define SERBSP_FSP_SHIFT 0 | ||
570 | |||
571 | /* | ||
572 | * The following defines are for the flags in the serial port backdoor status | ||
573 | * register. | ||
574 | */ | ||
575 | #define SERBST_RRDY 0x00000001 | ||
576 | #define SERBST_WBSY 0x00000002 | ||
577 | |||
578 | /* | ||
579 | * The following defines are for the flags in the serial port backdoor command | ||
580 | * register. | ||
581 | */ | ||
582 | #define SERBCM_RDC 0x00000001 | ||
583 | #define SERBCM_WRC 0x00000002 | ||
584 | |||
585 | /* | ||
586 | * The following defines are for the flags in the serial port backdoor address | ||
587 | * register. | ||
588 | */ | ||
589 | #ifdef NO_CS4612 | ||
590 | #define SERBAD_FAD_MASK 0x000000FF | ||
591 | #else | ||
592 | #define SERBAD_FAD_MASK 0x000001FF | ||
593 | #endif | ||
594 | #define SERBAD_FAD_SHIFT 0 | ||
595 | |||
596 | /* | ||
597 | * The following defines are for the flags in the serial port backdoor | ||
598 | * configuration register. | ||
599 | */ | ||
600 | #define SERBCF_HBP 0x00000001 | ||
601 | |||
602 | /* | ||
603 | * The following defines are for the flags in the serial port backdoor write | ||
604 | * port register. | ||
605 | */ | ||
606 | #define SERBWP_FWD_MASK 0x000FFFFF | ||
607 | #define SERBWP_FWD_SHIFT 0 | ||
608 | |||
609 | /* | ||
610 | * The following defines are for the flags in the serial port backdoor read | ||
611 | * port register. | ||
612 | */ | ||
613 | #define SERBRP_FRD_MASK 0x000FFFFF | ||
614 | #define SERBRP_FRD_SHIFT 0 | ||
615 | |||
616 | /* | ||
617 | * The following defines are for the flags in the async FIFO address register. | ||
618 | */ | ||
619 | #ifndef NO_CS4612 | ||
620 | #define ASER_FADDR_A1_MASK 0x000001FF | ||
621 | #define ASER_FADDR_EN1 0x00008000 | ||
622 | #define ASER_FADDR_A2_MASK 0x01FF0000 | ||
623 | #define ASER_FADDR_EN2 0x80000000 | ||
624 | #define ASER_FADDR_A1_SHIFT 0 | ||
625 | #define ASER_FADDR_A2_SHIFT 16 | ||
626 | #endif | ||
627 | |||
628 | /* | ||
629 | * The following defines are for the flags in the AC97 control register. | ||
630 | */ | ||
631 | #define ACCTL_RSTN 0x00000001 | ||
632 | #define ACCTL_ESYN 0x00000002 | ||
633 | #define ACCTL_VFRM 0x00000004 | ||
634 | #define ACCTL_DCV 0x00000008 | ||
635 | #define ACCTL_CRW 0x00000010 | ||
636 | #define ACCTL_ASYN 0x00000020 | ||
637 | #ifndef NO_CS4612 | ||
638 | #define ACCTL_TC 0x00000040 | ||
639 | #endif | ||
640 | |||
641 | /* | ||
642 | * The following defines are for the flags in the AC97 status register. | ||
643 | */ | ||
644 | #define ACSTS_CRDY 0x00000001 | ||
645 | #define ACSTS_VSTS 0x00000002 | ||
646 | #ifndef NO_CS4612 | ||
647 | #define ACSTS_WKUP 0x00000004 | ||
648 | #endif | ||
649 | |||
650 | /* | ||
651 | * The following defines are for the flags in the AC97 output slot valid | ||
652 | * register. | ||
653 | */ | ||
654 | #define ACOSV_SLV3 0x00000001 | ||
655 | #define ACOSV_SLV4 0x00000002 | ||
656 | #define ACOSV_SLV5 0x00000004 | ||
657 | #define ACOSV_SLV6 0x00000008 | ||
658 | #define ACOSV_SLV7 0x00000010 | ||
659 | #define ACOSV_SLV8 0x00000020 | ||
660 | #define ACOSV_SLV9 0x00000040 | ||
661 | #define ACOSV_SLV10 0x00000080 | ||
662 | #define ACOSV_SLV11 0x00000100 | ||
663 | #define ACOSV_SLV12 0x00000200 | ||
664 | |||
665 | /* | ||
666 | * The following defines are for the flags in the AC97 command address | ||
667 | * register. | ||
668 | */ | ||
669 | #define ACCAD_CI_MASK 0x0000007F | ||
670 | #define ACCAD_CI_SHIFT 0 | ||
671 | |||
672 | /* | ||
673 | * The following defines are for the flags in the AC97 command data register. | ||
674 | */ | ||
675 | #define ACCDA_CD_MASK 0x0000FFFF | ||
676 | #define ACCDA_CD_SHIFT 0 | ||
677 | |||
678 | /* | ||
679 | * The following defines are for the flags in the AC97 input slot valid | ||
680 | * register. | ||
681 | */ | ||
682 | #define ACISV_ISV3 0x00000001 | ||
683 | #define ACISV_ISV4 0x00000002 | ||
684 | #define ACISV_ISV5 0x00000004 | ||
685 | #define ACISV_ISV6 0x00000008 | ||
686 | #define ACISV_ISV7 0x00000010 | ||
687 | #define ACISV_ISV8 0x00000020 | ||
688 | #define ACISV_ISV9 0x00000040 | ||
689 | #define ACISV_ISV10 0x00000080 | ||
690 | #define ACISV_ISV11 0x00000100 | ||
691 | #define ACISV_ISV12 0x00000200 | ||
692 | |||
693 | /* | ||
694 | * The following defines are for the flags in the AC97 status address | ||
695 | * register. | ||
696 | */ | ||
697 | #define ACSAD_SI_MASK 0x0000007F | ||
698 | #define ACSAD_SI_SHIFT 0 | ||
699 | |||
700 | /* | ||
701 | * The following defines are for the flags in the AC97 status data register. | ||
702 | */ | ||
703 | #define ACSDA_SD_MASK 0x0000FFFF | ||
704 | #define ACSDA_SD_SHIFT 0 | ||
705 | |||
706 | /* | ||
707 | * The following defines are for the flags in the joystick poll/trigger | ||
708 | * register. | ||
709 | */ | ||
710 | #define JSPT_CAX 0x00000001 | ||
711 | #define JSPT_CAY 0x00000002 | ||
712 | #define JSPT_CBX 0x00000004 | ||
713 | #define JSPT_CBY 0x00000008 | ||
714 | #define JSPT_BA1 0x00000010 | ||
715 | #define JSPT_BA2 0x00000020 | ||
716 | #define JSPT_BB1 0x00000040 | ||
717 | #define JSPT_BB2 0x00000080 | ||
718 | |||
719 | /* | ||
720 | * The following defines are for the flags in the joystick control register. | ||
721 | */ | ||
722 | #define JSCTL_SP_MASK 0x00000003 | ||
723 | #define JSCTL_SP_SLOW 0x00000000 | ||
724 | #define JSCTL_SP_MEDIUM_SLOW 0x00000001 | ||
725 | #define JSCTL_SP_MEDIUM_FAST 0x00000002 | ||
726 | #define JSCTL_SP_FAST 0x00000003 | ||
727 | #define JSCTL_ARE 0x00000004 | ||
728 | |||
729 | /* | ||
730 | * The following defines are for the flags in the joystick coordinate pair 1 | ||
731 | * readback register. | ||
732 | */ | ||
733 | #define JSC1_Y1V_MASK 0x0000FFFF | ||
734 | #define JSC1_X1V_MASK 0xFFFF0000 | ||
735 | #define JSC1_Y1V_SHIFT 0 | ||
736 | #define JSC1_X1V_SHIFT 16 | ||
737 | |||
738 | /* | ||
739 | * The following defines are for the flags in the joystick coordinate pair 2 | ||
740 | * readback register. | ||
741 | */ | ||
742 | #define JSC2_Y2V_MASK 0x0000FFFF | ||
743 | #define JSC2_X2V_MASK 0xFFFF0000 | ||
744 | #define JSC2_Y2V_SHIFT 0 | ||
745 | #define JSC2_X2V_SHIFT 16 | ||
746 | |||
747 | /* | ||
748 | * The following defines are for the flags in the MIDI control register. | ||
749 | */ | ||
750 | #define MIDCR_TXE 0x00000001 /* Enable transmitting. */ | ||
751 | #define MIDCR_RXE 0x00000002 /* Enable receiving. */ | ||
752 | #define MIDCR_RIE 0x00000004 /* Interrupt upon tx ready. */ | ||
753 | #define MIDCR_TIE 0x00000008 /* Interrupt upon rx ready. */ | ||
754 | #define MIDCR_MLB 0x00000010 /* Enable midi loopback. */ | ||
755 | #define MIDCR_MRST 0x00000020 /* Reset interface. */ | ||
756 | |||
757 | /* | ||
758 | * The following defines are for the flags in the MIDI status register. | ||
759 | */ | ||
760 | #define MIDSR_TBF 0x00000001 /* Tx FIFO is full. */ | ||
761 | #define MIDSR_RBE 0x00000002 /* Rx FIFO is empty. */ | ||
762 | |||
763 | /* | ||
764 | * The following defines are for the flags in the MIDI write port register. | ||
765 | */ | ||
766 | #define MIDWP_MWD_MASK 0x000000FF | ||
767 | #define MIDWP_MWD_SHIFT 0 | ||
768 | |||
769 | /* | ||
770 | * The following defines are for the flags in the MIDI read port register. | ||
771 | */ | ||
772 | #define MIDRP_MRD_MASK 0x000000FF | ||
773 | #define MIDRP_MRD_SHIFT 0 | ||
774 | |||
775 | /* | ||
776 | * The following defines are for the flags in the joystick GPIO register. | ||
777 | */ | ||
778 | #define JSIO_DAX 0x00000001 | ||
779 | #define JSIO_DAY 0x00000002 | ||
780 | #define JSIO_DBX 0x00000004 | ||
781 | #define JSIO_DBY 0x00000008 | ||
782 | #define JSIO_AXOE 0x00000010 | ||
783 | #define JSIO_AYOE 0x00000020 | ||
784 | #define JSIO_BXOE 0x00000040 | ||
785 | #define JSIO_BYOE 0x00000080 | ||
786 | |||
787 | /* | ||
788 | * The following defines are for the flags in the master async/sync serial | ||
789 | * port enable register. | ||
790 | */ | ||
791 | #ifndef NO_CS4612 | ||
792 | #define ASER_MASTER_ME 0x00000001 | ||
793 | #endif | ||
794 | |||
795 | /* | ||
796 | * The following defines are for the flags in the configuration interface | ||
797 | * register. | ||
798 | */ | ||
799 | #define CFGI_CLK 0x00000001 | ||
800 | #define CFGI_DOUT 0x00000002 | ||
801 | #define CFGI_DIN_EEN 0x00000004 | ||
802 | #define CFGI_EELD 0x00000008 | ||
803 | |||
804 | /* | ||
805 | * The following defines are for the flags in the subsystem ID and vendor ID | ||
806 | * register. | ||
807 | */ | ||
808 | #define SSVID_VID_MASK 0x0000FFFF | ||
809 | #define SSVID_SID_MASK 0xFFFF0000 | ||
810 | #define SSVID_VID_SHIFT 0 | ||
811 | #define SSVID_SID_SHIFT 16 | ||
812 | |||
813 | /* | ||
814 | * The following defines are for the flags in the GPIO pin interface register. | ||
815 | */ | ||
816 | #define GPIOR_VOLDN 0x00000001 | ||
817 | #define GPIOR_VOLUP 0x00000002 | ||
818 | #define GPIOR_SI2D 0x00000004 | ||
819 | #define GPIOR_SI2OE 0x00000008 | ||
820 | |||
821 | /* | ||
822 | * The following defines are for the flags in the extended GPIO pin direction | ||
823 | * register. | ||
824 | */ | ||
825 | #ifndef NO_CS4612 | ||
826 | #define EGPIODR_GPOE0 0x00000001 | ||
827 | #define EGPIODR_GPOE1 0x00000002 | ||
828 | #define EGPIODR_GPOE2 0x00000004 | ||
829 | #define EGPIODR_GPOE3 0x00000008 | ||
830 | #define EGPIODR_GPOE4 0x00000010 | ||
831 | #define EGPIODR_GPOE5 0x00000020 | ||
832 | #define EGPIODR_GPOE6 0x00000040 | ||
833 | #define EGPIODR_GPOE7 0x00000080 | ||
834 | #define EGPIODR_GPOE8 0x00000100 | ||
835 | #endif | ||
836 | |||
837 | /* | ||
838 | * The following defines are for the flags in the extended GPIO pin polarity/ | ||
839 | * type register. | ||
840 | */ | ||
841 | #ifndef NO_CS4612 | ||
842 | #define EGPIOPTR_GPPT0 0x00000001 | ||
843 | #define EGPIOPTR_GPPT1 0x00000002 | ||
844 | #define EGPIOPTR_GPPT2 0x00000004 | ||
845 | #define EGPIOPTR_GPPT3 0x00000008 | ||
846 | #define EGPIOPTR_GPPT4 0x00000010 | ||
847 | #define EGPIOPTR_GPPT5 0x00000020 | ||
848 | #define EGPIOPTR_GPPT6 0x00000040 | ||
849 | #define EGPIOPTR_GPPT7 0x00000080 | ||
850 | #define EGPIOPTR_GPPT8 0x00000100 | ||
851 | #endif | ||
852 | |||
853 | /* | ||
854 | * The following defines are for the flags in the extended GPIO pin sticky | ||
855 | * register. | ||
856 | */ | ||
857 | #ifndef NO_CS4612 | ||
858 | #define EGPIOTR_GPS0 0x00000001 | ||
859 | #define EGPIOTR_GPS1 0x00000002 | ||
860 | #define EGPIOTR_GPS2 0x00000004 | ||
861 | #define EGPIOTR_GPS3 0x00000008 | ||
862 | #define EGPIOTR_GPS4 0x00000010 | ||
863 | #define EGPIOTR_GPS5 0x00000020 | ||
864 | #define EGPIOTR_GPS6 0x00000040 | ||
865 | #define EGPIOTR_GPS7 0x00000080 | ||
866 | #define EGPIOTR_GPS8 0x00000100 | ||
867 | #endif | ||
868 | |||
869 | /* | ||
870 | * The following defines are for the flags in the extended GPIO ping wakeup | ||
871 | * register. | ||
872 | */ | ||
873 | #ifndef NO_CS4612 | ||
874 | #define EGPIOWR_GPW0 0x00000001 | ||
875 | #define EGPIOWR_GPW1 0x00000002 | ||
876 | #define EGPIOWR_GPW2 0x00000004 | ||
877 | #define EGPIOWR_GPW3 0x00000008 | ||
878 | #define EGPIOWR_GPW4 0x00000010 | ||
879 | #define EGPIOWR_GPW5 0x00000020 | ||
880 | #define EGPIOWR_GPW6 0x00000040 | ||
881 | #define EGPIOWR_GPW7 0x00000080 | ||
882 | #define EGPIOWR_GPW8 0x00000100 | ||
883 | #endif | ||
884 | |||
885 | /* | ||
886 | * The following defines are for the flags in the extended GPIO pin status | ||
887 | * register. | ||
888 | */ | ||
889 | #ifndef NO_CS4612 | ||
890 | #define EGPIOSR_GPS0 0x00000001 | ||
891 | #define EGPIOSR_GPS1 0x00000002 | ||
892 | #define EGPIOSR_GPS2 0x00000004 | ||
893 | #define EGPIOSR_GPS3 0x00000008 | ||
894 | #define EGPIOSR_GPS4 0x00000010 | ||
895 | #define EGPIOSR_GPS5 0x00000020 | ||
896 | #define EGPIOSR_GPS6 0x00000040 | ||
897 | #define EGPIOSR_GPS7 0x00000080 | ||
898 | #define EGPIOSR_GPS8 0x00000100 | ||
899 | #endif | ||
900 | |||
901 | /* | ||
902 | * The following defines are for the flags in the serial port 6 configuration | ||
903 | * register. | ||
904 | */ | ||
905 | #ifndef NO_CS4612 | ||
906 | #define SERC6_ASDO2EN 0x00000001 | ||
907 | #endif | ||
908 | |||
909 | /* | ||
910 | * The following defines are for the flags in the serial port 7 configuration | ||
911 | * register. | ||
912 | */ | ||
913 | #ifndef NO_CS4612 | ||
914 | #define SERC7_ASDI2EN 0x00000001 | ||
915 | #define SERC7_POSILB 0x00000002 | ||
916 | #define SERC7_SIPOLB 0x00000004 | ||
917 | #define SERC7_SOSILB 0x00000008 | ||
918 | #define SERC7_SISOLB 0x00000010 | ||
919 | #endif | ||
920 | |||
921 | /* | ||
922 | * The following defines are for the flags in the serial port AC link | ||
923 | * configuration register. | ||
924 | */ | ||
925 | #ifndef NO_CS4612 | ||
926 | #define SERACC_CHIP_TYPE_MASK 0x00000001 | ||
927 | #define SERACC_CHIP_TYPE_1_03 0x00000000 | ||
928 | #define SERACC_CHIP_TYPE_2_0 0x00000001 | ||
929 | #define SERACC_TWO_CODECS 0x00000002 | ||
930 | #define SERACC_MDM 0x00000004 | ||
931 | #define SERACC_HSP 0x00000008 | ||
932 | #define SERACC_ODT 0x00000010 /* only CS4630 */ | ||
933 | #endif | ||
934 | |||
935 | /* | ||
936 | * The following defines are for the flags in the AC97 control register 2. | ||
937 | */ | ||
938 | #ifndef NO_CS4612 | ||
939 | #define ACCTL2_RSTN 0x00000001 | ||
940 | #define ACCTL2_ESYN 0x00000002 | ||
941 | #define ACCTL2_VFRM 0x00000004 | ||
942 | #define ACCTL2_DCV 0x00000008 | ||
943 | #define ACCTL2_CRW 0x00000010 | ||
944 | #define ACCTL2_ASYN 0x00000020 | ||
945 | #endif | ||
946 | |||
947 | /* | ||
948 | * The following defines are for the flags in the AC97 status register 2. | ||
949 | */ | ||
950 | #ifndef NO_CS4612 | ||
951 | #define ACSTS2_CRDY 0x00000001 | ||
952 | #define ACSTS2_VSTS 0x00000002 | ||
953 | #endif | ||
954 | |||
955 | /* | ||
956 | * The following defines are for the flags in the AC97 output slot valid | ||
957 | * register 2. | ||
958 | */ | ||
959 | #ifndef NO_CS4612 | ||
960 | #define ACOSV2_SLV3 0x00000001 | ||
961 | #define ACOSV2_SLV4 0x00000002 | ||
962 | #define ACOSV2_SLV5 0x00000004 | ||
963 | #define ACOSV2_SLV6 0x00000008 | ||
964 | #define ACOSV2_SLV7 0x00000010 | ||
965 | #define ACOSV2_SLV8 0x00000020 | ||
966 | #define ACOSV2_SLV9 0x00000040 | ||
967 | #define ACOSV2_SLV10 0x00000080 | ||
968 | #define ACOSV2_SLV11 0x00000100 | ||
969 | #define ACOSV2_SLV12 0x00000200 | ||
970 | #endif | ||
971 | |||
972 | /* | ||
973 | * The following defines are for the flags in the AC97 command address | ||
974 | * register 2. | ||
975 | */ | ||
976 | #ifndef NO_CS4612 | ||
977 | #define ACCAD2_CI_MASK 0x0000007F | ||
978 | #define ACCAD2_CI_SHIFT 0 | ||
979 | #endif | ||
980 | |||
981 | /* | ||
982 | * The following defines are for the flags in the AC97 command data register | ||
983 | * 2. | ||
984 | */ | ||
985 | #ifndef NO_CS4612 | ||
986 | #define ACCDA2_CD_MASK 0x0000FFFF | ||
987 | #define ACCDA2_CD_SHIFT 0 | ||
988 | #endif | ||
989 | |||
990 | /* | ||
991 | * The following defines are for the flags in the AC97 input slot valid | ||
992 | * register 2. | ||
993 | */ | ||
994 | #ifndef NO_CS4612 | ||
995 | #define ACISV2_ISV3 0x00000001 | ||
996 | #define ACISV2_ISV4 0x00000002 | ||
997 | #define ACISV2_ISV5 0x00000004 | ||
998 | #define ACISV2_ISV6 0x00000008 | ||
999 | #define ACISV2_ISV7 0x00000010 | ||
1000 | #define ACISV2_ISV8 0x00000020 | ||
1001 | #define ACISV2_ISV9 0x00000040 | ||
1002 | #define ACISV2_ISV10 0x00000080 | ||
1003 | #define ACISV2_ISV11 0x00000100 | ||
1004 | #define ACISV2_ISV12 0x00000200 | ||
1005 | #endif | ||
1006 | |||
1007 | /* | ||
1008 | * The following defines are for the flags in the AC97 status address | ||
1009 | * register 2. | ||
1010 | */ | ||
1011 | #ifndef NO_CS4612 | ||
1012 | #define ACSAD2_SI_MASK 0x0000007F | ||
1013 | #define ACSAD2_SI_SHIFT 0 | ||
1014 | #endif | ||
1015 | |||
1016 | /* | ||
1017 | * The following defines are for the flags in the AC97 status data register 2. | ||
1018 | */ | ||
1019 | #ifndef NO_CS4612 | ||
1020 | #define ACSDA2_SD_MASK 0x0000FFFF | ||
1021 | #define ACSDA2_SD_SHIFT 0 | ||
1022 | #endif | ||
1023 | |||
1024 | /* | ||
1025 | * The following defines are for the flags in the I/O trap address and control | ||
1026 | * registers (all 12). | ||
1027 | */ | ||
1028 | #ifndef NO_CS4612 | ||
1029 | #define IOTAC_SA_MASK 0x0000FFFF | ||
1030 | #define IOTAC_MSK_MASK 0x000F0000 | ||
1031 | #define IOTAC_IODC_MASK 0x06000000 | ||
1032 | #define IOTAC_IODC_16_BIT 0x00000000 | ||
1033 | #define IOTAC_IODC_10_BIT 0x02000000 | ||
1034 | #define IOTAC_IODC_12_BIT 0x04000000 | ||
1035 | #define IOTAC_WSPI 0x08000000 | ||
1036 | #define IOTAC_RSPI 0x10000000 | ||
1037 | #define IOTAC_WSE 0x20000000 | ||
1038 | #define IOTAC_WE 0x40000000 | ||
1039 | #define IOTAC_RE 0x80000000 | ||
1040 | #define IOTAC_SA_SHIFT 0 | ||
1041 | #define IOTAC_MSK_SHIFT 16 | ||
1042 | #endif | ||
1043 | |||
1044 | /* | ||
1045 | * The following defines are for the flags in the I/O trap fast read registers | ||
1046 | * (all 8). | ||
1047 | */ | ||
1048 | #ifndef NO_CS4612 | ||
1049 | #define IOTFR_D_MASK 0x0000FFFF | ||
1050 | #define IOTFR_A_MASK 0x000F0000 | ||
1051 | #define IOTFR_R_MASK 0x0F000000 | ||
1052 | #define IOTFR_ALL 0x40000000 | ||
1053 | #define IOTFR_VL 0x80000000 | ||
1054 | #define IOTFR_D_SHIFT 0 | ||
1055 | #define IOTFR_A_SHIFT 16 | ||
1056 | #define IOTFR_R_SHIFT 24 | ||
1057 | #endif | ||
1058 | |||
1059 | /* | ||
1060 | * The following defines are for the flags in the I/O trap FIFO register. | ||
1061 | */ | ||
1062 | #ifndef NO_CS4612 | ||
1063 | #define IOTFIFO_BA_MASK 0x00003FFF | ||
1064 | #define IOTFIFO_S_MASK 0x00FF0000 | ||
1065 | #define IOTFIFO_OF 0x40000000 | ||
1066 | #define IOTFIFO_SPIOF 0x80000000 | ||
1067 | #define IOTFIFO_BA_SHIFT 0 | ||
1068 | #define IOTFIFO_S_SHIFT 16 | ||
1069 | #endif | ||
1070 | |||
1071 | /* | ||
1072 | * The following defines are for the flags in the I/O trap retry read data | ||
1073 | * register. | ||
1074 | */ | ||
1075 | #ifndef NO_CS4612 | ||
1076 | #define IOTRRD_D_MASK 0x0000FFFF | ||
1077 | #define IOTRRD_RDV 0x80000000 | ||
1078 | #define IOTRRD_D_SHIFT 0 | ||
1079 | #endif | ||
1080 | |||
1081 | /* | ||
1082 | * The following defines are for the flags in the I/O trap FIFO pointer | ||
1083 | * register. | ||
1084 | */ | ||
1085 | #ifndef NO_CS4612 | ||
1086 | #define IOTFP_CA_MASK 0x00003FFF | ||
1087 | #define IOTFP_PA_MASK 0x3FFF0000 | ||
1088 | #define IOTFP_CA_SHIFT 0 | ||
1089 | #define IOTFP_PA_SHIFT 16 | ||
1090 | #endif | ||
1091 | |||
1092 | /* | ||
1093 | * The following defines are for the flags in the I/O trap control register. | ||
1094 | */ | ||
1095 | #ifndef NO_CS4612 | ||
1096 | #define IOTCR_ITD 0x00000001 | ||
1097 | #define IOTCR_HRV 0x00000002 | ||
1098 | #define IOTCR_SRV 0x00000004 | ||
1099 | #define IOTCR_DTI 0x00000008 | ||
1100 | #define IOTCR_DFI 0x00000010 | ||
1101 | #define IOTCR_DDP 0x00000020 | ||
1102 | #define IOTCR_JTE 0x00000040 | ||
1103 | #define IOTCR_PPE 0x00000080 | ||
1104 | #endif | ||
1105 | |||
1106 | /* | ||
1107 | * The following defines are for the flags in the direct PCI data register. | ||
1108 | */ | ||
1109 | #ifndef NO_CS4612 | ||
1110 | #define DPCID_D_MASK 0xFFFFFFFF | ||
1111 | #define DPCID_D_SHIFT 0 | ||
1112 | #endif | ||
1113 | |||
1114 | /* | ||
1115 | * The following defines are for the flags in the direct PCI address register. | ||
1116 | */ | ||
1117 | #ifndef NO_CS4612 | ||
1118 | #define DPCIA_A_MASK 0xFFFFFFFF | ||
1119 | #define DPCIA_A_SHIFT 0 | ||
1120 | #endif | ||
1121 | |||
1122 | /* | ||
1123 | * The following defines are for the flags in the direct PCI command register. | ||
1124 | */ | ||
1125 | #ifndef NO_CS4612 | ||
1126 | #define DPCIC_C_MASK 0x0000000F | ||
1127 | #define DPCIC_C_IOREAD 0x00000002 | ||
1128 | #define DPCIC_C_IOWRITE 0x00000003 | ||
1129 | #define DPCIC_BE_MASK 0x000000F0 | ||
1130 | #endif | ||
1131 | |||
1132 | /* | ||
1133 | * The following defines are for the flags in the PC/PCI request register. | ||
1134 | */ | ||
1135 | #ifndef NO_CS4612 | ||
1136 | #define PCPCIR_RDC_MASK 0x00000007 | ||
1137 | #define PCPCIR_C_MASK 0x00007000 | ||
1138 | #define PCPCIR_REQ 0x00008000 | ||
1139 | #define PCPCIR_RDC_SHIFT 0 | ||
1140 | #define PCPCIR_C_SHIFT 12 | ||
1141 | #endif | ||
1142 | |||
1143 | /* | ||
1144 | * The following defines are for the flags in the PC/PCI grant register. | ||
1145 | */ | ||
1146 | #ifndef NO_CS4612 | ||
1147 | #define PCPCIG_GDC_MASK 0x00000007 | ||
1148 | #define PCPCIG_VL 0x00008000 | ||
1149 | #define PCPCIG_GDC_SHIFT 0 | ||
1150 | #endif | ||
1151 | |||
1152 | /* | ||
1153 | * The following defines are for the flags in the PC/PCI master enable | ||
1154 | * register. | ||
1155 | */ | ||
1156 | #ifndef NO_CS4612 | ||
1157 | #define PCPCIEN_EN 0x00000001 | ||
1158 | #endif | ||
1159 | |||
1160 | /* | ||
1161 | * The following defines are for the flags in the extended PCI power | ||
1162 | * management control register. | ||
1163 | */ | ||
1164 | #ifndef NO_CS4612 | ||
1165 | #define EPCIPMC_GWU 0x00000001 | ||
1166 | #define EPCIPMC_FSPC 0x00000002 | ||
1167 | #endif | ||
1168 | |||
1169 | /* | ||
1170 | * The following defines are for the flags in the SP control register. | ||
1171 | */ | ||
1172 | #define SPCR_RUN 0x00000001 | ||
1173 | #define SPCR_STPFR 0x00000002 | ||
1174 | #define SPCR_RUNFR 0x00000004 | ||
1175 | #define SPCR_TICK 0x00000008 | ||
1176 | #define SPCR_DRQEN 0x00000020 | ||
1177 | #define SPCR_RSTSP 0x00000040 | ||
1178 | #define SPCR_OREN 0x00000080 | ||
1179 | #ifndef NO_CS4612 | ||
1180 | #define SPCR_PCIINT 0x00000100 | ||
1181 | #define SPCR_OINTD 0x00000200 | ||
1182 | #define SPCR_CRE 0x00008000 | ||
1183 | #endif | ||
1184 | |||
1185 | /* | ||
1186 | * The following defines are for the flags in the debug index register. | ||
1187 | */ | ||
1188 | #define DREG_REGID_MASK 0x0000007F | ||
1189 | #define DREG_DEBUG 0x00000080 | ||
1190 | #define DREG_RGBK_MASK 0x00000700 | ||
1191 | #define DREG_TRAP 0x00000800 | ||
1192 | #if !defined(NO_CS4612) | ||
1193 | #if !defined(NO_CS4615) | ||
1194 | #define DREG_TRAPX 0x00001000 | ||
1195 | #endif | ||
1196 | #endif | ||
1197 | #define DREG_REGID_SHIFT 0 | ||
1198 | #define DREG_RGBK_SHIFT 8 | ||
1199 | #define DREG_RGBK_REGID_MASK 0x0000077F | ||
1200 | #define DREG_REGID_R0 0x00000010 | ||
1201 | #define DREG_REGID_R1 0x00000011 | ||
1202 | #define DREG_REGID_R2 0x00000012 | ||
1203 | #define DREG_REGID_R3 0x00000013 | ||
1204 | #define DREG_REGID_R4 0x00000014 | ||
1205 | #define DREG_REGID_R5 0x00000015 | ||
1206 | #define DREG_REGID_R6 0x00000016 | ||
1207 | #define DREG_REGID_R7 0x00000017 | ||
1208 | #define DREG_REGID_R8 0x00000018 | ||
1209 | #define DREG_REGID_R9 0x00000019 | ||
1210 | #define DREG_REGID_RA 0x0000001A | ||
1211 | #define DREG_REGID_RB 0x0000001B | ||
1212 | #define DREG_REGID_RC 0x0000001C | ||
1213 | #define DREG_REGID_RD 0x0000001D | ||
1214 | #define DREG_REGID_RE 0x0000001E | ||
1215 | #define DREG_REGID_RF 0x0000001F | ||
1216 | #define DREG_REGID_RA_BUS_LOW 0x00000020 | ||
1217 | #define DREG_REGID_RA_BUS_HIGH 0x00000038 | ||
1218 | #define DREG_REGID_YBUS_LOW 0x00000050 | ||
1219 | #define DREG_REGID_YBUS_HIGH 0x00000058 | ||
1220 | #define DREG_REGID_TRAP_0 0x00000100 | ||
1221 | #define DREG_REGID_TRAP_1 0x00000101 | ||
1222 | #define DREG_REGID_TRAP_2 0x00000102 | ||
1223 | #define DREG_REGID_TRAP_3 0x00000103 | ||
1224 | #define DREG_REGID_TRAP_4 0x00000104 | ||
1225 | #define DREG_REGID_TRAP_5 0x00000105 | ||
1226 | #define DREG_REGID_TRAP_6 0x00000106 | ||
1227 | #define DREG_REGID_TRAP_7 0x00000107 | ||
1228 | #define DREG_REGID_INDIRECT_ADDRESS 0x0000010E | ||
1229 | #define DREG_REGID_TOP_OF_STACK 0x0000010F | ||
1230 | #if !defined(NO_CS4612) | ||
1231 | #if !defined(NO_CS4615) | ||
1232 | #define DREG_REGID_TRAP_8 0x00000110 | ||
1233 | #define DREG_REGID_TRAP_9 0x00000111 | ||
1234 | #define DREG_REGID_TRAP_10 0x00000112 | ||
1235 | #define DREG_REGID_TRAP_11 0x00000113 | ||
1236 | #define DREG_REGID_TRAP_12 0x00000114 | ||
1237 | #define DREG_REGID_TRAP_13 0x00000115 | ||
1238 | #define DREG_REGID_TRAP_14 0x00000116 | ||
1239 | #define DREG_REGID_TRAP_15 0x00000117 | ||
1240 | #define DREG_REGID_TRAP_16 0x00000118 | ||
1241 | #define DREG_REGID_TRAP_17 0x00000119 | ||
1242 | #define DREG_REGID_TRAP_18 0x0000011A | ||
1243 | #define DREG_REGID_TRAP_19 0x0000011B | ||
1244 | #define DREG_REGID_TRAP_20 0x0000011C | ||
1245 | #define DREG_REGID_TRAP_21 0x0000011D | ||
1246 | #define DREG_REGID_TRAP_22 0x0000011E | ||
1247 | #define DREG_REGID_TRAP_23 0x0000011F | ||
1248 | #endif | ||
1249 | #endif | ||
1250 | #define DREG_REGID_RSA0_LOW 0x00000200 | ||
1251 | #define DREG_REGID_RSA0_HIGH 0x00000201 | ||
1252 | #define DREG_REGID_RSA1_LOW 0x00000202 | ||
1253 | #define DREG_REGID_RSA1_HIGH 0x00000203 | ||
1254 | #define DREG_REGID_RSA2 0x00000204 | ||
1255 | #define DREG_REGID_RSA3 0x00000205 | ||
1256 | #define DREG_REGID_RSI0_LOW 0x00000206 | ||
1257 | #define DREG_REGID_RSI0_HIGH 0x00000207 | ||
1258 | #define DREG_REGID_RSI1 0x00000208 | ||
1259 | #define DREG_REGID_RSI2 0x00000209 | ||
1260 | #define DREG_REGID_SAGUSTATUS 0x0000020A | ||
1261 | #define DREG_REGID_RSCONFIG01_LOW 0x0000020B | ||
1262 | #define DREG_REGID_RSCONFIG01_HIGH 0x0000020C | ||
1263 | #define DREG_REGID_RSCONFIG23_LOW 0x0000020D | ||
1264 | #define DREG_REGID_RSCONFIG23_HIGH 0x0000020E | ||
1265 | #define DREG_REGID_RSDMA01E 0x0000020F | ||
1266 | #define DREG_REGID_RSDMA23E 0x00000210 | ||
1267 | #define DREG_REGID_RSD0_LOW 0x00000211 | ||
1268 | #define DREG_REGID_RSD0_HIGH 0x00000212 | ||
1269 | #define DREG_REGID_RSD1_LOW 0x00000213 | ||
1270 | #define DREG_REGID_RSD1_HIGH 0x00000214 | ||
1271 | #define DREG_REGID_RSD2_LOW 0x00000215 | ||
1272 | #define DREG_REGID_RSD2_HIGH 0x00000216 | ||
1273 | #define DREG_REGID_RSD3_LOW 0x00000217 | ||
1274 | #define DREG_REGID_RSD3_HIGH 0x00000218 | ||
1275 | #define DREG_REGID_SRAR_HIGH 0x0000021A | ||
1276 | #define DREG_REGID_SRAR_LOW 0x0000021B | ||
1277 | #define DREG_REGID_DMA_STATE 0x0000021C | ||
1278 | #define DREG_REGID_CURRENT_DMA_STREAM 0x0000021D | ||
1279 | #define DREG_REGID_NEXT_DMA_STREAM 0x0000021E | ||
1280 | #define DREG_REGID_CPU_STATUS 0x00000300 | ||
1281 | #define DREG_REGID_MAC_MODE 0x00000301 | ||
1282 | #define DREG_REGID_STACK_AND_REPEAT 0x00000302 | ||
1283 | #define DREG_REGID_INDEX0 0x00000304 | ||
1284 | #define DREG_REGID_INDEX1 0x00000305 | ||
1285 | #define DREG_REGID_DMA_STATE_0_3 0x00000400 | ||
1286 | #define DREG_REGID_DMA_STATE_4_7 0x00000404 | ||
1287 | #define DREG_REGID_DMA_STATE_8_11 0x00000408 | ||
1288 | #define DREG_REGID_DMA_STATE_12_15 0x0000040C | ||
1289 | #define DREG_REGID_DMA_STATE_16_19 0x00000410 | ||
1290 | #define DREG_REGID_DMA_STATE_20_23 0x00000414 | ||
1291 | #define DREG_REGID_DMA_STATE_24_27 0x00000418 | ||
1292 | #define DREG_REGID_DMA_STATE_28_31 0x0000041C | ||
1293 | #define DREG_REGID_DMA_STATE_32_35 0x00000420 | ||
1294 | #define DREG_REGID_DMA_STATE_36_39 0x00000424 | ||
1295 | #define DREG_REGID_DMA_STATE_40_43 0x00000428 | ||
1296 | #define DREG_REGID_DMA_STATE_44_47 0x0000042C | ||
1297 | #define DREG_REGID_DMA_STATE_48_51 0x00000430 | ||
1298 | #define DREG_REGID_DMA_STATE_52_55 0x00000434 | ||
1299 | #define DREG_REGID_DMA_STATE_56_59 0x00000438 | ||
1300 | #define DREG_REGID_DMA_STATE_60_63 0x0000043C | ||
1301 | #define DREG_REGID_DMA_STATE_64_67 0x00000440 | ||
1302 | #define DREG_REGID_DMA_STATE_68_71 0x00000444 | ||
1303 | #define DREG_REGID_DMA_STATE_72_75 0x00000448 | ||
1304 | #define DREG_REGID_DMA_STATE_76_79 0x0000044C | ||
1305 | #define DREG_REGID_DMA_STATE_80_83 0x00000450 | ||
1306 | #define DREG_REGID_DMA_STATE_84_87 0x00000454 | ||
1307 | #define DREG_REGID_DMA_STATE_88_91 0x00000458 | ||
1308 | #define DREG_REGID_DMA_STATE_92_95 0x0000045C | ||
1309 | #define DREG_REGID_TRAP_SELECT 0x00000500 | ||
1310 | #define DREG_REGID_TRAP_WRITE_0 0x00000500 | ||
1311 | #define DREG_REGID_TRAP_WRITE_1 0x00000501 | ||
1312 | #define DREG_REGID_TRAP_WRITE_2 0x00000502 | ||
1313 | #define DREG_REGID_TRAP_WRITE_3 0x00000503 | ||
1314 | #define DREG_REGID_TRAP_WRITE_4 0x00000504 | ||
1315 | #define DREG_REGID_TRAP_WRITE_5 0x00000505 | ||
1316 | #define DREG_REGID_TRAP_WRITE_6 0x00000506 | ||
1317 | #define DREG_REGID_TRAP_WRITE_7 0x00000507 | ||
1318 | #if !defined(NO_CS4612) | ||
1319 | #if !defined(NO_CS4615) | ||
1320 | #define DREG_REGID_TRAP_WRITE_8 0x00000510 | ||
1321 | #define DREG_REGID_TRAP_WRITE_9 0x00000511 | ||
1322 | #define DREG_REGID_TRAP_WRITE_10 0x00000512 | ||
1323 | #define DREG_REGID_TRAP_WRITE_11 0x00000513 | ||
1324 | #define DREG_REGID_TRAP_WRITE_12 0x00000514 | ||
1325 | #define DREG_REGID_TRAP_WRITE_13 0x00000515 | ||
1326 | #define DREG_REGID_TRAP_WRITE_14 0x00000516 | ||
1327 | #define DREG_REGID_TRAP_WRITE_15 0x00000517 | ||
1328 | #define DREG_REGID_TRAP_WRITE_16 0x00000518 | ||
1329 | #define DREG_REGID_TRAP_WRITE_17 0x00000519 | ||
1330 | #define DREG_REGID_TRAP_WRITE_18 0x0000051A | ||
1331 | #define DREG_REGID_TRAP_WRITE_19 0x0000051B | ||
1332 | #define DREG_REGID_TRAP_WRITE_20 0x0000051C | ||
1333 | #define DREG_REGID_TRAP_WRITE_21 0x0000051D | ||
1334 | #define DREG_REGID_TRAP_WRITE_22 0x0000051E | ||
1335 | #define DREG_REGID_TRAP_WRITE_23 0x0000051F | ||
1336 | #endif | ||
1337 | #endif | ||
1338 | #define DREG_REGID_MAC0_ACC0_LOW 0x00000600 | ||
1339 | #define DREG_REGID_MAC0_ACC1_LOW 0x00000601 | ||
1340 | #define DREG_REGID_MAC0_ACC2_LOW 0x00000602 | ||
1341 | #define DREG_REGID_MAC0_ACC3_LOW 0x00000603 | ||
1342 | #define DREG_REGID_MAC1_ACC0_LOW 0x00000604 | ||
1343 | #define DREG_REGID_MAC1_ACC1_LOW 0x00000605 | ||
1344 | #define DREG_REGID_MAC1_ACC2_LOW 0x00000606 | ||
1345 | #define DREG_REGID_MAC1_ACC3_LOW 0x00000607 | ||
1346 | #define DREG_REGID_MAC0_ACC0_MID 0x00000608 | ||
1347 | #define DREG_REGID_MAC0_ACC1_MID 0x00000609 | ||
1348 | #define DREG_REGID_MAC0_ACC2_MID 0x0000060A | ||
1349 | #define DREG_REGID_MAC0_ACC3_MID 0x0000060B | ||
1350 | #define DREG_REGID_MAC1_ACC0_MID 0x0000060C | ||
1351 | #define DREG_REGID_MAC1_ACC1_MID 0x0000060D | ||
1352 | #define DREG_REGID_MAC1_ACC2_MID 0x0000060E | ||
1353 | #define DREG_REGID_MAC1_ACC3_MID 0x0000060F | ||
1354 | #define DREG_REGID_MAC0_ACC0_HIGH 0x00000610 | ||
1355 | #define DREG_REGID_MAC0_ACC1_HIGH 0x00000611 | ||
1356 | #define DREG_REGID_MAC0_ACC2_HIGH 0x00000612 | ||
1357 | #define DREG_REGID_MAC0_ACC3_HIGH 0x00000613 | ||
1358 | #define DREG_REGID_MAC1_ACC0_HIGH 0x00000614 | ||
1359 | #define DREG_REGID_MAC1_ACC1_HIGH 0x00000615 | ||
1360 | #define DREG_REGID_MAC1_ACC2_HIGH 0x00000616 | ||
1361 | #define DREG_REGID_MAC1_ACC3_HIGH 0x00000617 | ||
1362 | #define DREG_REGID_RSHOUT_LOW 0x00000620 | ||
1363 | #define DREG_REGID_RSHOUT_MID 0x00000628 | ||
1364 | #define DREG_REGID_RSHOUT_HIGH 0x00000630 | ||
1365 | |||
1366 | /* | ||
1367 | * The following defines are for the flags in the DMA stream requestor write | ||
1368 | */ | ||
1369 | #define DSRWP_DSR_MASK 0x0000000F | ||
1370 | #define DSRWP_DSR_BG_RQ 0x00000001 | ||
1371 | #define DSRWP_DSR_PRIORITY_MASK 0x00000006 | ||
1372 | #define DSRWP_DSR_PRIORITY_0 0x00000000 | ||
1373 | #define DSRWP_DSR_PRIORITY_1 0x00000002 | ||
1374 | #define DSRWP_DSR_PRIORITY_2 0x00000004 | ||
1375 | #define DSRWP_DSR_PRIORITY_3 0x00000006 | ||
1376 | #define DSRWP_DSR_RQ_PENDING 0x00000008 | ||
1377 | |||
1378 | /* | ||
1379 | * The following defines are for the flags in the trap write port register. | ||
1380 | */ | ||
1381 | #define TWPR_TW_MASK 0x0000FFFF | ||
1382 | #define TWPR_TW_SHIFT 0 | ||
1383 | |||
1384 | /* | ||
1385 | * The following defines are for the flags in the stack pointer write | ||
1386 | * register. | ||
1387 | */ | ||
1388 | #define SPWR_STKP_MASK 0x0000000F | ||
1389 | #define SPWR_STKP_SHIFT 0 | ||
1390 | |||
1391 | /* | ||
1392 | * The following defines are for the flags in the SP interrupt register. | ||
1393 | */ | ||
1394 | #define SPIR_FRI 0x00000001 | ||
1395 | #define SPIR_DOI 0x00000002 | ||
1396 | #define SPIR_GPI2 0x00000004 | ||
1397 | #define SPIR_GPI3 0x00000008 | ||
1398 | #define SPIR_IP0 0x00000010 | ||
1399 | #define SPIR_IP1 0x00000020 | ||
1400 | #define SPIR_IP2 0x00000040 | ||
1401 | #define SPIR_IP3 0x00000080 | ||
1402 | |||
1403 | /* | ||
1404 | * The following defines are for the flags in the functional group 1 register. | ||
1405 | */ | ||
1406 | #define FGR1_F1S_MASK 0x0000FFFF | ||
1407 | #define FGR1_F1S_SHIFT 0 | ||
1408 | |||
1409 | /* | ||
1410 | * The following defines are for the flags in the SP clock status register. | ||
1411 | */ | ||
1412 | #define SPCS_FRI 0x00000001 | ||
1413 | #define SPCS_DOI 0x00000002 | ||
1414 | #define SPCS_GPI2 0x00000004 | ||
1415 | #define SPCS_GPI3 0x00000008 | ||
1416 | #define SPCS_IP0 0x00000010 | ||
1417 | #define SPCS_IP1 0x00000020 | ||
1418 | #define SPCS_IP2 0x00000040 | ||
1419 | #define SPCS_IP3 0x00000080 | ||
1420 | #define SPCS_SPRUN 0x00000100 | ||
1421 | #define SPCS_SLEEP 0x00000200 | ||
1422 | #define SPCS_FG 0x00000400 | ||
1423 | #define SPCS_ORUN 0x00000800 | ||
1424 | #define SPCS_IRQ 0x00001000 | ||
1425 | #define SPCS_FGN_MASK 0x0000E000 | ||
1426 | #define SPCS_FGN_SHIFT 13 | ||
1427 | |||
1428 | /* | ||
1429 | * The following defines are for the flags in the SP DMA requestor status | ||
1430 | * register. | ||
1431 | */ | ||
1432 | #define SDSR_DCS_MASK 0x000000FF | ||
1433 | #define SDSR_DCS_SHIFT 0 | ||
1434 | #define SDSR_DCS_NONE 0x00000007 | ||
1435 | |||
1436 | /* | ||
1437 | * The following defines are for the flags in the frame timer register. | ||
1438 | */ | ||
1439 | #define FRMT_FTV_MASK 0x0000FFFF | ||
1440 | #define FRMT_FTV_SHIFT 0 | ||
1441 | |||
1442 | /* | ||
1443 | * The following defines are for the flags in the frame timer current count | ||
1444 | * register. | ||
1445 | */ | ||
1446 | #define FRCC_FCC_MASK 0x0000FFFF | ||
1447 | #define FRCC_FCC_SHIFT 0 | ||
1448 | |||
1449 | /* | ||
1450 | * The following defines are for the flags in the frame timer save count | ||
1451 | * register. | ||
1452 | */ | ||
1453 | #define FRSC_FCS_MASK 0x0000FFFF | ||
1454 | #define FRSC_FCS_SHIFT 0 | ||
1455 | |||
1456 | /* | ||
1457 | * The following define the various flags stored in the scatter/gather | ||
1458 | * descriptors. | ||
1459 | */ | ||
1460 | #define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8 | ||
1461 | #define DMA_SG_SAMPLE_END_MASK 0x0FFF0000 | ||
1462 | #define DMA_SG_SAMPLE_END_FLAG 0x10000000 | ||
1463 | #define DMA_SG_LOOP_END_FLAG 0x20000000 | ||
1464 | #define DMA_SG_SIGNAL_END_FLAG 0x40000000 | ||
1465 | #define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000 | ||
1466 | #define DMA_SG_NEXT_ENTRY_SHIFT 3 | ||
1467 | #define DMA_SG_SAMPLE_END_SHIFT 16 | ||
1468 | |||
1469 | /* | ||
1470 | * The following define the offsets of the fields within the on-chip generic | ||
1471 | * DMA requestor. | ||
1472 | */ | ||
1473 | #define DMA_RQ_CONTROL1 0x00000000 | ||
1474 | #define DMA_RQ_CONTROL2 0x00000004 | ||
1475 | #define DMA_RQ_SOURCE_ADDR 0x00000008 | ||
1476 | #define DMA_RQ_DESTINATION_ADDR 0x0000000C | ||
1477 | #define DMA_RQ_NEXT_PAGE_ADDR 0x00000010 | ||
1478 | #define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014 | ||
1479 | #define DMA_RQ_LOOP_START_ADDR 0x00000018 | ||
1480 | #define DMA_RQ_POST_LOOP_ADDR 0x0000001C | ||
1481 | #define DMA_RQ_PAGE_MAP_ADDR 0x00000020 | ||
1482 | |||
1483 | /* | ||
1484 | * The following defines are for the flags in the first control word of the | ||
1485 | * on-chip generic DMA requestor. | ||
1486 | */ | ||
1487 | #define DMA_RQ_C1_COUNT_MASK 0x000003FF | ||
1488 | #define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000 | ||
1489 | #define DMA_RQ_C1_SOURCE_GATHER 0x00002000 | ||
1490 | #define DMA_RQ_C1_DONE_FLAG 0x00004000 | ||
1491 | #define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000 | ||
1492 | #define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000 | ||
1493 | #define DMA_RQ_C1_FULL_PAGE 0x00000000 | ||
1494 | #define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000 | ||
1495 | #define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000 | ||
1496 | #define DMA_RQ_C1_AT_SAMPLE_END 0x00030000 | ||
1497 | #define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000 | ||
1498 | #define DMA_RQ_C1_NOT_LOOP_END 0x00000000 | ||
1499 | #define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000 | ||
1500 | #define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000 | ||
1501 | #define DMA_RQ_C1_LOOP_BEGIN 0x000C0000 | ||
1502 | #define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000 | ||
1503 | #define DMA_RQ_C1_PM_NONE_PENDING 0x00000000 | ||
1504 | #define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000 | ||
1505 | #define DMA_RQ_C1_PM_RESERVED 0x00200000 | ||
1506 | #define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000 | ||
1507 | #define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000 | ||
1508 | #define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000 | ||
1509 | #define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000 | ||
1510 | #define DMA_RQ_C1_DEST_LINEAR 0x00000000 | ||
1511 | #define DMA_RQ_C1_DEST_MOD16 0x01000000 | ||
1512 | #define DMA_RQ_C1_DEST_MOD32 0x02000000 | ||
1513 | #define DMA_RQ_C1_DEST_MOD64 0x03000000 | ||
1514 | #define DMA_RQ_C1_DEST_MOD128 0x04000000 | ||
1515 | #define DMA_RQ_C1_DEST_MOD256 0x05000000 | ||
1516 | #define DMA_RQ_C1_DEST_MOD512 0x06000000 | ||
1517 | #define DMA_RQ_C1_DEST_MOD1024 0x07000000 | ||
1518 | #define DMA_RQ_C1_DEST_ON_HOST 0x08000000 | ||
1519 | #define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000 | ||
1520 | #define DMA_RQ_C1_SOURCE_LINEAR 0x00000000 | ||
1521 | #define DMA_RQ_C1_SOURCE_MOD16 0x10000000 | ||
1522 | #define DMA_RQ_C1_SOURCE_MOD32 0x20000000 | ||
1523 | #define DMA_RQ_C1_SOURCE_MOD64 0x30000000 | ||
1524 | #define DMA_RQ_C1_SOURCE_MOD128 0x40000000 | ||
1525 | #define DMA_RQ_C1_SOURCE_MOD256 0x50000000 | ||
1526 | #define DMA_RQ_C1_SOURCE_MOD512 0x60000000 | ||
1527 | #define DMA_RQ_C1_SOURCE_MOD1024 0x70000000 | ||
1528 | #define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000 | ||
1529 | #define DMA_RQ_C1_COUNT_SHIFT 0 | ||
1530 | |||
1531 | /* | ||
1532 | * The following defines are for the flags in the second control word of the | ||
1533 | * on-chip generic DMA requestor. | ||
1534 | */ | ||
1535 | #define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003F | ||
1536 | #define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300 | ||
1537 | #define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000 | ||
1538 | #define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100 | ||
1539 | #define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200 | ||
1540 | #define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300 | ||
1541 | #define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000 | ||
1542 | #define DMA_RQ_C2_AC_NONE 0x00000000 | ||
1543 | #define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000 | ||
1544 | #define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000 | ||
1545 | #define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000 | ||
1546 | #define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000 | ||
1547 | #define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000 | ||
1548 | #define DMA_RQ_C2_LOOP_MASK 0x30000000 | ||
1549 | #define DMA_RQ_C2_NO_LOOP 0x00000000 | ||
1550 | #define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000 | ||
1551 | #define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000 | ||
1552 | #define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000 | ||
1553 | #define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000 | ||
1554 | #define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000 | ||
1555 | #define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0 | ||
1556 | #define DMA_RQ_C2_LOOP_END_SHIFT 16 | ||
1557 | |||
1558 | /* | ||
1559 | * The following defines are for the flags in the source and destination words | ||
1560 | * of the on-chip generic DMA requestor. | ||
1561 | */ | ||
1562 | #define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFF | ||
1563 | #define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000 | ||
1564 | #define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000 | ||
1565 | #define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000 | ||
1566 | #define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000 | ||
1567 | #define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000 | ||
1568 | #define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000 | ||
1569 | #define DMA_RQ_SD_END_FLAG 0x40000000 | ||
1570 | #define DMA_RQ_SD_ERROR_FLAG 0x80000000 | ||
1571 | #define DMA_RQ_SD_ADDRESS_SHIFT 0 | ||
1572 | |||
1573 | /* | ||
1574 | * The following defines are for the flags in the page map address word of the | ||
1575 | * on-chip generic DMA requestor. | ||
1576 | */ | ||
1577 | #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8 | ||
1578 | #define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000 | ||
1579 | #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3 | ||
1580 | #define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12 | ||
1581 | |||
1582 | #define BA1_VARIDEC_BUF_1 0x000 | ||
1583 | |||
1584 | #define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */ | ||
1585 | #define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */ | ||
1586 | #define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */ | ||
1587 | #define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */ | ||
1588 | #define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */ | ||
1589 | #define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */ | ||
1590 | #define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */ | ||
1591 | |||
1592 | #define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */ | ||
1593 | #define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */ | ||
1594 | #define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */ | ||
1595 | #define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */ | ||
1596 | #define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */ | ||
1597 | #define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */ | ||
1598 | #define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */ | ||
1599 | #define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */ | ||
1600 | |||
1601 | #define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */ | ||
1602 | #define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */ | ||
1603 | #define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */ | ||
1604 | #define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */ | ||
1605 | |||
1606 | /* | ||
1607 | * | ||
1608 | */ | ||
1609 | |||
1610 | #define CS46XX_MODE_OUTPUT (1<<0) /* MIDI UART - output */ | ||
1611 | #define CS46XX_MODE_INPUT (1<<1) /* MIDI UART - input */ | ||
1612 | |||
1613 | /* | ||
1614 | * | ||
1615 | */ | ||
1616 | |||
1617 | #define SAVE_REG_MAX 0x10 | ||
1618 | #define POWER_DOWN_ALL 0x7f0f | ||
1619 | |||
1620 | /* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */ | ||
1621 | #define MAX_NR_AC97 4 | ||
1622 | #define CS46XX_PRIMARY_CODEC_INDEX 0 | ||
1623 | #define CS46XX_SECONDARY_CODEC_INDEX 1 | ||
1624 | #define CS46XX_SECONDARY_CODEC_OFFSET 0x80 | ||
1625 | #define CS46XX_DSP_CAPTURE_CHANNEL 1 | ||
1626 | |||
1627 | /* capture */ | ||
1628 | #define CS46XX_DSP_CAPTURE_CHANNEL 1 | ||
1629 | |||
1630 | /* mixer */ | ||
1631 | #define CS46XX_MIXER_SPDIF_INPUT_ELEMENT 1 | ||
1632 | #define CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT 2 | ||
1633 | |||
1634 | |||
1635 | struct snd_cs46xx_pcm { | ||
1636 | struct snd_dma_buffer hw_buf; | ||
1637 | |||
1638 | unsigned int ctl; | ||
1639 | unsigned int shift; /* Shift count to trasform frames in bytes */ | ||
1640 | struct snd_pcm_indirect pcm_rec; | ||
1641 | struct snd_pcm_substream *substream; | ||
1642 | |||
1643 | struct dsp_pcm_channel_descriptor * pcm_channel; | ||
1644 | |||
1645 | int pcm_channel_id; /* Fron Rear, Center Lfe ... */ | ||
1646 | }; | ||
1647 | |||
1648 | struct snd_cs46xx_region { | ||
1649 | char name[24]; | ||
1650 | unsigned long base; | ||
1651 | void __iomem *remap_addr; | ||
1652 | unsigned long size; | ||
1653 | struct resource *resource; | ||
1654 | }; | ||
1655 | |||
1656 | struct snd_cs46xx { | ||
1657 | int irq; | ||
1658 | unsigned long ba0_addr; | ||
1659 | unsigned long ba1_addr; | ||
1660 | union { | ||
1661 | struct { | ||
1662 | struct snd_cs46xx_region ba0; | ||
1663 | struct snd_cs46xx_region data0; | ||
1664 | struct snd_cs46xx_region data1; | ||
1665 | struct snd_cs46xx_region pmem; | ||
1666 | struct snd_cs46xx_region reg; | ||
1667 | } name; | ||
1668 | struct snd_cs46xx_region idx[5]; | ||
1669 | } region; | ||
1670 | |||
1671 | unsigned int mode; | ||
1672 | |||
1673 | struct { | ||
1674 | struct snd_dma_buffer hw_buf; | ||
1675 | |||
1676 | unsigned int ctl; | ||
1677 | unsigned int shift; /* Shift count to trasform frames in bytes */ | ||
1678 | struct snd_pcm_indirect pcm_rec; | ||
1679 | struct snd_pcm_substream *substream; | ||
1680 | } capt; | ||
1681 | |||
1682 | |||
1683 | int nr_ac97_codecs; | ||
1684 | struct snd_ac97_bus *ac97_bus; | ||
1685 | struct snd_ac97 *ac97[MAX_NR_AC97]; | ||
1686 | |||
1687 | struct pci_dev *pci; | ||
1688 | struct snd_card *card; | ||
1689 | struct snd_pcm *pcm; | ||
1690 | |||
1691 | struct snd_rawmidi *rmidi; | ||
1692 | struct snd_rawmidi_substream *midi_input; | ||
1693 | struct snd_rawmidi_substream *midi_output; | ||
1694 | |||
1695 | spinlock_t reg_lock; | ||
1696 | unsigned int midcr; | ||
1697 | unsigned int uartm; | ||
1698 | |||
1699 | int amplifier; | ||
1700 | void (*amplifier_ctrl)(struct snd_cs46xx *, int); | ||
1701 | void (*active_ctrl)(struct snd_cs46xx *, int); | ||
1702 | void (*mixer_init)(struct snd_cs46xx *); | ||
1703 | |||
1704 | int acpi_port; | ||
1705 | struct snd_kcontrol *eapd_switch; /* for amplifier hack */ | ||
1706 | int accept_valid; /* accept mmap valid (for OSS) */ | ||
1707 | int in_suspend; | ||
1708 | |||
1709 | struct gameport *gameport; | ||
1710 | |||
1711 | #ifdef CONFIG_SND_CS46XX_NEW_DSP | ||
1712 | struct mutex spos_mutex; | ||
1713 | |||
1714 | struct dsp_spos_instance * dsp_spos_instance; | ||
1715 | |||
1716 | struct snd_pcm *pcm_rear; | ||
1717 | struct snd_pcm *pcm_center_lfe; | ||
1718 | struct snd_pcm *pcm_iec958; | ||
1719 | #else /* for compatibility */ | ||
1720 | struct snd_cs46xx_pcm *playback_pcm; | ||
1721 | unsigned int play_ctl; | ||
1722 | #endif | ||
1723 | |||
1724 | #ifdef CONFIG_PM | ||
1725 | u32 *saved_regs; | ||
1726 | #endif | ||
1727 | }; | ||
1728 | |||
1729 | int snd_cs46xx_create(struct snd_card *card, | ||
1730 | struct pci_dev *pci, | ||
1731 | int external_amp, int thinkpad, | ||
1732 | struct snd_cs46xx **rcodec); | ||
1733 | int snd_cs46xx_suspend(struct pci_dev *pci, pm_message_t state); | ||
1734 | int snd_cs46xx_resume(struct pci_dev *pci); | ||
1735 | |||
1736 | int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device, struct snd_pcm **rpcm); | ||
1737 | int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device, struct snd_pcm **rpcm); | ||
1738 | int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device, struct snd_pcm **rpcm); | ||
1739 | int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device, struct snd_pcm **rpcm); | ||
1740 | int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device); | ||
1741 | int snd_cs46xx_midi(struct snd_cs46xx *chip, int device, struct snd_rawmidi **rmidi); | ||
1742 | int snd_cs46xx_start_dsp(struct snd_cs46xx *chip); | ||
1743 | int snd_cs46xx_gameport(struct snd_cs46xx *chip); | ||
1744 | |||
1745 | #endif /* __SOUND_CS46XX_H */ | ||
diff --git a/include/sound/cs46xx_dsp_scb_types.h b/include/sound/cs46xx_dsp_scb_types.h deleted file mode 100644 index 080857ad0ca2..000000000000 --- a/include/sound/cs46xx_dsp_scb_types.h +++ /dev/null | |||
@@ -1,1213 +0,0 @@ | |||
1 | /* | ||
2 | * The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards | ||
3 | * Copyright (c) by Jaroslav Kysela <perex@perex.cz> | ||
4 | * | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | * | ||
20 | * | ||
21 | * NOTE: comments are copy/paste from cwcemb80.lst | ||
22 | * provided by Tom Woller at Cirrus (my only | ||
23 | * documentation about the SP OS running inside | ||
24 | * the DSP) | ||
25 | */ | ||
26 | |||
27 | #ifndef __CS46XX_DSP_SCB_TYPES_H__ | ||
28 | #define __CS46XX_DSP_SCB_TYPES_H__ | ||
29 | |||
30 | #include <asm/byteorder.h> | ||
31 | |||
32 | #ifndef ___DSP_DUAL_16BIT_ALLOC | ||
33 | #if defined(__LITTLE_ENDIAN) | ||
34 | #define ___DSP_DUAL_16BIT_ALLOC(a,b) u16 a; u16 b; | ||
35 | #elif defined(__BIG_ENDIAN) | ||
36 | #define ___DSP_DUAL_16BIT_ALLOC(a,b) u16 b; u16 a; | ||
37 | #else | ||
38 | #error Not __LITTLE_ENDIAN and not __BIG_ENDIAN, then what ??? | ||
39 | #endif | ||
40 | #endif | ||
41 | |||
42 | /* This structs are used internally by the SP */ | ||
43 | |||
44 | struct dsp_basic_dma_req { | ||
45 | /* DMA Requestor Word 0 (DCW) fields: | ||
46 | |||
47 | 31 [30-28]27 [26:24] 23 22 21 20 [19:18] [17:16] 15 14 13 12 11 10 9 8 7 6 [5:0] | ||
48 | _______________________________________________________________________________________ | ||
49 | |S| SBT |D| DBT |wb|wb| | | LS | SS |Opt|Do|SSG|DSG| | | | | | | Dword | | ||
50 | |H|_____ |H|_________|S_|D |__|__|______|_______|___|ne|__ |__ |__|__|_|_|_|_|_Count -1| | ||
51 | */ | ||
52 | u32 dcw; /* DMA Control Word */ | ||
53 | u32 dmw; /* DMA Mode Word */ | ||
54 | u32 saw; /* Source Address Word */ | ||
55 | u32 daw; /* Destination Address Word */ | ||
56 | }; | ||
57 | |||
58 | struct dsp_scatter_gather_ext { | ||
59 | u32 npaw; /* Next-Page Address Word */ | ||
60 | |||
61 | /* DMA Requestor Word 5 (NPCW) fields: | ||
62 | |||
63 | 31-30 29 28 [27:16] [15:12] [11:3] [2:0] | ||
64 | _________________________________________________________________________________________ | ||
65 | |SV |LE|SE| Sample-end byte offset | | Page-map entry offset for next | | | ||
66 | |page|__|__| ___________________________|_________|__page, if !sample-end___________|____| | ||
67 | */ | ||
68 | u32 npcw; /* Next-Page Control Word */ | ||
69 | u32 lbaw; /* Loop-Begin Address Word */ | ||
70 | u32 nplbaw; /* Next-Page after Loop-Begin Address Word */ | ||
71 | u32 sgaw; /* Scatter/Gather Address Word */ | ||
72 | }; | ||
73 | |||
74 | struct dsp_volume_control { | ||
75 | ___DSP_DUAL_16BIT_ALLOC( | ||
76 | rightTarg, /* Target volume for left & right channels */ | ||
77 | leftTarg | ||
78 | ) | ||
79 | ___DSP_DUAL_16BIT_ALLOC( | ||
80 | rightVol, /* Current left & right channel volumes */ | ||
81 | leftVol | ||
82 | ) | ||
83 | }; | ||
84 | |||
85 | /* Generic stream control block (SCB) structure definition */ | ||
86 | struct dsp_generic_scb { | ||
87 | /* For streaming I/O, the DSP should never alter any words in the DMA | ||
88 | requestor or the scatter/gather extension. Only ad hoc DMA request | ||
89 | streams are free to alter the requestor (currently only occur in the | ||
90 | DOS-based MIDI controller and in debugger-inserted code). | ||
91 | |||
92 | If an SCB does not have any associated DMA requestor, these 9 ints | ||
93 | may be freed for use by other tasks, but the pointer to the SCB must | ||
94 | still be such that the insOrd:nextSCB appear at offset 9 from the | ||
95 | SCB pointer. | ||
96 | |||
97 | Basic (non scatter/gather) DMA requestor (4 ints) | ||
98 | */ | ||
99 | |||
100 | /* Initialized by the host, only modified by DMA | ||
101 | R/O for the DSP task */ | ||
102 | struct dsp_basic_dma_req basic_req; /* Optional */ | ||
103 | |||
104 | /* Scatter/gather DMA requestor extension (5 ints) | ||
105 | Initialized by the host, only modified by DMA | ||
106 | DSP task never needs to even read these. | ||
107 | */ | ||
108 | struct dsp_scatter_gather_ext sg_ext; /* Optional */ | ||
109 | |||
110 | /* Sublist pointer & next stream control block (SCB) link. | ||
111 | Initialized & modified by the host R/O for the DSP task | ||
112 | */ | ||
113 | ___DSP_DUAL_16BIT_ALLOC( | ||
114 | next_scb, /* REQUIRED */ | ||
115 | sub_list_ptr /* REQUIRED */ | ||
116 | ) | ||
117 | |||
118 | /* Pointer to this tasks parameter block & stream function pointer | ||
119 | Initialized by the host R/O for the DSP task */ | ||
120 | ___DSP_DUAL_16BIT_ALLOC( | ||
121 | entry_point, /* REQUIRED */ | ||
122 | this_spb /* REQUIRED */ | ||
123 | ) | ||
124 | |||
125 | /* rsConfig register for stream buffer (rsDMA reg. | ||
126 | is loaded from basicReq.daw for incoming streams, or | ||
127 | basicReq.saw, for outgoing streams) | ||
128 | |||
129 | 31 30 29 [28:24] [23:16] 15 14 13 12 11 10 9 8 7 6 5 4 [3:0] | ||
130 | ______________________________________________________________________________ | ||
131 | |DMA |D|maxDMAsize| streamNum|dir|p| | | | | | |ds |shr 1|rev Cy | mod | | ||
132 | |prio |_|__________|__________|___|_|__|__|__|__|_|_|___|_____|_______|_______| | ||
133 | 31 30 29 [28:24] [23:16] 15 14 13 12 11 10 9 8 7 6 5 4 [3:0] | ||
134 | |||
135 | |||
136 | Initialized by the host R/O for the DSP task | ||
137 | */ | ||
138 | u32 strm_rs_config; /* REQUIRED */ | ||
139 | // | ||
140 | /* On mixer input streams: indicates mixer input stream configuration | ||
141 | On Tees, this is copied from the stream being snooped | ||
142 | |||
143 | Stream sample pointer & MAC-unit mode for this stream | ||
144 | |||
145 | Initialized by the host Updated by the DSP task | ||
146 | */ | ||
147 | u32 strm_buf_ptr; /* REQUIRED */ | ||
148 | |||
149 | /* On mixer input streams: points to next mixer input and is updated by the | ||
150 | mixer subroutine in the "parent" DSP task | ||
151 | (least-significant 16 bits are preserved, unused) | ||
152 | |||
153 | On Tees, the pointer is copied from the stream being snooped on | ||
154 | initialization, and, subsequently, it is copied into the | ||
155 | stream being snooped. | ||
156 | |||
157 | On wavetable/3D voices: the strmBufPtr will use all 32 bits to allow for | ||
158 | fractional phase accumulation | ||
159 | |||
160 | Fractional increment per output sample in the input sample buffer | ||
161 | |||
162 | (Not used on mixer input streams & redefined on Tees) | ||
163 | On wavetable/3D voices: this 32-bit word specifies the integer.fractional | ||
164 | increment per output sample. | ||
165 | */ | ||
166 | u32 strmPhiIncr; | ||
167 | |||
168 | |||
169 | /* Standard stereo volume control | ||
170 | Initialized by the host (host updates target volumes) | ||
171 | |||
172 | Current volumes update by the DSP task | ||
173 | On mixer input streams: required & updated by the mixer subroutine in the | ||
174 | "parent" DSP task | ||
175 | |||
176 | On Tees, both current & target volumes are copied up on initialization, | ||
177 | and, subsequently, the target volume is copied up while the current | ||
178 | volume is copied down. | ||
179 | |||
180 | These two 32-bit words are redefined for wavetable & 3-D voices. | ||
181 | */ | ||
182 | struct dsp_volume_control vol_ctrl_t; /* Optional */ | ||
183 | }; | ||
184 | |||
185 | |||
186 | struct dsp_spos_control_block { | ||
187 | /* WARNING: Certain items in this structure are modified by the host | ||
188 | Any dword that can be modified by the host, must not be | ||
189 | modified by the SP as the host can only do atomic dword | ||
190 | writes, and to do otherwise, even a read modify write, | ||
191 | may lead to corrupted data on the SP. | ||
192 | |||
193 | This rule does not apply to one off boot time initialisation prior to starting the SP | ||
194 | */ | ||
195 | |||
196 | |||
197 | ___DSP_DUAL_16BIT_ALLOC( | ||
198 | /* First element on the Hyper forground task tree */ | ||
199 | hfg_tree_root_ptr, /* HOST */ | ||
200 | /* First 3 dwords are written by the host and read-only on the DSP */ | ||
201 | hfg_stack_base /* HOST */ | ||
202 | ) | ||
203 | |||
204 | ___DSP_DUAL_16BIT_ALLOC( | ||
205 | /* Point to this data structure to enable easy access */ | ||
206 | spos_cb_ptr, /* SP */ | ||
207 | prev_task_tree_ptr /* SP && HOST */ | ||
208 | ) | ||
209 | |||
210 | ___DSP_DUAL_16BIT_ALLOC( | ||
211 | /* Currently Unused */ | ||
212 | xxinterval_timer_period, | ||
213 | /* Enable extension of SPOS data structure */ | ||
214 | HFGSPB_ptr | ||
215 | ) | ||
216 | |||
217 | |||
218 | ___DSP_DUAL_16BIT_ALLOC( | ||
219 | xxnum_HFG_ticks_thisInterval, | ||
220 | /* Modified by the DSP */ | ||
221 | xxnum_tntervals | ||
222 | ) | ||
223 | |||
224 | |||
225 | /* Set by DSP upon encountering a trap (breakpoint) or a spurious | ||
226 | interrupt. The host must clear this dword after reading it | ||
227 | upon receiving spInt1. */ | ||
228 | ___DSP_DUAL_16BIT_ALLOC( | ||
229 | spurious_int_flag, /* (Host & SP) Nature of the spurious interrupt */ | ||
230 | trap_flag /* (Host & SP) Nature of detected Trap */ | ||
231 | ) | ||
232 | |||
233 | ___DSP_DUAL_16BIT_ALLOC( | ||
234 | unused2, | ||
235 | invalid_IP_flag /* (Host & SP ) Indicate detection of invalid instruction pointer */ | ||
236 | ) | ||
237 | |||
238 | ___DSP_DUAL_16BIT_ALLOC( | ||
239 | /* pointer to forground task tree header for use in next task search */ | ||
240 | fg_task_tree_hdr_ptr, /* HOST */ | ||
241 | /* Data structure for controlling synchronous link update */ | ||
242 | hfg_sync_update_ptr /* HOST */ | ||
243 | ) | ||
244 | |||
245 | ___DSP_DUAL_16BIT_ALLOC( | ||
246 | begin_foreground_FCNT, /* SP */ | ||
247 | /* Place holder for holding sleep timing */ | ||
248 | last_FCNT_before_sleep /* SP */ | ||
249 | ) | ||
250 | |||
251 | ___DSP_DUAL_16BIT_ALLOC( | ||
252 | unused7, /* SP */ | ||
253 | next_task_treePtr /* SP */ | ||
254 | ) | ||
255 | |||
256 | u32 unused5; | ||
257 | |||
258 | ___DSP_DUAL_16BIT_ALLOC( | ||
259 | active_flags, /* SP */ | ||
260 | /* State flags, used to assist control of execution of Hyper Forground */ | ||
261 | HFG_flags /* SP */ | ||
262 | ) | ||
263 | |||
264 | ___DSP_DUAL_16BIT_ALLOC( | ||
265 | unused9, | ||
266 | unused8 | ||
267 | ) | ||
268 | |||
269 | /* Space for saving enough context so that we can set up enough | ||
270 | to save some more context. | ||
271 | */ | ||
272 | u32 rFE_save_for_invalid_IP; | ||
273 | u32 r32_save_for_spurious_int; | ||
274 | u32 r32_save_for_trap; | ||
275 | u32 r32_save_for_HFG; | ||
276 | }; | ||
277 | |||
278 | /* SPB for MIX_TO_OSTREAM algorithm family */ | ||
279 | struct dsp_mix2_ostream_spb | ||
280 | { | ||
281 | /* 16b.16b integer.frac approximation to the | ||
282 | number of 3 sample triplets to output each | ||
283 | frame. (approximation must be floor, to | ||
284 | insure that the fractional error is always | ||
285 | positive) | ||
286 | */ | ||
287 | u32 outTripletsPerFrame; | ||
288 | |||
289 | /* 16b.16b integer.frac accumulated number of | ||
290 | output triplets since the start of group | ||
291 | */ | ||
292 | u32 accumOutTriplets; | ||
293 | }; | ||
294 | |||
295 | /* SCB for Timing master algorithm */ | ||
296 | struct dsp_timing_master_scb { | ||
297 | /* First 12 dwords from generic_scb_t */ | ||
298 | struct dsp_basic_dma_req basic_req; /* Optional */ | ||
299 | struct dsp_scatter_gather_ext sg_ext; /* Optional */ | ||
300 | ___DSP_DUAL_16BIT_ALLOC( | ||
301 | next_scb, /* REQUIRED */ | ||
302 | sub_list_ptr /* REQUIRED */ | ||
303 | ) | ||
304 | |||
305 | ___DSP_DUAL_16BIT_ALLOC( | ||
306 | entry_point, /* REQUIRED */ | ||
307 | this_spb /* REQUIRED */ | ||
308 | ) | ||
309 | |||
310 | ___DSP_DUAL_16BIT_ALLOC( | ||
311 | /* Initial values are 0000:xxxx */ | ||
312 | reserved, | ||
313 | extra_sample_accum | ||
314 | ) | ||
315 | |||
316 | |||
317 | /* Initial values are xxxx:0000 | ||
318 | hi: Current CODEC output FIFO pointer | ||
319 | (0 to 0x0f) | ||
320 | lo: Flag indicating that the CODEC | ||
321 | FIFO is sync'd (host clears to | ||
322 | resynchronize the FIFO pointer | ||
323 | upon start/restart) | ||
324 | */ | ||
325 | ___DSP_DUAL_16BIT_ALLOC( | ||
326 | codec_FIFO_syncd, | ||
327 | codec_FIFO_ptr | ||
328 | ) | ||
329 | |||
330 | /* Init. 8000:0005 for 44.1k | ||
331 | 8000:0001 for 48k | ||
332 | hi: Fractional sample accumulator 0.16b | ||
333 | lo: Number of frames remaining to be | ||
334 | processed in the current group of | ||
335 | frames | ||
336 | */ | ||
337 | ___DSP_DUAL_16BIT_ALLOC( | ||
338 | frac_samp_accum_qm1, | ||
339 | TM_frms_left_in_group | ||
340 | ) | ||
341 | |||
342 | /* Init. 0001:0005 for 44.1k | ||
343 | 0000:0001 for 48k | ||
344 | hi: Fractional sample correction factor 0.16b | ||
345 | to be added every frameGroupLength frames | ||
346 | to correct for truncation error in | ||
347 | nsamp_per_frm_q15 | ||
348 | lo: Number of frames in the group | ||
349 | */ | ||
350 | ___DSP_DUAL_16BIT_ALLOC( | ||
351 | frac_samp_correction_qm1, | ||
352 | TM_frm_group_length | ||
353 | ) | ||
354 | |||
355 | /* Init. 44.1k*65536/8k = 0x00058333 for 44.1k | ||
356 | 48k*65536/8k = 0x00060000 for 48k | ||
357 | 16b.16b integer.frac approximation to the | ||
358 | number of samples to output each frame. | ||
359 | (approximation must be floor, to insure */ | ||
360 | u32 nsamp_per_frm_q15; | ||
361 | }; | ||
362 | |||
363 | /* SCB for CODEC output algorithm */ | ||
364 | struct dsp_codec_output_scb { | ||
365 | /* First 13 dwords from generic_scb_t */ | ||
366 | struct dsp_basic_dma_req basic_req; /* Optional */ | ||
367 | struct dsp_scatter_gather_ext sg_ext; /* Optional */ | ||
368 | ___DSP_DUAL_16BIT_ALLOC( | ||
369 | next_scb, /* REQUIRED */ | ||
370 | sub_list_ptr /* REQUIRED */ | ||
371 | ) | ||
372 | |||
373 | ___DSP_DUAL_16BIT_ALLOC( | ||
374 | entry_point, /* REQUIRED */ | ||
375 | this_spb /* REQUIRED */ | ||
376 | ) | ||
377 | |||
378 | u32 strm_rs_config; /* REQUIRED */ | ||
379 | |||
380 | u32 strm_buf_ptr; /* REQUIRED */ | ||
381 | |||
382 | /* NOTE: The CODEC output task reads samples from the first task on its | ||
383 | sublist at the stream buffer pointer (init. to lag DMA destination | ||
384 | address word). After the required number of samples is transferred, | ||
385 | the CODEC output task advances sub_list_ptr->strm_buf_ptr past the samples | ||
386 | consumed. | ||
387 | */ | ||
388 | |||
389 | /* Init. 0000:0010 for SDout | ||
390 | 0060:0010 for SDout2 | ||
391 | 0080:0010 for SDout3 | ||
392 | hi: Base IO address of FIFO to which | ||
393 | the left-channel samples are to | ||
394 | be written. | ||
395 | lo: Displacement for the base IO | ||
396 | address for left-channel to obtain | ||
397 | the base IO address for the FIFO | ||
398 | to which the right-channel samples | ||
399 | are to be written. | ||
400 | */ | ||
401 | ___DSP_DUAL_16BIT_ALLOC( | ||
402 | left_chan_base_IO_addr, | ||
403 | right_chan_IO_disp | ||
404 | ) | ||
405 | |||
406 | |||
407 | /* Init: 0x0080:0004 for non-AC-97 | ||
408 | Init: 0x0080:0000 for AC-97 | ||
409 | hi: Exponential volume change rate | ||
410 | for input stream | ||
411 | lo: Positive shift count to shift the | ||
412 | 16-bit input sample to obtain the | ||
413 | 32-bit output word | ||
414 | */ | ||
415 | ___DSP_DUAL_16BIT_ALLOC( | ||
416 | CO_scale_shift_count, | ||
417 | CO_exp_vol_change_rate | ||
418 | ) | ||
419 | |||
420 | /* Pointer to SCB at end of input chain */ | ||
421 | ___DSP_DUAL_16BIT_ALLOC( | ||
422 | reserved, | ||
423 | last_sub_ptr | ||
424 | ) | ||
425 | }; | ||
426 | |||
427 | /* SCB for CODEC input algorithm */ | ||
428 | struct dsp_codec_input_scb { | ||
429 | /* First 13 dwords from generic_scb_t */ | ||
430 | struct dsp_basic_dma_req basic_req; /* Optional */ | ||
431 | struct dsp_scatter_gather_ext sg_ext; /* Optional */ | ||
432 | ___DSP_DUAL_16BIT_ALLOC( | ||
433 | next_scb, /* REQUIRED */ | ||
434 | sub_list_ptr /* REQUIRED */ | ||
435 | ) | ||
436 | |||
437 | ___DSP_DUAL_16BIT_ALLOC( | ||
438 | entry_point, /* REQUIRED */ | ||
439 | this_spb /* REQUIRED */ | ||
440 | ) | ||
441 | |||
442 | u32 strm_rs_config; /* REQUIRED */ | ||
443 | u32 strm_buf_ptr; /* REQUIRED */ | ||
444 | |||
445 | /* NOTE: The CODEC input task reads samples from the hardware FIFO | ||
446 | sublist at the DMA source address word (sub_list_ptr->basic_req.saw). | ||
447 | After the required number of samples is transferred, the CODEC | ||
448 | output task advances sub_list_ptr->basic_req.saw past the samples | ||
449 | consumed. SPuD must initialize the sub_list_ptr->basic_req.saw | ||
450 | to point half-way around from the initial sub_list_ptr->strm_nuf_ptr | ||
451 | to allow for lag/lead. | ||
452 | */ | ||
453 | |||
454 | /* Init. 0000:0010 for SDout | ||
455 | 0060:0010 for SDout2 | ||
456 | 0080:0010 for SDout3 | ||
457 | hi: Base IO address of FIFO to which | ||
458 | the left-channel samples are to | ||
459 | be written. | ||
460 | lo: Displacement for the base IO | ||
461 | address for left-channel to obtain | ||
462 | the base IO address for the FIFO | ||
463 | to which the right-channel samples | ||
464 | are to be written. | ||
465 | */ | ||
466 | ___DSP_DUAL_16BIT_ALLOC( | ||
467 | rightChanINdisp, | ||
468 | left_chan_base_IN_addr | ||
469 | ) | ||
470 | /* Init. ?:fffc | ||
471 | lo: Negative shift count to shift the | ||
472 | 32-bit input dword to obtain the | ||
473 | 16-bit sample msb-aligned (count | ||
474 | is negative to shift left) | ||
475 | */ | ||
476 | ___DSP_DUAL_16BIT_ALLOC( | ||
477 | scaleShiftCount, | ||
478 | reserver1 | ||
479 | ) | ||
480 | |||
481 | u32 reserved2; | ||
482 | }; | ||
483 | |||
484 | |||
485 | struct dsp_pcm_serial_input_scb { | ||
486 | /* First 13 dwords from generic_scb_t */ | ||
487 | struct dsp_basic_dma_req basic_req; /* Optional */ | ||
488 | struct dsp_scatter_gather_ext sg_ext; /* Optional */ | ||
489 | ___DSP_DUAL_16BIT_ALLOC( | ||
490 | next_scb, /* REQUIRED */ | ||
491 | sub_list_ptr /* REQUIRED */ | ||
492 | ) | ||
493 | |||
494 | ___DSP_DUAL_16BIT_ALLOC( | ||
495 | entry_point, /* REQUIRED */ | ||
496 | this_spb /* REQUIRED */ | ||
497 | ) | ||
498 | |||
499 | u32 strm_buf_ptr; /* REQUIRED */ | ||
500 | u32 strm_rs_config; /* REQUIRED */ | ||
501 | |||
502 | /* Init. Ptr to CODEC input SCB | ||
503 | hi: Pointer to the SCB containing the | ||
504 | input buffer to which CODEC input | ||
505 | samples are written | ||
506 | lo: Flag indicating the link to the CODEC | ||
507 | input task is to be initialized | ||
508 | */ | ||
509 | ___DSP_DUAL_16BIT_ALLOC( | ||
510 | init_codec_input_link, | ||
511 | codec_input_buf_scb | ||
512 | ) | ||
513 | |||
514 | /* Initialized by the host (host updates target volumes) */ | ||
515 | struct dsp_volume_control psi_vol_ctrl; | ||
516 | |||
517 | }; | ||
518 | |||
519 | struct dsp_src_task_scb { | ||
520 | ___DSP_DUAL_16BIT_ALLOC( | ||
521 | frames_left_in_gof, | ||
522 | gofs_left_in_sec | ||
523 | ) | ||
524 | |||
525 | ___DSP_DUAL_16BIT_ALLOC( | ||
526 | const2_thirds, | ||
527 | num_extra_tnput_samples | ||
528 | ) | ||
529 | |||
530 | ___DSP_DUAL_16BIT_ALLOC( | ||
531 | cor_per_gof, | ||
532 | correction_per_sec | ||
533 | ) | ||
534 | |||
535 | ___DSP_DUAL_16BIT_ALLOC( | ||
536 | output_buf_producer_ptr, | ||
537 | junk_DMA_MID | ||
538 | ) | ||
539 | |||
540 | ___DSP_DUAL_16BIT_ALLOC( | ||
541 | gof_length, | ||
542 | gofs_per_sec | ||
543 | ) | ||
544 | |||
545 | u32 input_buf_strm_config; | ||
546 | |||
547 | ___DSP_DUAL_16BIT_ALLOC( | ||
548 | reserved_for_SRC_use, | ||
549 | input_buf_consumer_ptr | ||
550 | ) | ||
551 | |||
552 | u32 accum_phi; | ||
553 | |||
554 | ___DSP_DUAL_16BIT_ALLOC( | ||
555 | exp_src_vol_change_rate, | ||
556 | input_buf_producer_ptr | ||
557 | ) | ||
558 | |||
559 | ___DSP_DUAL_16BIT_ALLOC( | ||
560 | src_next_scb, | ||
561 | src_sub_list_ptr | ||
562 | ) | ||
563 | |||
564 | ___DSP_DUAL_16BIT_ALLOC( | ||
565 | src_entry_point, | ||
566 | src_this_sbp | ||
567 | ) | ||
568 | |||
569 | u32 src_strm_rs_config; | ||
570 | u32 src_strm_buf_ptr; | ||
571 | |||
572 | u32 phiIncr6int_26frac; | ||
573 | |||
574 | struct dsp_volume_control src_vol_ctrl; | ||
575 | }; | ||
576 | |||
577 | struct dsp_decimate_by_pow2_scb { | ||
578 | /* decimationFactor = 2, 4, or 8 (larger factors waste too much memory | ||
579 | when compared to cascading decimators) | ||
580 | */ | ||
581 | ___DSP_DUAL_16BIT_ALLOC( | ||
582 | dec2_coef_base_ptr, | ||
583 | dec2_coef_increment | ||
584 | ) | ||
585 | |||
586 | /* coefIncrement = 128 / decimationFactor (for our ROM filter) | ||
587 | coefBasePtr = 0x8000 (for our ROM filter) | ||
588 | */ | ||
589 | ___DSP_DUAL_16BIT_ALLOC( | ||
590 | dec2_in_samples_per_out_triplet, | ||
591 | dec2_extra_in_samples | ||
592 | ) | ||
593 | /* extraInSamples: # of accumulated, unused input samples (init. to 0) | ||
594 | inSamplesPerOutTriplet = 3 * decimationFactor | ||
595 | */ | ||
596 | |||
597 | ___DSP_DUAL_16BIT_ALLOC( | ||
598 | dec2_const2_thirds, | ||
599 | dec2_half_num_taps_mp5 | ||
600 | ) | ||
601 | /* halfNumTapsM5: (1/2 number of taps in decimation filter) minus 5 | ||
602 | const2thirds: constant 2/3 in 16Q0 format (sign.15) | ||
603 | */ | ||
604 | |||
605 | ___DSP_DUAL_16BIT_ALLOC( | ||
606 | dec2_output_buf_producer_ptr, | ||
607 | dec2_junkdma_mid | ||
608 | ) | ||
609 | |||
610 | u32 dec2_reserved2; | ||
611 | |||
612 | u32 dec2_input_nuf_strm_config; | ||
613 | /* inputBufStrmConfig: rsConfig for the input buffer to the decimator | ||
614 | (buffer size = decimationFactor * 32 dwords) | ||
615 | */ | ||
616 | |||
617 | ___DSP_DUAL_16BIT_ALLOC( | ||
618 | dec2_phi_incr, | ||
619 | dec2_input_buf_consumer_ptr | ||
620 | ) | ||
621 | /* inputBufConsumerPtr: Input buffer read pointer (into SRC filter) | ||
622 | phiIncr = decimationFactor * 4 | ||
623 | */ | ||
624 | |||
625 | u32 dec2_reserved3; | ||
626 | |||
627 | ___DSP_DUAL_16BIT_ALLOC( | ||
628 | dec2_exp_vol_change_rate, | ||
629 | dec2_input_buf_producer_ptr | ||
630 | ) | ||
631 | /* inputBufProducerPtr: Input buffer write pointer | ||
632 | expVolChangeRate: Exponential volume change rate for possible | ||
633 | future mixer on input streams | ||
634 | */ | ||
635 | |||
636 | ___DSP_DUAL_16BIT_ALLOC( | ||
637 | dec2_next_scb, | ||
638 | dec2_sub_list_ptr | ||
639 | ) | ||
640 | |||
641 | ___DSP_DUAL_16BIT_ALLOC( | ||
642 | dec2_entry_point, | ||
643 | dec2_this_spb | ||
644 | ) | ||
645 | |||
646 | u32 dec2_strm_rs_config; | ||
647 | u32 dec2_strm_buf_ptr; | ||
648 | |||
649 | u32 dec2_reserved4; | ||
650 | |||
651 | struct dsp_volume_control dec2_vol_ctrl; /* Not used! */ | ||
652 | }; | ||
653 | |||
654 | struct dsp_vari_decimate_scb { | ||
655 | ___DSP_DUAL_16BIT_ALLOC( | ||
656 | vdec_frames_left_in_gof, | ||
657 | vdec_gofs_left_in_sec | ||
658 | ) | ||
659 | |||
660 | ___DSP_DUAL_16BIT_ALLOC( | ||
661 | vdec_const2_thirds, | ||
662 | vdec_extra_in_samples | ||
663 | ) | ||
664 | /* extraInSamples: # of accumulated, unused input samples (init. to 0) | ||
665 | const2thirds: constant 2/3 in 16Q0 format (sign.15) */ | ||
666 | |||
667 | ___DSP_DUAL_16BIT_ALLOC( | ||
668 | vdec_cor_per_gof, | ||
669 | vdec_correction_per_sec | ||
670 | ) | ||
671 | |||
672 | ___DSP_DUAL_16BIT_ALLOC( | ||
673 | vdec_output_buf_producer_ptr, | ||
674 | vdec_input_buf_consumer_ptr | ||
675 | ) | ||
676 | /* inputBufConsumerPtr: Input buffer read pointer (into SRC filter) */ | ||
677 | ___DSP_DUAL_16BIT_ALLOC( | ||
678 | vdec_gof_length, | ||
679 | vdec_gofs_per_sec | ||
680 | ) | ||
681 | |||
682 | u32 vdec_input_buf_strm_config; | ||
683 | /* inputBufStrmConfig: rsConfig for the input buffer to the decimator | ||
684 | (buffer size = 64 dwords) */ | ||
685 | u32 vdec_coef_increment; | ||
686 | /* coefIncrement = - 128.0 / decimationFactor (as a 32Q15 number) */ | ||
687 | |||
688 | u32 vdec_accumphi; | ||
689 | /* accumPhi: accumulated fractional phase increment (6.26) */ | ||
690 | |||
691 | ___DSP_DUAL_16BIT_ALLOC( | ||
692 | vdec_exp_vol_change_rate, | ||
693 | vdec_input_buf_producer_ptr | ||
694 | ) | ||
695 | /* inputBufProducerPtr: Input buffer write pointer | ||
696 | expVolChangeRate: Exponential volume change rate for possible | ||
697 | future mixer on input streams */ | ||
698 | |||
699 | ___DSP_DUAL_16BIT_ALLOC( | ||
700 | vdec_next_scb, | ||
701 | vdec_sub_list_ptr | ||
702 | ) | ||
703 | |||
704 | ___DSP_DUAL_16BIT_ALLOC( | ||
705 | vdec_entry_point, | ||
706 | vdec_this_spb | ||
707 | ) | ||
708 | |||
709 | u32 vdec_strm_rs_config; | ||
710 | u32 vdec_strm_buf_ptr; | ||
711 | |||
712 | u32 vdec_phi_incr_6int_26frac; | ||
713 | |||
714 | struct dsp_volume_control vdec_vol_ctrl; | ||
715 | }; | ||
716 | |||
717 | |||
718 | /* SCB for MIX_TO_OSTREAM algorithm family */ | ||
719 | struct dsp_mix2_ostream_scb { | ||
720 | /* First 13 dwords from generic_scb_t */ | ||
721 | struct dsp_basic_dma_req basic_req; /* Optional */ | ||
722 | struct dsp_scatter_gather_ext sg_ext; /* Optional */ | ||
723 | ___DSP_DUAL_16BIT_ALLOC( | ||
724 | next_scb, /* REQUIRED */ | ||
725 | sub_list_ptr /* REQUIRED */ | ||
726 | ) | ||
727 | |||
728 | ___DSP_DUAL_16BIT_ALLOC( | ||
729 | entry_point, /* REQUIRED */ | ||
730 | this_spb /* REQUIRED */ | ||
731 | ) | ||
732 | |||
733 | u32 strm_rs_config; /* REQUIRED */ | ||
734 | u32 strm_buf_ptr; /* REQUIRED */ | ||
735 | |||
736 | |||
737 | /* hi: Number of mixed-down input triplets | ||
738 | computed since start of group | ||
739 | lo: Number of frames remaining to be | ||
740 | processed in the current group of | ||
741 | frames | ||
742 | */ | ||
743 | ___DSP_DUAL_16BIT_ALLOC( | ||
744 | frames_left_in_group, | ||
745 | accum_input_triplets | ||
746 | ) | ||
747 | |||
748 | /* hi: Exponential volume change rate | ||
749 | for mixer on input streams | ||
750 | lo: Number of frames in the group | ||
751 | */ | ||
752 | ___DSP_DUAL_16BIT_ALLOC( | ||
753 | frame_group_length, | ||
754 | exp_vol_change_rate | ||
755 | ) | ||
756 | |||
757 | ___DSP_DUAL_16BIT_ALLOC( | ||
758 | const_FFFF, | ||
759 | const_zero | ||
760 | ) | ||
761 | }; | ||
762 | |||
763 | |||
764 | /* SCB for S16_MIX algorithm */ | ||
765 | struct dsp_mix_only_scb { | ||
766 | /* First 13 dwords from generic_scb_t */ | ||
767 | struct dsp_basic_dma_req basic_req; /* Optional */ | ||
768 | struct dsp_scatter_gather_ext sg_ext; /* Optional */ | ||
769 | ___DSP_DUAL_16BIT_ALLOC( | ||
770 | next_scb, /* REQUIRED */ | ||
771 | sub_list_ptr /* REQUIRED */ | ||
772 | ) | ||
773 | |||
774 | ___DSP_DUAL_16BIT_ALLOC( | ||
775 | entry_point, /* REQUIRED */ | ||
776 | this_spb /* REQUIRED */ | ||
777 | ) | ||
778 | |||
779 | u32 strm_rs_config; /* REQUIRED */ | ||
780 | u32 strm_buf_ptr; /* REQUIRED */ | ||
781 | |||
782 | u32 reserved; | ||
783 | struct dsp_volume_control vol_ctrl; | ||
784 | }; | ||
785 | |||
786 | /* SCB for the async. CODEC input algorithm */ | ||
787 | struct dsp_async_codec_input_scb { | ||
788 | u32 io_free2; | ||
789 | |||
790 | u32 io_current_total; | ||
791 | u32 io_previous_total; | ||
792 | |||
793 | u16 io_count; | ||
794 | u16 io_count_limit; | ||
795 | |||
796 | u16 o_fifo_base_addr; | ||
797 | u16 ost_mo_format; | ||
798 | /* 1 = stereo; 0 = mono | ||
799 | xxx for ASER 1 (not allowed); 118 for ASER2 */ | ||
800 | |||
801 | u32 ostrm_rs_config; | ||
802 | u32 ostrm_buf_ptr; | ||
803 | |||
804 | ___DSP_DUAL_16BIT_ALLOC( | ||
805 | io_sclks_per_lr_clk, | ||
806 | io_io_enable | ||
807 | ) | ||
808 | |||
809 | u32 io_free4; | ||
810 | |||
811 | ___DSP_DUAL_16BIT_ALLOC( | ||
812 | io_next_scb, | ||
813 | io_sub_list_ptr | ||
814 | ) | ||
815 | |||
816 | ___DSP_DUAL_16BIT_ALLOC( | ||
817 | io_entry_point, | ||
818 | io_this_spb | ||
819 | ) | ||
820 | |||
821 | u32 istrm_rs_config; | ||
822 | u32 istrm_buf_ptr; | ||
823 | |||
824 | /* Init. 0000:8042: for ASER1 | ||
825 | 0000:8044: for ASER2 */ | ||
826 | ___DSP_DUAL_16BIT_ALLOC( | ||
827 | io_stat_reg_addr, | ||
828 | iofifo_pointer | ||
829 | ) | ||
830 | |||
831 | /* Init 1 stero:100 ASER1 | ||
832 | Init 0 mono:110 ASER2 | ||
833 | */ | ||
834 | ___DSP_DUAL_16BIT_ALLOC( | ||
835 | ififo_base_addr, | ||
836 | ist_mo_format | ||
837 | ) | ||
838 | |||
839 | u32 i_free; | ||
840 | }; | ||
841 | |||
842 | |||
843 | /* SCB for the SP/DIF CODEC input and output */ | ||
844 | struct dsp_spdifiscb { | ||
845 | ___DSP_DUAL_16BIT_ALLOC( | ||
846 | status_ptr, | ||
847 | status_start_ptr | ||
848 | ) | ||
849 | |||
850 | u32 current_total; | ||
851 | u32 previous_total; | ||
852 | |||
853 | ___DSP_DUAL_16BIT_ALLOC( | ||
854 | count, | ||
855 | count_limit | ||
856 | ) | ||
857 | |||
858 | u32 status_data; | ||
859 | |||
860 | ___DSP_DUAL_16BIT_ALLOC( | ||
861 | status, | ||
862 | free4 | ||
863 | ) | ||
864 | |||
865 | u32 free3; | ||
866 | |||
867 | ___DSP_DUAL_16BIT_ALLOC( | ||
868 | free2, | ||
869 | bit_count | ||
870 | ) | ||
871 | |||
872 | u32 temp_status; | ||
873 | |||
874 | ___DSP_DUAL_16BIT_ALLOC( | ||
875 | next_SCB, | ||
876 | sub_list_ptr | ||
877 | ) | ||
878 | |||
879 | ___DSP_DUAL_16BIT_ALLOC( | ||
880 | entry_point, | ||
881 | this_spb | ||
882 | ) | ||
883 | |||
884 | u32 strm_rs_config; | ||
885 | u32 strm_buf_ptr; | ||
886 | |||
887 | ___DSP_DUAL_16BIT_ALLOC( | ||
888 | stat_reg_addr, | ||
889 | fifo_pointer | ||
890 | ) | ||
891 | |||
892 | ___DSP_DUAL_16BIT_ALLOC( | ||
893 | fifo_base_addr, | ||
894 | st_mo_format | ||
895 | ) | ||
896 | |||
897 | u32 free1; | ||
898 | }; | ||
899 | |||
900 | |||
901 | /* SCB for the SP/DIF CODEC input and output */ | ||
902 | struct dsp_spdifoscb { | ||
903 | |||
904 | u32 free2; | ||
905 | |||
906 | u32 free3[4]; | ||
907 | |||
908 | /* Need to be here for compatibility with AsynchFGTxCode */ | ||
909 | u32 strm_rs_config; | ||
910 | |||
911 | u32 strm_buf_ptr; | ||
912 | |||
913 | ___DSP_DUAL_16BIT_ALLOC( | ||
914 | status, | ||
915 | free5 | ||
916 | ) | ||
917 | |||
918 | u32 free4; | ||
919 | |||
920 | ___DSP_DUAL_16BIT_ALLOC( | ||
921 | next_scb, | ||
922 | sub_list_ptr | ||
923 | ) | ||
924 | |||
925 | ___DSP_DUAL_16BIT_ALLOC( | ||
926 | entry_point, | ||
927 | this_spb | ||
928 | ) | ||
929 | |||
930 | u32 free6[2]; | ||
931 | |||
932 | ___DSP_DUAL_16BIT_ALLOC( | ||
933 | stat_reg_addr, | ||
934 | fifo_pointer | ||
935 | ) | ||
936 | |||
937 | ___DSP_DUAL_16BIT_ALLOC( | ||
938 | fifo_base_addr, | ||
939 | st_mo_format | ||
940 | ) | ||
941 | |||
942 | u32 free1; | ||
943 | }; | ||
944 | |||
945 | |||
946 | struct dsp_asynch_fg_rx_scb { | ||
947 | ___DSP_DUAL_16BIT_ALLOC( | ||
948 | bot_buf_mask, | ||
949 | buf_Mask | ||
950 | ) | ||
951 | |||
952 | ___DSP_DUAL_16BIT_ALLOC( | ||
953 | max, | ||
954 | min | ||
955 | ) | ||
956 | |||
957 | ___DSP_DUAL_16BIT_ALLOC( | ||
958 | old_producer_pointer, | ||
959 | hfg_scb_ptr | ||
960 | ) | ||
961 | |||
962 | ___DSP_DUAL_16BIT_ALLOC( | ||
963 | delta, | ||
964 | adjust_count | ||
965 | ) | ||
966 | |||
967 | u32 unused2[5]; | ||
968 | |||
969 | ___DSP_DUAL_16BIT_ALLOC( | ||
970 | sibling_ptr, | ||
971 | child_ptr | ||
972 | ) | ||
973 | |||
974 | ___DSP_DUAL_16BIT_ALLOC( | ||
975 | code_ptr, | ||
976 | this_ptr | ||
977 | ) | ||
978 | |||
979 | u32 strm_rs_config; | ||
980 | |||
981 | u32 strm_buf_ptr; | ||
982 | |||
983 | u32 unused_phi_incr; | ||
984 | |||
985 | ___DSP_DUAL_16BIT_ALLOC( | ||
986 | right_targ, | ||
987 | left_targ | ||
988 | ) | ||
989 | |||
990 | ___DSP_DUAL_16BIT_ALLOC( | ||
991 | right_vol, | ||
992 | left_vol | ||
993 | ) | ||
994 | }; | ||
995 | |||
996 | |||
997 | struct dsp_asynch_fg_tx_scb { | ||
998 | ___DSP_DUAL_16BIT_ALLOC( | ||
999 | not_buf_mask, | ||
1000 | buf_mask | ||
1001 | ) | ||
1002 | |||
1003 | ___DSP_DUAL_16BIT_ALLOC( | ||
1004 | max, | ||
1005 | min | ||
1006 | ) | ||
1007 | |||
1008 | ___DSP_DUAL_16BIT_ALLOC( | ||
1009 | unused1, | ||
1010 | hfg_scb_ptr | ||
1011 | ) | ||
1012 | |||
1013 | ___DSP_DUAL_16BIT_ALLOC( | ||
1014 | delta, | ||
1015 | adjust_count | ||
1016 | ) | ||
1017 | |||
1018 | u32 accum_phi; | ||
1019 | |||
1020 | ___DSP_DUAL_16BIT_ALLOC( | ||
1021 | unused2, | ||
1022 | const_one_third | ||
1023 | ) | ||
1024 | |||
1025 | u32 unused3[3]; | ||
1026 | |||
1027 | ___DSP_DUAL_16BIT_ALLOC( | ||
1028 | sibling_ptr, | ||
1029 | child_ptr | ||
1030 | ) | ||
1031 | |||
1032 | ___DSP_DUAL_16BIT_ALLOC( | ||
1033 | codePtr, | ||
1034 | this_ptr | ||
1035 | ) | ||
1036 | |||
1037 | u32 strm_rs_config; | ||
1038 | |||
1039 | u32 strm_buf_ptr; | ||
1040 | |||
1041 | u32 phi_incr; | ||
1042 | |||
1043 | ___DSP_DUAL_16BIT_ALLOC( | ||
1044 | unused_right_targ, | ||
1045 | unused_left_targ | ||
1046 | ) | ||
1047 | |||
1048 | ___DSP_DUAL_16BIT_ALLOC( | ||
1049 | unused_right_vol, | ||
1050 | unused_left_vol | ||
1051 | ) | ||
1052 | }; | ||
1053 | |||
1054 | |||
1055 | struct dsp_output_snoop_scb { | ||
1056 | /* First 13 dwords from generic_scb_t */ | ||
1057 | struct dsp_basic_dma_req basic_req; /* Optional */ | ||
1058 | struct dsp_scatter_gather_ext sg_ext; /* Optional */ | ||
1059 | ___DSP_DUAL_16BIT_ALLOC( | ||
1060 | next_scb, /* REQUIRED */ | ||
1061 | sub_list_ptr /* REQUIRED */ | ||
1062 | ) | ||
1063 | |||
1064 | ___DSP_DUAL_16BIT_ALLOC( | ||
1065 | entry_point, /* REQUIRED */ | ||
1066 | this_spb /* REQUIRED */ | ||
1067 | ) | ||
1068 | |||
1069 | u32 strm_rs_config; /* REQUIRED */ | ||
1070 | u32 strm_buf_ptr; /* REQUIRED */ | ||
1071 | |||
1072 | ___DSP_DUAL_16BIT_ALLOC( | ||
1073 | init_snoop_input_link, | ||
1074 | snoop_child_input_scb | ||
1075 | ) | ||
1076 | |||
1077 | u32 snoop_input_buf_ptr; | ||
1078 | |||
1079 | ___DSP_DUAL_16BIT_ALLOC( | ||
1080 | reserved, | ||
1081 | input_scb | ||
1082 | ) | ||
1083 | }; | ||
1084 | |||
1085 | struct dsp_spio_write_scb { | ||
1086 | ___DSP_DUAL_16BIT_ALLOC( | ||
1087 | address1, | ||
1088 | address2 | ||
1089 | ) | ||
1090 | |||
1091 | u32 data1; | ||
1092 | |||
1093 | u32 data2; | ||
1094 | |||
1095 | ___DSP_DUAL_16BIT_ALLOC( | ||
1096 | address3, | ||
1097 | address4 | ||
1098 | ) | ||
1099 | |||
1100 | u32 data3; | ||
1101 | |||
1102 | u32 data4; | ||
1103 | |||
1104 | ___DSP_DUAL_16BIT_ALLOC( | ||
1105 | unused1, | ||
1106 | data_ptr | ||
1107 | ) | ||
1108 | |||
1109 | u32 unused2[2]; | ||
1110 | |||
1111 | ___DSP_DUAL_16BIT_ALLOC( | ||
1112 | sibling_ptr, | ||
1113 | child_ptr | ||
1114 | ) | ||
1115 | |||
1116 | ___DSP_DUAL_16BIT_ALLOC( | ||
1117 | entry_point, | ||
1118 | this_ptr | ||
1119 | ) | ||
1120 | |||
1121 | u32 unused3[5]; | ||
1122 | }; | ||
1123 | |||
1124 | struct dsp_magic_snoop_task { | ||
1125 | u32 i0; | ||
1126 | u32 i1; | ||
1127 | |||
1128 | u32 strm_buf_ptr1; | ||
1129 | |||
1130 | u16 i2; | ||
1131 | u16 snoop_scb; | ||
1132 | |||
1133 | u32 i3; | ||
1134 | u32 i4; | ||
1135 | u32 i5; | ||
1136 | u32 i6; | ||
1137 | |||
1138 | u32 i7; | ||
1139 | |||
1140 | ___DSP_DUAL_16BIT_ALLOC( | ||
1141 | next_scb, | ||
1142 | sub_list_ptr | ||
1143 | ) | ||
1144 | |||
1145 | ___DSP_DUAL_16BIT_ALLOC( | ||
1146 | entry_point, | ||
1147 | this_ptr | ||
1148 | ) | ||
1149 | |||
1150 | u32 strm_buf_config; | ||
1151 | u32 strm_buf_ptr2; | ||
1152 | |||
1153 | u32 i8; | ||
1154 | |||
1155 | struct dsp_volume_control vdec_vol_ctrl; | ||
1156 | }; | ||
1157 | |||
1158 | |||
1159 | struct dsp_filter_scb { | ||
1160 | ___DSP_DUAL_16BIT_ALLOC( | ||
1161 | a0_right, /* 0x00 */ | ||
1162 | a0_left | ||
1163 | ) | ||
1164 | ___DSP_DUAL_16BIT_ALLOC( | ||
1165 | a1_right, /* 0x01 */ | ||
1166 | a1_left | ||
1167 | ) | ||
1168 | ___DSP_DUAL_16BIT_ALLOC( | ||
1169 | a2_right, /* 0x02 */ | ||
1170 | a2_left | ||
1171 | ) | ||
1172 | ___DSP_DUAL_16BIT_ALLOC( | ||
1173 | output_buf_ptr, /* 0x03 */ | ||
1174 | init | ||
1175 | ) | ||
1176 | |||
1177 | ___DSP_DUAL_16BIT_ALLOC( | ||
1178 | filter_unused3, /* 0x04 */ | ||
1179 | filter_unused2 | ||
1180 | ) | ||
1181 | |||
1182 | u32 prev_sample_output1; /* 0x05 */ | ||
1183 | u32 prev_sample_output2; /* 0x06 */ | ||
1184 | u32 prev_sample_input1; /* 0x07 */ | ||
1185 | u32 prev_sample_input2; /* 0x08 */ | ||
1186 | |||
1187 | ___DSP_DUAL_16BIT_ALLOC( | ||
1188 | next_scb_ptr, /* 0x09 */ | ||
1189 | sub_list_ptr | ||
1190 | ) | ||
1191 | |||
1192 | ___DSP_DUAL_16BIT_ALLOC( | ||
1193 | entry_point, /* 0x0A */ | ||
1194 | spb_ptr | ||
1195 | ) | ||
1196 | |||
1197 | u32 strm_rs_config; /* 0x0B */ | ||
1198 | u32 strm_buf_ptr; /* 0x0C */ | ||
1199 | |||
1200 | ___DSP_DUAL_16BIT_ALLOC( | ||
1201 | b0_right, /* 0x0D */ | ||
1202 | b0_left | ||
1203 | ) | ||
1204 | ___DSP_DUAL_16BIT_ALLOC( | ||
1205 | b1_right, /* 0x0E */ | ||
1206 | b1_left | ||
1207 | ) | ||
1208 | ___DSP_DUAL_16BIT_ALLOC( | ||
1209 | b2_right, /* 0x0F */ | ||
1210 | b2_left | ||
1211 | ) | ||
1212 | }; | ||
1213 | #endif /* __DSP_SCB_TYPES_H__ */ | ||
diff --git a/include/sound/cs46xx_dsp_spos.h b/include/sound/cs46xx_dsp_spos.h deleted file mode 100644 index 8008c59288a6..000000000000 --- a/include/sound/cs46xx_dsp_spos.h +++ /dev/null | |||
@@ -1,234 +0,0 @@ | |||
1 | /* | ||
2 | * The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards | ||
3 | * Copyright (c) by Jaroslav Kysela <perex@perex.cz> | ||
4 | * | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | * | ||
20 | */ | ||
21 | |||
22 | #ifndef __CS46XX_DSP_SPOS_H__ | ||
23 | #define __CS46XX_DSP_SPOS_H__ | ||
24 | |||
25 | #include "cs46xx_dsp_scb_types.h" | ||
26 | #include "cs46xx_dsp_task_types.h" | ||
27 | |||
28 | #define SYMBOL_CONSTANT 0x0 | ||
29 | #define SYMBOL_SAMPLE 0x1 | ||
30 | #define SYMBOL_PARAMETER 0x2 | ||
31 | #define SYMBOL_CODE 0x3 | ||
32 | |||
33 | #define SEGTYPE_SP_PROGRAM 0x00000001 | ||
34 | #define SEGTYPE_SP_PARAMETER 0x00000002 | ||
35 | #define SEGTYPE_SP_SAMPLE 0x00000003 | ||
36 | #define SEGTYPE_SP_COEFFICIENT 0x00000004 | ||
37 | |||
38 | #define DSP_SPOS_UU 0x0deadul /* unused */ | ||
39 | #define DSP_SPOS_DC 0x0badul /* don't care */ | ||
40 | #define DSP_SPOS_DC_DC 0x0bad0badul /* don't care */ | ||
41 | #define DSP_SPOS_UUUU 0xdeadc0edul /* unused */ | ||
42 | #define DSP_SPOS_UUHI 0xdeadul | ||
43 | #define DSP_SPOS_UULO 0xc0edul | ||
44 | #define DSP_SPOS_DCDC 0x0badf1d0ul /* don't care */ | ||
45 | #define DSP_SPOS_DCDCHI 0x0badul | ||
46 | #define DSP_SPOS_DCDCLO 0xf1d0ul | ||
47 | |||
48 | #define DSP_MAX_TASK_NAME 60 | ||
49 | #define DSP_MAX_SYMBOL_NAME 100 | ||
50 | #define DSP_MAX_SCB_NAME 60 | ||
51 | #define DSP_MAX_SCB_DESC 200 | ||
52 | #define DSP_MAX_TASK_DESC 50 | ||
53 | |||
54 | #define DSP_MAX_PCM_CHANNELS 32 | ||
55 | #define DSP_MAX_SRC_NR 14 | ||
56 | |||
57 | #define DSP_PCM_MAIN_CHANNEL 1 | ||
58 | #define DSP_PCM_REAR_CHANNEL 2 | ||
59 | #define DSP_PCM_CENTER_LFE_CHANNEL 3 | ||
60 | #define DSP_PCM_S71_CHANNEL 4 /* surround 7.1 */ | ||
61 | #define DSP_IEC958_CHANNEL 5 | ||
62 | |||
63 | #define DSP_SPDIF_STATUS_OUTPUT_ENABLED 1 | ||
64 | #define DSP_SPDIF_STATUS_PLAYBACK_OPEN 2 | ||
65 | #define DSP_SPDIF_STATUS_HW_ENABLED 4 | ||
66 | #define DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED 8 | ||
67 | |||
68 | struct dsp_symbol_entry { | ||
69 | u32 address; | ||
70 | char symbol_name[DSP_MAX_SYMBOL_NAME]; | ||
71 | int symbol_type; | ||
72 | |||
73 | /* initialized by driver */ | ||
74 | struct dsp_module_desc * module; | ||
75 | int deleted; | ||
76 | }; | ||
77 | |||
78 | struct dsp_symbol_desc { | ||
79 | int nsymbols; | ||
80 | |||
81 | struct dsp_symbol_entry *symbols; | ||
82 | |||
83 | /* initialized by driver */ | ||
84 | int highest_frag_index; | ||
85 | }; | ||
86 | |||
87 | struct dsp_segment_desc { | ||
88 | int segment_type; | ||
89 | u32 offset; | ||
90 | u32 size; | ||
91 | u32 * data; | ||
92 | }; | ||
93 | |||
94 | struct dsp_module_desc { | ||
95 | char * module_name; | ||
96 | struct dsp_symbol_desc symbol_table; | ||
97 | int nsegments; | ||
98 | struct dsp_segment_desc * segments; | ||
99 | |||
100 | /* initialized by driver */ | ||
101 | u32 overlay_begin_address; | ||
102 | u32 load_address; | ||
103 | int nfixups; | ||
104 | }; | ||
105 | |||
106 | struct dsp_scb_descriptor { | ||
107 | char scb_name[DSP_MAX_SCB_NAME]; | ||
108 | u32 address; | ||
109 | int index; | ||
110 | u32 *data; | ||
111 | |||
112 | struct dsp_scb_descriptor * sub_list_ptr; | ||
113 | struct dsp_scb_descriptor * next_scb_ptr; | ||
114 | struct dsp_scb_descriptor * parent_scb_ptr; | ||
115 | |||
116 | struct dsp_symbol_entry * task_entry; | ||
117 | struct dsp_symbol_entry * scb_symbol; | ||
118 | |||
119 | struct snd_info_entry *proc_info; | ||
120 | int ref_count; | ||
121 | |||
122 | u16 volume[2]; | ||
123 | unsigned int deleted :1; | ||
124 | unsigned int updated :1; | ||
125 | unsigned int volume_set :1; | ||
126 | }; | ||
127 | |||
128 | struct dsp_task_descriptor { | ||
129 | char task_name[DSP_MAX_TASK_NAME]; | ||
130 | int size; | ||
131 | u32 address; | ||
132 | int index; | ||
133 | u32 *data; | ||
134 | }; | ||
135 | |||
136 | struct dsp_pcm_channel_descriptor { | ||
137 | int active; | ||
138 | int src_slot; | ||
139 | int pcm_slot; | ||
140 | u32 sample_rate; | ||
141 | u32 unlinked; | ||
142 | struct dsp_scb_descriptor * pcm_reader_scb; | ||
143 | struct dsp_scb_descriptor * src_scb; | ||
144 | struct dsp_scb_descriptor * mixer_scb; | ||
145 | |||
146 | void * private_data; | ||
147 | }; | ||
148 | |||
149 | struct dsp_spos_instance { | ||
150 | struct dsp_symbol_desc symbol_table; /* currently available loaded symbols in SP */ | ||
151 | |||
152 | int nmodules; | ||
153 | struct dsp_module_desc * modules; /* modules loaded into SP */ | ||
154 | |||
155 | struct dsp_segment_desc code; | ||
156 | |||
157 | /* Main PCM playback mixer */ | ||
158 | struct dsp_scb_descriptor * master_mix_scb; | ||
159 | u16 dac_volume_right; | ||
160 | u16 dac_volume_left; | ||
161 | |||
162 | /* Rear/surround PCM playback mixer */ | ||
163 | struct dsp_scb_descriptor * rear_mix_scb; | ||
164 | |||
165 | /* Center/LFE mixer */ | ||
166 | struct dsp_scb_descriptor * center_lfe_mix_scb; | ||
167 | |||
168 | int npcm_channels; | ||
169 | int nsrc_scb; | ||
170 | struct dsp_pcm_channel_descriptor pcm_channels[DSP_MAX_PCM_CHANNELS]; | ||
171 | int src_scb_slots[DSP_MAX_SRC_NR]; | ||
172 | |||
173 | /* cache this symbols */ | ||
174 | struct dsp_symbol_entry * null_algorithm; /* used by PCMreaderSCB's */ | ||
175 | struct dsp_symbol_entry * s16_up; /* used by SRCtaskSCB's */ | ||
176 | |||
177 | /* proc fs */ | ||
178 | struct snd_card *snd_card; | ||
179 | struct snd_info_entry * proc_dsp_dir; | ||
180 | struct snd_info_entry * proc_sym_info_entry; | ||
181 | struct snd_info_entry * proc_modules_info_entry; | ||
182 | struct snd_info_entry * proc_parameter_dump_info_entry; | ||
183 | struct snd_info_entry * proc_sample_dump_info_entry; | ||
184 | |||
185 | /* SCB's descriptors */ | ||
186 | int nscb; | ||
187 | int scb_highest_frag_index; | ||
188 | struct dsp_scb_descriptor scbs[DSP_MAX_SCB_DESC]; | ||
189 | struct snd_info_entry * proc_scb_info_entry; | ||
190 | struct dsp_scb_descriptor * the_null_scb; | ||
191 | |||
192 | /* Task's descriptors */ | ||
193 | int ntask; | ||
194 | struct dsp_task_descriptor tasks[DSP_MAX_TASK_DESC]; | ||
195 | struct snd_info_entry * proc_task_info_entry; | ||
196 | |||
197 | /* SPDIF status */ | ||
198 | int spdif_status_out; | ||
199 | int spdif_status_in; | ||
200 | u16 spdif_input_volume_right; | ||
201 | u16 spdif_input_volume_left; | ||
202 | /* spdif channel status, | ||
203 | left right and user validity bits */ | ||
204 | unsigned int spdif_csuv_default; | ||
205 | unsigned int spdif_csuv_stream; | ||
206 | |||
207 | /* SPDIF input sample rate converter */ | ||
208 | struct dsp_scb_descriptor * spdif_in_src; | ||
209 | /* SPDIF input asynch. receiver */ | ||
210 | struct dsp_scb_descriptor * asynch_rx_scb; | ||
211 | |||
212 | /* Capture record mixer SCB */ | ||
213 | struct dsp_scb_descriptor * record_mixer_scb; | ||
214 | |||
215 | /* CODEC input SCB */ | ||
216 | struct dsp_scb_descriptor * codec_in_scb; | ||
217 | |||
218 | /* reference snooper */ | ||
219 | struct dsp_scb_descriptor * ref_snoop_scb; | ||
220 | |||
221 | /* SPDIF output PCM reference */ | ||
222 | struct dsp_scb_descriptor * spdif_pcm_input_scb; | ||
223 | |||
224 | /* asynch TX task */ | ||
225 | struct dsp_scb_descriptor * asynch_tx_scb; | ||
226 | |||
227 | /* record sources */ | ||
228 | struct dsp_scb_descriptor * pcm_input; | ||
229 | struct dsp_scb_descriptor * adc_input; | ||
230 | |||
231 | int spdif_in_sample_rate; | ||
232 | }; | ||
233 | |||
234 | #endif /* __DSP_SPOS_H__ */ | ||
diff --git a/include/sound/cs46xx_dsp_task_types.h b/include/sound/cs46xx_dsp_task_types.h deleted file mode 100644 index 5cf920bfda27..000000000000 --- a/include/sound/cs46xx_dsp_task_types.h +++ /dev/null | |||
@@ -1,252 +0,0 @@ | |||
1 | /* | ||
2 | * The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards | ||
3 | * Copyright (c) by Jaroslav Kysela <perex@perex.cz> | ||
4 | * | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | * | ||
20 | * | ||
21 | * NOTE: comments are copy/paste from cwcemb80.lst | ||
22 | * provided by Tom Woller at Cirrus (my only | ||
23 | * documentation about the SP OS running inside | ||
24 | * the DSP) | ||
25 | */ | ||
26 | |||
27 | #ifndef __CS46XX_DSP_TASK_TYPES_H__ | ||
28 | #define __CS46XX_DSP_TASK_TYPES_H__ | ||
29 | |||
30 | #include "cs46xx_dsp_scb_types.h" | ||
31 | |||
32 | /********************************************************************************************* | ||
33 | Example hierarchy of stream control blocks in the SP | ||
34 | |||
35 | hfgTree | ||
36 | Ptr____Call (c) | ||
37 | \ | ||
38 | -------+------ ------------- ------------- ------------- ----- | ||
39 | | SBlaster IF |______\| Foreground |___\| Middlegr'nd |___\| Background |___\| Nul | | ||
40 | | |Goto /| tree header |g /| tree header |g /| tree header |g /| SCB |r | ||
41 | -------------- (g) ------------- ------------- ------------- ----- | ||
42 | |c |c |c |c | ||
43 | | | | | | ||
44 | \/ ------------- ------------- ------------- | ||
45 | | Foreground |_\ | Middlegr'nd |_\ | Background |_\ | ||
46 | | tree |g/ | tree |g/ | tree |g/ | ||
47 | ------------- ------------- ------------- | ||
48 | |c |c |c | ||
49 | | | | | ||
50 | \/ \/ \/ | ||
51 | |||
52 | *********************************************************************************************/ | ||
53 | |||
54 | #define HFG_FIRST_EXECUTE_MODE 0x0001 | ||
55 | #define HFG_FIRST_EXECUTE_MODE_BIT 0 | ||
56 | #define HFG_CONTEXT_SWITCH_MODE 0x0002 | ||
57 | #define HFG_CONTEXT_SWITCH_MODE_BIT 1 | ||
58 | |||
59 | #define MAX_FG_STACK_SIZE 32 /* THESE NEED TO BE COMPUTED PROPERLY */ | ||
60 | #define MAX_MG_STACK_SIZE 16 | ||
61 | #define MAX_BG_STACK_SIZE 9 | ||
62 | #define MAX_HFG_STACK_SIZE 4 | ||
63 | |||
64 | #define SLEEP_ACTIVE_INCREMENT 0 /* Enable task tree thread to go to sleep | ||
65 | This should only ever be used on the Background thread */ | ||
66 | #define STANDARD_ACTIVE_INCREMENT 1 /* Task tree thread normal operation */ | ||
67 | #define SUSPEND_ACTIVE_INCREMENT 2 /* Cause execution to suspend in the task tree thread | ||
68 | This should only ever be used on the Background thread */ | ||
69 | |||
70 | #define HOSTFLAGS_DISABLE_BG_SLEEP 0 /* Host-controlled flag that determines whether we go to sleep | ||
71 | at the end of BG */ | ||
72 | |||
73 | /* Minimal context save area for Hyper Forground */ | ||
74 | struct dsp_hf_save_area { | ||
75 | u32 r10_save; | ||
76 | u32 r54_save; | ||
77 | u32 r98_save; | ||
78 | |||
79 | ___DSP_DUAL_16BIT_ALLOC( | ||
80 | status_save, | ||
81 | ind_save | ||
82 | ) | ||
83 | |||
84 | ___DSP_DUAL_16BIT_ALLOC( | ||
85 | rci1_save, | ||
86 | rci0_save | ||
87 | ) | ||
88 | |||
89 | u32 r32_save; | ||
90 | u32 r76_save; | ||
91 | u32 rsd2_save; | ||
92 | |||
93 | ___DSP_DUAL_16BIT_ALLOC( | ||
94 | rsi2_save, /* See TaskTreeParameterBlock for | ||
95 | remainder of registers */ | ||
96 | rsa2Save | ||
97 | ) | ||
98 | /* saved as part of HFG context */ | ||
99 | }; | ||
100 | |||
101 | |||
102 | /* Task link data structure */ | ||
103 | struct dsp_tree_link { | ||
104 | ___DSP_DUAL_16BIT_ALLOC( | ||
105 | /* Pointer to sibling task control block */ | ||
106 | next_scb, | ||
107 | /* Pointer to child task control block */ | ||
108 | sub_ptr | ||
109 | ) | ||
110 | |||
111 | ___DSP_DUAL_16BIT_ALLOC( | ||
112 | /* Pointer to code entry point */ | ||
113 | entry_point, | ||
114 | /* Pointer to local data */ | ||
115 | this_spb | ||
116 | ) | ||
117 | }; | ||
118 | |||
119 | |||
120 | struct dsp_task_tree_data { | ||
121 | ___DSP_DUAL_16BIT_ALLOC( | ||
122 | /* Initial tock count; controls task tree execution rate */ | ||
123 | tock_count_limit, | ||
124 | /* Tock down counter */ | ||
125 | tock_count | ||
126 | ) | ||
127 | |||
128 | /* Add to ActiveCount when TockCountLimit reached: | ||
129 | Subtract on task tree termination */ | ||
130 | ___DSP_DUAL_16BIT_ALLOC( | ||
131 | active_tncrement, | ||
132 | /* Number of pending activations for task tree */ | ||
133 | active_count | ||
134 | ) | ||
135 | |||
136 | ___DSP_DUAL_16BIT_ALLOC( | ||
137 | /* BitNumber to enable modification of correct bit in ActiveTaskFlags */ | ||
138 | active_bit, | ||
139 | /* Pointer to OS location for indicating current activity on task level */ | ||
140 | active_task_flags_ptr | ||
141 | ) | ||
142 | |||
143 | /* Data structure for controlling movement of memory blocks:- | ||
144 | currently unused */ | ||
145 | ___DSP_DUAL_16BIT_ALLOC( | ||
146 | mem_upd_ptr, | ||
147 | /* Data structure for controlling synchronous link update */ | ||
148 | link_upd_ptr | ||
149 | ) | ||
150 | |||
151 | ___DSP_DUAL_16BIT_ALLOC( | ||
152 | /* Save area for remainder of full context. */ | ||
153 | save_area, | ||
154 | /* Address of start of local stack for data storage */ | ||
155 | data_stack_base_ptr | ||
156 | ) | ||
157 | |||
158 | }; | ||
159 | |||
160 | |||
161 | struct dsp_interval_timer_data | ||
162 | { | ||
163 | /* These data items have the same relative locations to those */ | ||
164 | ___DSP_DUAL_16BIT_ALLOC( | ||
165 | interval_timer_period, | ||
166 | itd_unused | ||
167 | ) | ||
168 | |||
169 | /* used for this data in the SPOS control block for SPOS 1.0 */ | ||
170 | ___DSP_DUAL_16BIT_ALLOC( | ||
171 | num_FG_ticks_this_interval, | ||
172 | num_intervals | ||
173 | ) | ||
174 | }; | ||
175 | |||
176 | |||
177 | /* This structure contains extra storage for the task tree | ||
178 | Currently, this additional data is related only to a full context save */ | ||
179 | struct dsp_task_tree_context_block { | ||
180 | /* Up to 10 values are saved onto the stack. 8 for the task tree, 1 for | ||
181 | The access to the context switch (call or interrupt), and 1 spare that | ||
182 | users should never use. This last may be required by the system */ | ||
183 | ___DSP_DUAL_16BIT_ALLOC( | ||
184 | stack1, | ||
185 | stack0 | ||
186 | ) | ||
187 | ___DSP_DUAL_16BIT_ALLOC( | ||
188 | stack3, | ||
189 | stack2 | ||
190 | ) | ||
191 | ___DSP_DUAL_16BIT_ALLOC( | ||
192 | stack5, | ||
193 | stack4 | ||
194 | ) | ||
195 | ___DSP_DUAL_16BIT_ALLOC( | ||
196 | stack7, | ||
197 | stack6 | ||
198 | ) | ||
199 | ___DSP_DUAL_16BIT_ALLOC( | ||
200 | stack9, | ||
201 | stack8 | ||
202 | ) | ||
203 | |||
204 | u32 saverfe; | ||
205 | |||
206 | /* Value may be overwriten by stack save algorithm. | ||
207 | Retain the size of the stack data saved here if used */ | ||
208 | ___DSP_DUAL_16BIT_ALLOC( | ||
209 | reserved1, | ||
210 | stack_size | ||
211 | ) | ||
212 | u32 saverba; /* (HFG) */ | ||
213 | u32 saverdc; | ||
214 | u32 savers_config_23; /* (HFG) */ | ||
215 | u32 savers_DMA23; /* (HFG) */ | ||
216 | u32 saversa0; | ||
217 | u32 saversi0; | ||
218 | u32 saversa1; | ||
219 | u32 saversi1; | ||
220 | u32 saversa3; | ||
221 | u32 saversd0; | ||
222 | u32 saversd1; | ||
223 | u32 saversd3; | ||
224 | u32 savers_config01; | ||
225 | u32 savers_DMA01; | ||
226 | u32 saveacc0hl; | ||
227 | u32 saveacc1hl; | ||
228 | u32 saveacc0xacc1x; | ||
229 | u32 saveacc2hl; | ||
230 | u32 saveacc3hl; | ||
231 | u32 saveacc2xacc3x; | ||
232 | u32 saveaux0hl; | ||
233 | u32 saveaux1hl; | ||
234 | u32 saveaux0xaux1x; | ||
235 | u32 saveaux2hl; | ||
236 | u32 saveaux3hl; | ||
237 | u32 saveaux2xaux3x; | ||
238 | u32 savershouthl; | ||
239 | u32 savershoutxmacmode; | ||
240 | }; | ||
241 | |||
242 | |||
243 | struct dsp_task_tree_control_block { | ||
244 | struct dsp_hf_save_area context; | ||
245 | struct dsp_tree_link links; | ||
246 | struct dsp_task_tree_data data; | ||
247 | struct dsp_task_tree_context_block context_blk; | ||
248 | struct dsp_interval_timer_data int_timer; | ||
249 | }; | ||
250 | |||
251 | |||
252 | #endif /* __DSP_TASK_TYPES_H__ */ | ||
diff --git a/include/sound/trident.h b/include/sound/trident.h deleted file mode 100644 index 9f191a0a1e19..000000000000 --- a/include/sound/trident.h +++ /dev/null | |||
@@ -1,445 +0,0 @@ | |||
1 | #ifndef __SOUND_TRIDENT_H | ||
2 | #define __SOUND_TRIDENT_H | ||
3 | |||
4 | /* | ||
5 | * audio@tridentmicro.com | ||
6 | * Fri Feb 19 15:55:28 MST 1999 | ||
7 | * Definitions for Trident 4DWave DX/NX chips | ||
8 | * | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * This program is distributed in the hope that it will be useful, | ||
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
18 | * GNU General Public License for more details. | ||
19 | * | ||
20 | * You should have received a copy of the GNU General Public License | ||
21 | * along with this program; if not, write to the Free Software | ||
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
23 | * | ||
24 | */ | ||
25 | |||
26 | #include "pcm.h" | ||
27 | #include "mpu401.h" | ||
28 | #include "ac97_codec.h" | ||
29 | #include "util_mem.h" | ||
30 | |||
31 | #define TRIDENT_DEVICE_ID_DX ((PCI_VENDOR_ID_TRIDENT<<16)|PCI_DEVICE_ID_TRIDENT_4DWAVE_DX) | ||
32 | #define TRIDENT_DEVICE_ID_NX ((PCI_VENDOR_ID_TRIDENT<<16)|PCI_DEVICE_ID_TRIDENT_4DWAVE_NX) | ||
33 | #define TRIDENT_DEVICE_ID_SI7018 ((PCI_VENDOR_ID_SI<<16)|PCI_DEVICE_ID_SI_7018) | ||
34 | |||
35 | #define SNDRV_TRIDENT_VOICE_TYPE_PCM 0 | ||
36 | #define SNDRV_TRIDENT_VOICE_TYPE_SYNTH 1 | ||
37 | #define SNDRV_TRIDENT_VOICE_TYPE_MIDI 2 | ||
38 | |||
39 | #define SNDRV_TRIDENT_VFLG_RUNNING (1<<0) | ||
40 | |||
41 | /* TLB code constants */ | ||
42 | #define SNDRV_TRIDENT_PAGE_SIZE 4096 | ||
43 | #define SNDRV_TRIDENT_PAGE_SHIFT 12 | ||
44 | #define SNDRV_TRIDENT_PAGE_MASK ((1<<SNDRV_TRIDENT_PAGE_SHIFT)-1) | ||
45 | #define SNDRV_TRIDENT_MAX_PAGES 4096 | ||
46 | |||
47 | /* | ||
48 | * Direct registers | ||
49 | */ | ||
50 | |||
51 | #define TRID_REG(trident, x) ((trident)->port + (x)) | ||
52 | |||
53 | #define ID_4DWAVE_DX 0x2000 | ||
54 | #define ID_4DWAVE_NX 0x2001 | ||
55 | |||
56 | /* Bank definitions */ | ||
57 | |||
58 | #define T4D_BANK_A 0 | ||
59 | #define T4D_BANK_B 1 | ||
60 | #define T4D_NUM_BANKS 2 | ||
61 | |||
62 | /* Register definitions */ | ||
63 | |||
64 | /* Global registers */ | ||
65 | |||
66 | enum global_control_bits { | ||
67 | CHANNEL_IDX = 0x0000003f, | ||
68 | OVERRUN_IE = 0x00000400, /* interrupt enable: capture overrun */ | ||
69 | UNDERRUN_IE = 0x00000800, /* interrupt enable: playback underrun */ | ||
70 | ENDLP_IE = 0x00001000, /* interrupt enable: end of buffer */ | ||
71 | MIDLP_IE = 0x00002000, /* interrupt enable: middle buffer */ | ||
72 | ETOG_IE = 0x00004000, /* interrupt enable: envelope toggling */ | ||
73 | EDROP_IE = 0x00008000, /* interrupt enable: envelope drop */ | ||
74 | BANK_B_EN = 0x00010000, /* SiS: enable bank B (64 channels) */ | ||
75 | PCMIN_B_MIX = 0x00020000, /* SiS: PCM IN B mixing enable */ | ||
76 | I2S_OUT_ASSIGN = 0x00040000, /* SiS: I2S Out contains surround PCM */ | ||
77 | SPDIF_OUT_ASSIGN= 0x00080000, /* SiS: 0=S/PDIF L/R | 1=PCM Out FIFO */ | ||
78 | MAIN_OUT_ASSIGN = 0x00100000, /* SiS: 0=PCM Out FIFO | 1=MMC Out buffer */ | ||
79 | }; | ||
80 | |||
81 | enum miscint_bits { | ||
82 | PB_UNDERRUN_IRQ = 0x00000001, REC_OVERRUN_IRQ = 0x00000002, | ||
83 | SB_IRQ = 0x00000004, MPU401_IRQ = 0x00000008, | ||
84 | OPL3_IRQ = 0x00000010, ADDRESS_IRQ = 0x00000020, | ||
85 | ENVELOPE_IRQ = 0x00000040, PB_UNDERRUN = 0x00000100, | ||
86 | REC_OVERRUN = 0x00000200, MIXER_UNDERFLOW = 0x00000400, | ||
87 | MIXER_OVERFLOW = 0x00000800, NX_SB_IRQ_DISABLE = 0x00001000, | ||
88 | ST_TARGET_REACHED = 0x00008000, | ||
89 | PB_24K_MODE = 0x00010000, ST_IRQ_EN = 0x00800000, | ||
90 | ACGPIO_IRQ = 0x01000000 | ||
91 | }; | ||
92 | |||
93 | /* T2 legacy dma control registers. */ | ||
94 | #define LEGACY_DMAR0 0x00 // ADR0 | ||
95 | #define LEGACY_DMAR4 0x04 // CNT0 | ||
96 | #define LEGACY_DMAR6 0x06 // CNT0 - High bits | ||
97 | #define LEGACY_DMAR11 0x0b // MOD | ||
98 | #define LEGACY_DMAR15 0x0f // MMR | ||
99 | |||
100 | #define T4D_START_A 0x80 | ||
101 | #define T4D_STOP_A 0x84 | ||
102 | #define T4D_DLY_A 0x88 | ||
103 | #define T4D_SIGN_CSO_A 0x8c | ||
104 | #define T4D_CSPF_A 0x90 | ||
105 | #define T4D_CSPF_B 0xbc | ||
106 | #define T4D_CEBC_A 0x94 | ||
107 | #define T4D_AINT_A 0x98 | ||
108 | #define T4D_AINTEN_A 0x9c | ||
109 | #define T4D_LFO_GC_CIR 0xa0 | ||
110 | #define T4D_MUSICVOL_WAVEVOL 0xa8 | ||
111 | #define T4D_SBDELTA_DELTA_R 0xac | ||
112 | #define T4D_MISCINT 0xb0 | ||
113 | #define T4D_START_B 0xb4 | ||
114 | #define T4D_STOP_B 0xb8 | ||
115 | #define T4D_SBBL_SBCL 0xc0 | ||
116 | #define T4D_SBCTRL_SBE2R_SBDD 0xc4 | ||
117 | #define T4D_STIMER 0xc8 | ||
118 | #define T4D_AINT_B 0xd8 | ||
119 | #define T4D_AINTEN_B 0xdc | ||
120 | #define T4D_RCI 0x70 | ||
121 | |||
122 | /* MPU-401 UART */ | ||
123 | #define T4D_MPU401_BASE 0x20 | ||
124 | #define T4D_MPUR0 0x20 | ||
125 | #define T4D_MPUR1 0x21 | ||
126 | #define T4D_MPUR2 0x22 | ||
127 | #define T4D_MPUR3 0x23 | ||
128 | |||
129 | /* S/PDIF Registers */ | ||
130 | #define NX_SPCTRL_SPCSO 0x24 | ||
131 | #define NX_SPLBA 0x28 | ||
132 | #define NX_SPESO 0x2c | ||
133 | #define NX_SPCSTATUS 0x64 | ||
134 | |||
135 | /* Joystick */ | ||
136 | #define GAMEPORT_GCR 0x30 | ||
137 | #define GAMEPORT_MODE_ADC 0x80 | ||
138 | #define GAMEPORT_LEGACY 0x31 | ||
139 | #define GAMEPORT_AXES 0x34 | ||
140 | |||
141 | /* NX Specific Registers */ | ||
142 | #define NX_TLBC 0x6c | ||
143 | |||
144 | /* Channel Registers */ | ||
145 | |||
146 | #define CH_START 0xe0 | ||
147 | |||
148 | #define CH_DX_CSO_ALPHA_FMS 0xe0 | ||
149 | #define CH_DX_ESO_DELTA 0xe8 | ||
150 | #define CH_DX_FMC_RVOL_CVOL 0xec | ||
151 | |||
152 | #define CH_NX_DELTA_CSO 0xe0 | ||
153 | #define CH_NX_DELTA_ESO 0xe8 | ||
154 | #define CH_NX_ALPHA_FMS_FMC_RVOL_CVOL 0xec | ||
155 | |||
156 | #define CH_LBA 0xe4 | ||
157 | #define CH_GVSEL_PAN_VOL_CTRL_EC 0xf0 | ||
158 | #define CH_EBUF1 0xf4 | ||
159 | #define CH_EBUF2 0xf8 | ||
160 | |||
161 | /* AC-97 Registers */ | ||
162 | |||
163 | #define DX_ACR0_AC97_W 0x40 | ||
164 | #define DX_ACR1_AC97_R 0x44 | ||
165 | #define DX_ACR2_AC97_COM_STAT 0x48 | ||
166 | |||
167 | #define NX_ACR0_AC97_COM_STAT 0x40 | ||
168 | #define NX_ACR1_AC97_W 0x44 | ||
169 | #define NX_ACR2_AC97_R_PRIMARY 0x48 | ||
170 | #define NX_ACR3_AC97_R_SECONDARY 0x4c | ||
171 | |||
172 | #define SI_AC97_WRITE 0x40 | ||
173 | #define SI_AC97_READ 0x44 | ||
174 | #define SI_SERIAL_INTF_CTRL 0x48 | ||
175 | #define SI_AC97_GPIO 0x4c | ||
176 | #define SI_ASR0 0x50 | ||
177 | #define SI_SPDIF_CS 0x70 | ||
178 | #define SI_GPIO 0x7c | ||
179 | |||
180 | enum trident_nx_ac97_bits { | ||
181 | /* ACR1-3 */ | ||
182 | NX_AC97_BUSY_WRITE = 0x0800, | ||
183 | NX_AC97_BUSY_READ = 0x0800, | ||
184 | NX_AC97_BUSY_DATA = 0x0400, | ||
185 | NX_AC97_WRITE_SECONDARY = 0x0100, | ||
186 | /* ACR0 */ | ||
187 | NX_AC97_SECONDARY_READY = 0x0040, | ||
188 | NX_AC97_SECONDARY_RECORD = 0x0020, | ||
189 | NX_AC97_SURROUND_OUTPUT = 0x0010, | ||
190 | NX_AC97_PRIMARY_READY = 0x0008, | ||
191 | NX_AC97_PRIMARY_RECORD = 0x0004, | ||
192 | NX_AC97_PCM_OUTPUT = 0x0002, | ||
193 | NX_AC97_WARM_RESET = 0x0001 | ||
194 | }; | ||
195 | |||
196 | enum trident_dx_ac97_bits { | ||
197 | DX_AC97_BUSY_WRITE = 0x8000, | ||
198 | DX_AC97_BUSY_READ = 0x8000, | ||
199 | DX_AC97_READY = 0x0010, | ||
200 | DX_AC97_RECORD = 0x0008, | ||
201 | DX_AC97_PLAYBACK = 0x0002 | ||
202 | }; | ||
203 | |||
204 | enum sis7018_ac97_bits { | ||
205 | SI_AC97_BUSY_WRITE = 0x00008000, | ||
206 | SI_AC97_AUDIO_BUSY = 0x00004000, | ||
207 | SI_AC97_MODEM_BUSY = 0x00002000, | ||
208 | SI_AC97_BUSY_READ = 0x00008000, | ||
209 | SI_AC97_SECONDARY = 0x00000080, | ||
210 | }; | ||
211 | |||
212 | enum serial_intf_ctrl_bits { | ||
213 | WARM_RESET = 0x00000001, | ||
214 | COLD_RESET = 0x00000002, | ||
215 | I2S_CLOCK = 0x00000004, | ||
216 | PCM_SEC_AC97 = 0x00000008, | ||
217 | AC97_DBL_RATE = 0x00000010, | ||
218 | SPDIF_EN = 0x00000020, | ||
219 | I2S_OUTPUT_EN = 0x00000040, | ||
220 | I2S_INPUT_EN = 0x00000080, | ||
221 | PCMIN = 0x00000100, | ||
222 | LINE1IN = 0x00000200, | ||
223 | MICIN = 0x00000400, | ||
224 | LINE2IN = 0x00000800, | ||
225 | HEAD_SET_IN = 0x00001000, | ||
226 | GPIOIN = 0x00002000, | ||
227 | /* 7018 spec says id = 01 but the demo board routed to 10 | ||
228 | SECONDARY_ID= 0x00004000, */ | ||
229 | SECONDARY_ID = 0x00004000, | ||
230 | PCMOUT = 0x00010000, | ||
231 | SURROUT = 0x00020000, | ||
232 | CENTEROUT = 0x00040000, | ||
233 | LFEOUT = 0x00080000, | ||
234 | LINE1OUT = 0x00100000, | ||
235 | LINE2OUT = 0x00200000, | ||
236 | GPIOOUT = 0x00400000, | ||
237 | SI_AC97_PRIMARY_READY = 0x01000000, | ||
238 | SI_AC97_SECONDARY_READY = 0x02000000, | ||
239 | SI_AC97_POWERDOWN = 0x04000000, | ||
240 | }; | ||
241 | |||
242 | /* PCM defaults */ | ||
243 | |||
244 | #define T4D_DEFAULT_PCM_VOL 10 /* 0 - 255 */ | ||
245 | #define T4D_DEFAULT_PCM_PAN 0 /* 0 - 127 */ | ||
246 | #define T4D_DEFAULT_PCM_RVOL 127 /* 0 - 127 */ | ||
247 | #define T4D_DEFAULT_PCM_CVOL 127 /* 0 - 127 */ | ||
248 | |||
249 | struct snd_trident; | ||
250 | struct snd_trident_voice; | ||
251 | struct snd_trident_pcm_mixer; | ||
252 | |||
253 | struct snd_trident_port { | ||
254 | struct snd_midi_channel_set * chset; | ||
255 | struct snd_trident * trident; | ||
256 | int mode; /* operation mode */ | ||
257 | int client; /* sequencer client number */ | ||
258 | int port; /* sequencer port number */ | ||
259 | unsigned int midi_has_voices: 1; | ||
260 | }; | ||
261 | |||
262 | struct snd_trident_memblk_arg { | ||
263 | short first_page, last_page; | ||
264 | }; | ||
265 | |||
266 | struct snd_trident_tlb { | ||
267 | unsigned int * entries; /* 16k-aligned TLB table */ | ||
268 | dma_addr_t entries_dmaaddr; /* 16k-aligned PCI address to TLB table */ | ||
269 | unsigned long * shadow_entries; /* shadow entries with virtual addresses */ | ||
270 | struct snd_dma_buffer buffer; | ||
271 | struct snd_util_memhdr * memhdr; /* page allocation list */ | ||
272 | struct snd_dma_buffer silent_page; | ||
273 | }; | ||
274 | |||
275 | struct snd_trident_voice { | ||
276 | unsigned int number; | ||
277 | unsigned int use: 1, | ||
278 | pcm: 1, | ||
279 | synth:1, | ||
280 | midi: 1; | ||
281 | unsigned int flags; | ||
282 | unsigned char client; | ||
283 | unsigned char port; | ||
284 | unsigned char index; | ||
285 | |||
286 | struct snd_trident_sample_ops *sample_ops; | ||
287 | |||
288 | /* channel parameters */ | ||
289 | unsigned int CSO; /* 24 bits (16 on DX) */ | ||
290 | unsigned int ESO; /* 24 bits (16 on DX) */ | ||
291 | unsigned int LBA; /* 30 bits */ | ||
292 | unsigned short EC; /* 12 bits */ | ||
293 | unsigned short Alpha; /* 12 bits */ | ||
294 | unsigned short Delta; /* 16 bits */ | ||
295 | unsigned short Attribute; /* 16 bits - SiS 7018 */ | ||
296 | unsigned short Vol; /* 12 bits (6.6) */ | ||
297 | unsigned char Pan; /* 7 bits (1.4.2) */ | ||
298 | unsigned char GVSel; /* 1 bit */ | ||
299 | unsigned char RVol; /* 7 bits (5.2) */ | ||
300 | unsigned char CVol; /* 7 bits (5.2) */ | ||
301 | unsigned char FMC; /* 2 bits */ | ||
302 | unsigned char CTRL; /* 4 bits */ | ||
303 | unsigned char FMS; /* 4 bits */ | ||
304 | unsigned char LFO; /* 8 bits */ | ||
305 | |||
306 | unsigned int negCSO; /* nonzero - use negative CSO */ | ||
307 | |||
308 | struct snd_util_memblk *memblk; /* memory block if TLB enabled */ | ||
309 | |||
310 | /* PCM data */ | ||
311 | |||
312 | struct snd_trident *trident; | ||
313 | struct snd_pcm_substream *substream; | ||
314 | struct snd_trident_voice *extra; /* extra PCM voice (acts as interrupt generator) */ | ||
315 | unsigned int running: 1, | ||
316 | capture: 1, | ||
317 | spdif: 1, | ||
318 | foldback: 1, | ||
319 | isync: 1, | ||
320 | isync2: 1, | ||
321 | isync3: 1; | ||
322 | int foldback_chan; /* foldback subdevice number */ | ||
323 | unsigned int stimer; /* global sample timer (to detect spurious interrupts) */ | ||
324 | unsigned int spurious_threshold; /* spurious threshold */ | ||
325 | unsigned int isync_mark; | ||
326 | unsigned int isync_max; | ||
327 | unsigned int isync_ESO; | ||
328 | |||
329 | /* --- */ | ||
330 | |||
331 | void *private_data; | ||
332 | void (*private_free)(struct snd_trident_voice *voice); | ||
333 | }; | ||
334 | |||
335 | struct snd_4dwave { | ||
336 | int seq_client; | ||
337 | |||
338 | struct snd_trident_port seq_ports[4]; | ||
339 | struct snd_trident_voice voices[64]; | ||
340 | |||
341 | int ChanSynthCount; /* number of allocated synth channels */ | ||
342 | int max_size; /* maximum synth memory size in bytes */ | ||
343 | int current_size; /* current allocated synth mem in bytes */ | ||
344 | }; | ||
345 | |||
346 | struct snd_trident_pcm_mixer { | ||
347 | struct snd_trident_voice *voice; /* active voice */ | ||
348 | unsigned short vol; /* front volume */ | ||
349 | unsigned char pan; /* pan control */ | ||
350 | unsigned char rvol; /* rear volume */ | ||
351 | unsigned char cvol; /* center volume */ | ||
352 | unsigned char pad; | ||
353 | }; | ||
354 | |||
355 | struct snd_trident { | ||
356 | int irq; | ||
357 | |||
358 | unsigned int device; /* device ID */ | ||
359 | |||
360 | unsigned char bDMAStart; | ||
361 | |||
362 | unsigned long port; | ||
363 | unsigned long midi_port; | ||
364 | |||
365 | unsigned int spurious_irq_count; | ||
366 | unsigned int spurious_irq_max_delta; | ||
367 | |||
368 | struct snd_trident_tlb tlb; /* TLB entries for NX cards */ | ||
369 | |||
370 | unsigned char spdif_ctrl; | ||
371 | unsigned char spdif_pcm_ctrl; | ||
372 | unsigned int spdif_bits; | ||
373 | unsigned int spdif_pcm_bits; | ||
374 | struct snd_kcontrol *spdif_pcm_ctl; /* S/PDIF settings */ | ||
375 | unsigned int ac97_ctrl; | ||
376 | |||
377 | unsigned int ChanMap[2]; /* allocation map for hardware channels */ | ||
378 | |||
379 | int ChanPCM; /* max number of PCM channels */ | ||
380 | int ChanPCMcnt; /* actual number of PCM channels */ | ||
381 | |||
382 | unsigned int ac97_detect: 1; /* 1 = AC97 in detection phase */ | ||
383 | unsigned int in_suspend: 1; /* 1 during suspend/resume */ | ||
384 | |||
385 | struct snd_4dwave synth; /* synth specific variables */ | ||
386 | |||
387 | spinlock_t event_lock; | ||
388 | spinlock_t voice_alloc; | ||
389 | |||
390 | struct snd_dma_device dma_dev; | ||
391 | |||
392 | struct pci_dev *pci; | ||
393 | struct snd_card *card; | ||
394 | struct snd_pcm *pcm; /* ADC/DAC PCM */ | ||
395 | struct snd_pcm *foldback; /* Foldback PCM */ | ||
396 | struct snd_pcm *spdif; /* SPDIF PCM */ | ||
397 | struct snd_rawmidi *rmidi; | ||
398 | |||
399 | struct snd_ac97_bus *ac97_bus; | ||
400 | struct snd_ac97 *ac97; | ||
401 | struct snd_ac97 *ac97_sec; | ||
402 | |||
403 | unsigned int musicvol_wavevol; | ||
404 | struct snd_trident_pcm_mixer pcm_mixer[32]; | ||
405 | struct snd_kcontrol *ctl_vol; /* front volume */ | ||
406 | struct snd_kcontrol *ctl_pan; /* pan */ | ||
407 | struct snd_kcontrol *ctl_rvol; /* rear volume */ | ||
408 | struct snd_kcontrol *ctl_cvol; /* center volume */ | ||
409 | |||
410 | spinlock_t reg_lock; | ||
411 | |||
412 | struct gameport *gameport; | ||
413 | }; | ||
414 | |||
415 | int snd_trident_create(struct snd_card *card, | ||
416 | struct pci_dev *pci, | ||
417 | int pcm_streams, | ||
418 | int pcm_spdif_device, | ||
419 | int max_wavetable_size, | ||
420 | struct snd_trident ** rtrident); | ||
421 | int snd_trident_create_gameport(struct snd_trident *trident); | ||
422 | |||
423 | int snd_trident_pcm(struct snd_trident * trident, int device, struct snd_pcm **rpcm); | ||
424 | int snd_trident_foldback_pcm(struct snd_trident * trident, int device, struct snd_pcm **rpcm); | ||
425 | int snd_trident_spdif_pcm(struct snd_trident * trident, int device, struct snd_pcm **rpcm); | ||
426 | int snd_trident_attach_synthesizer(struct snd_trident * trident); | ||
427 | struct snd_trident_voice *snd_trident_alloc_voice(struct snd_trident * trident, int type, | ||
428 | int client, int port); | ||
429 | void snd_trident_free_voice(struct snd_trident * trident, struct snd_trident_voice *voice); | ||
430 | void snd_trident_start_voice(struct snd_trident * trident, unsigned int voice); | ||
431 | void snd_trident_stop_voice(struct snd_trident * trident, unsigned int voice); | ||
432 | void snd_trident_write_voice_regs(struct snd_trident * trident, struct snd_trident_voice *voice); | ||
433 | int snd_trident_suspend(struct pci_dev *pci, pm_message_t state); | ||
434 | int snd_trident_resume(struct pci_dev *pci); | ||
435 | |||
436 | /* TLB memory allocation */ | ||
437 | struct snd_util_memblk *snd_trident_alloc_pages(struct snd_trident *trident, | ||
438 | struct snd_pcm_substream *substream); | ||
439 | int snd_trident_free_pages(struct snd_trident *trident, struct snd_util_memblk *blk); | ||
440 | struct snd_util_memblk *snd_trident_synth_alloc(struct snd_trident *trident, unsigned int size); | ||
441 | int snd_trident_synth_free(struct snd_trident *trident, struct snd_util_memblk *blk); | ||
442 | int snd_trident_synth_copy_from_user(struct snd_trident *trident, struct snd_util_memblk *blk, | ||
443 | int offset, const char __user *data, int size); | ||
444 | |||
445 | #endif /* __SOUND_TRIDENT_H */ | ||
diff --git a/include/sound/vx_core.h b/include/sound/vx_core.h index 5456343ebe4c..4f67c762cd74 100644 --- a/include/sound/vx_core.h +++ b/include/sound/vx_core.h | |||
@@ -341,7 +341,7 @@ int vx_change_frequency(struct vx_core *chip); | |||
341 | /* | 341 | /* |
342 | * PM | 342 | * PM |
343 | */ | 343 | */ |
344 | int snd_vx_suspend(struct vx_core *card, pm_message_t state); | 344 | int snd_vx_suspend(struct vx_core *card); |
345 | int snd_vx_resume(struct vx_core *card); | 345 | int snd_vx_resume(struct vx_core *card); |
346 | 346 | ||
347 | /* | 347 | /* |
diff --git a/include/sound/ymfpci.h b/include/sound/ymfpci.h deleted file mode 100644 index 41199664666b..000000000000 --- a/include/sound/ymfpci.h +++ /dev/null | |||
@@ -1,390 +0,0 @@ | |||
1 | #ifndef __SOUND_YMFPCI_H | ||
2 | #define __SOUND_YMFPCI_H | ||
3 | |||
4 | /* | ||
5 | * Copyright (c) by Jaroslav Kysela <perex@perex.cz> | ||
6 | * Definitions for Yahama YMF724/740/744/754 chips | ||
7 | * | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
22 | * | ||
23 | */ | ||
24 | |||
25 | #include "pcm.h" | ||
26 | #include "rawmidi.h" | ||
27 | #include "ac97_codec.h" | ||
28 | #include "timer.h" | ||
29 | #include <linux/gameport.h> | ||
30 | |||
31 | /* | ||
32 | * Direct registers | ||
33 | */ | ||
34 | |||
35 | #define YMFREG(chip, reg) (chip->port + YDSXGR_##reg) | ||
36 | |||
37 | #define YDSXGR_INTFLAG 0x0004 | ||
38 | #define YDSXGR_ACTIVITY 0x0006 | ||
39 | #define YDSXGR_GLOBALCTRL 0x0008 | ||
40 | #define YDSXGR_ZVCTRL 0x000A | ||
41 | #define YDSXGR_TIMERCTRL 0x0010 | ||
42 | #define YDSXGR_TIMERCOUNT 0x0012 | ||
43 | #define YDSXGR_SPDIFOUTCTRL 0x0018 | ||
44 | #define YDSXGR_SPDIFOUTSTATUS 0x001C | ||
45 | #define YDSXGR_EEPROMCTRL 0x0020 | ||
46 | #define YDSXGR_SPDIFINCTRL 0x0034 | ||
47 | #define YDSXGR_SPDIFINSTATUS 0x0038 | ||
48 | #define YDSXGR_DSPPROGRAMDL 0x0048 | ||
49 | #define YDSXGR_DLCNTRL 0x004C | ||
50 | #define YDSXGR_GPIOININTFLAG 0x0050 | ||
51 | #define YDSXGR_GPIOININTENABLE 0x0052 | ||
52 | #define YDSXGR_GPIOINSTATUS 0x0054 | ||
53 | #define YDSXGR_GPIOOUTCTRL 0x0056 | ||
54 | #define YDSXGR_GPIOFUNCENABLE 0x0058 | ||
55 | #define YDSXGR_GPIOTYPECONFIG 0x005A | ||
56 | #define YDSXGR_AC97CMDDATA 0x0060 | ||
57 | #define YDSXGR_AC97CMDADR 0x0062 | ||
58 | #define YDSXGR_PRISTATUSDATA 0x0064 | ||
59 | #define YDSXGR_PRISTATUSADR 0x0066 | ||
60 | #define YDSXGR_SECSTATUSDATA 0x0068 | ||
61 | #define YDSXGR_SECSTATUSADR 0x006A | ||
62 | #define YDSXGR_SECCONFIG 0x0070 | ||
63 | #define YDSXGR_LEGACYOUTVOL 0x0080 | ||
64 | #define YDSXGR_LEGACYOUTVOLL 0x0080 | ||
65 | #define YDSXGR_LEGACYOUTVOLR 0x0082 | ||
66 | #define YDSXGR_NATIVEDACOUTVOL 0x0084 | ||
67 | #define YDSXGR_NATIVEDACOUTVOLL 0x0084 | ||
68 | #define YDSXGR_NATIVEDACOUTVOLR 0x0086 | ||
69 | #define YDSXGR_ZVOUTVOL 0x0088 | ||
70 | #define YDSXGR_ZVOUTVOLL 0x0088 | ||
71 | #define YDSXGR_ZVOUTVOLR 0x008A | ||
72 | #define YDSXGR_SECADCOUTVOL 0x008C | ||
73 | #define YDSXGR_SECADCOUTVOLL 0x008C | ||
74 | #define YDSXGR_SECADCOUTVOLR 0x008E | ||
75 | #define YDSXGR_PRIADCOUTVOL 0x0090 | ||
76 | #define YDSXGR_PRIADCOUTVOLL 0x0090 | ||
77 | #define YDSXGR_PRIADCOUTVOLR 0x0092 | ||
78 | #define YDSXGR_LEGACYLOOPVOL 0x0094 | ||
79 | #define YDSXGR_LEGACYLOOPVOLL 0x0094 | ||
80 | #define YDSXGR_LEGACYLOOPVOLR 0x0096 | ||
81 | #define YDSXGR_NATIVEDACLOOPVOL 0x0098 | ||
82 | #define YDSXGR_NATIVEDACLOOPVOLL 0x0098 | ||
83 | #define YDSXGR_NATIVEDACLOOPVOLR 0x009A | ||
84 | #define YDSXGR_ZVLOOPVOL 0x009C | ||
85 | #define YDSXGR_ZVLOOPVOLL 0x009E | ||
86 | #define YDSXGR_ZVLOOPVOLR 0x009E | ||
87 | #define YDSXGR_SECADCLOOPVOL 0x00A0 | ||
88 | #define YDSXGR_SECADCLOOPVOLL 0x00A0 | ||
89 | #define YDSXGR_SECADCLOOPVOLR 0x00A2 | ||
90 | #define YDSXGR_PRIADCLOOPVOL 0x00A4 | ||
91 | #define YDSXGR_PRIADCLOOPVOLL 0x00A4 | ||
92 | #define YDSXGR_PRIADCLOOPVOLR 0x00A6 | ||
93 | #define YDSXGR_NATIVEADCINVOL 0x00A8 | ||
94 | #define YDSXGR_NATIVEADCINVOLL 0x00A8 | ||
95 | #define YDSXGR_NATIVEADCINVOLR 0x00AA | ||
96 | #define YDSXGR_NATIVEDACINVOL 0x00AC | ||
97 | #define YDSXGR_NATIVEDACINVOLL 0x00AC | ||
98 | #define YDSXGR_NATIVEDACINVOLR 0x00AE | ||
99 | #define YDSXGR_BUF441OUTVOL 0x00B0 | ||
100 | #define YDSXGR_BUF441OUTVOLL 0x00B0 | ||
101 | #define YDSXGR_BUF441OUTVOLR 0x00B2 | ||
102 | #define YDSXGR_BUF441LOOPVOL 0x00B4 | ||
103 | #define YDSXGR_BUF441LOOPVOLL 0x00B4 | ||
104 | #define YDSXGR_BUF441LOOPVOLR 0x00B6 | ||
105 | #define YDSXGR_SPDIFOUTVOL 0x00B8 | ||
106 | #define YDSXGR_SPDIFOUTVOLL 0x00B8 | ||
107 | #define YDSXGR_SPDIFOUTVOLR 0x00BA | ||
108 | #define YDSXGR_SPDIFLOOPVOL 0x00BC | ||
109 | #define YDSXGR_SPDIFLOOPVOLL 0x00BC | ||
110 | #define YDSXGR_SPDIFLOOPVOLR 0x00BE | ||
111 | #define YDSXGR_ADCSLOTSR 0x00C0 | ||
112 | #define YDSXGR_RECSLOTSR 0x00C4 | ||
113 | #define YDSXGR_ADCFORMAT 0x00C8 | ||
114 | #define YDSXGR_RECFORMAT 0x00CC | ||
115 | #define YDSXGR_P44SLOTSR 0x00D0 | ||
116 | #define YDSXGR_STATUS 0x0100 | ||
117 | #define YDSXGR_CTRLSELECT 0x0104 | ||
118 | #define YDSXGR_MODE 0x0108 | ||
119 | #define YDSXGR_SAMPLECOUNT 0x010C | ||
120 | #define YDSXGR_NUMOFSAMPLES 0x0110 | ||
121 | #define YDSXGR_CONFIG 0x0114 | ||
122 | #define YDSXGR_PLAYCTRLSIZE 0x0140 | ||
123 | #define YDSXGR_RECCTRLSIZE 0x0144 | ||
124 | #define YDSXGR_EFFCTRLSIZE 0x0148 | ||
125 | #define YDSXGR_WORKSIZE 0x014C | ||
126 | #define YDSXGR_MAPOFREC 0x0150 | ||
127 | #define YDSXGR_MAPOFEFFECT 0x0154 | ||
128 | #define YDSXGR_PLAYCTRLBASE 0x0158 | ||
129 | #define YDSXGR_RECCTRLBASE 0x015C | ||
130 | #define YDSXGR_EFFCTRLBASE 0x0160 | ||
131 | #define YDSXGR_WORKBASE 0x0164 | ||
132 | #define YDSXGR_DSPINSTRAM 0x1000 | ||
133 | #define YDSXGR_CTRLINSTRAM 0x4000 | ||
134 | |||
135 | #define YDSXG_AC97READCMD 0x8000 | ||
136 | #define YDSXG_AC97WRITECMD 0x0000 | ||
137 | |||
138 | #define PCIR_DSXG_LEGACY 0x40 | ||
139 | #define PCIR_DSXG_ELEGACY 0x42 | ||
140 | #define PCIR_DSXG_CTRL 0x48 | ||
141 | #define PCIR_DSXG_PWRCTRL1 0x4a | ||
142 | #define PCIR_DSXG_PWRCTRL2 0x4e | ||
143 | #define PCIR_DSXG_FMBASE 0x60 | ||
144 | #define PCIR_DSXG_SBBASE 0x62 | ||
145 | #define PCIR_DSXG_MPU401BASE 0x64 | ||
146 | #define PCIR_DSXG_JOYBASE 0x66 | ||
147 | |||
148 | #define YDSXG_DSPLENGTH 0x0080 | ||
149 | #define YDSXG_CTRLLENGTH 0x3000 | ||
150 | |||
151 | #define YDSXG_DEFAULT_WORK_SIZE 0x0400 | ||
152 | |||
153 | #define YDSXG_PLAYBACK_VOICES 64 | ||
154 | #define YDSXG_CAPTURE_VOICES 2 | ||
155 | #define YDSXG_EFFECT_VOICES 5 | ||
156 | |||
157 | #define YMFPCI_LEGACY_SBEN (1 << 0) /* soundblaster enable */ | ||
158 | #define YMFPCI_LEGACY_FMEN (1 << 1) /* OPL3 enable */ | ||
159 | #define YMFPCI_LEGACY_JPEN (1 << 2) /* joystick enable */ | ||
160 | #define YMFPCI_LEGACY_MEN (1 << 3) /* MPU401 enable */ | ||
161 | #define YMFPCI_LEGACY_MIEN (1 << 4) /* MPU RX irq enable */ | ||
162 | #define YMFPCI_LEGACY_IOBITS (1 << 5) /* i/o bits range, 0 = 16bit, 1 =10bit */ | ||
163 | #define YMFPCI_LEGACY_SDMA (3 << 6) /* SB DMA select */ | ||
164 | #define YMFPCI_LEGACY_SBIRQ (7 << 8) /* SB IRQ select */ | ||
165 | #define YMFPCI_LEGACY_MPUIRQ (7 << 11) /* MPU IRQ select */ | ||
166 | #define YMFPCI_LEGACY_SIEN (1 << 14) /* serialized IRQ */ | ||
167 | #define YMFPCI_LEGACY_LAD (1 << 15) /* legacy audio disable */ | ||
168 | |||
169 | #define YMFPCI_LEGACY2_FMIO (3 << 0) /* OPL3 i/o address (724/740) */ | ||
170 | #define YMFPCI_LEGACY2_SBIO (3 << 2) /* SB i/o address (724/740) */ | ||
171 | #define YMFPCI_LEGACY2_MPUIO (3 << 4) /* MPU401 i/o address (724/740) */ | ||
172 | #define YMFPCI_LEGACY2_JSIO (3 << 6) /* joystick i/o address (724/740) */ | ||
173 | #define YMFPCI_LEGACY2_MAIM (1 << 8) /* MPU401 ack intr mask */ | ||
174 | #define YMFPCI_LEGACY2_SMOD (3 << 11) /* SB DMA mode */ | ||
175 | #define YMFPCI_LEGACY2_SBVER (3 << 13) /* SB version select */ | ||
176 | #define YMFPCI_LEGACY2_IMOD (1 << 15) /* legacy IRQ mode */ | ||
177 | /* SIEN:IMOD 0:0 = legacy irq, 0:1 = INTA, 1:0 = serialized IRQ */ | ||
178 | |||
179 | #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) | ||
180 | #define SUPPORT_JOYSTICK | ||
181 | #endif | ||
182 | |||
183 | /* | ||
184 | * | ||
185 | */ | ||
186 | |||
187 | struct snd_ymfpci_playback_bank { | ||
188 | u32 format; | ||
189 | u32 loop_default; | ||
190 | u32 base; /* 32-bit address */ | ||
191 | u32 loop_start; /* 32-bit offset */ | ||
192 | u32 loop_end; /* 32-bit offset */ | ||
193 | u32 loop_frac; /* 8-bit fraction - loop_start */ | ||
194 | u32 delta_end; /* pitch delta end */ | ||
195 | u32 lpfK_end; | ||
196 | u32 eg_gain_end; | ||
197 | u32 left_gain_end; | ||
198 | u32 right_gain_end; | ||
199 | u32 eff1_gain_end; | ||
200 | u32 eff2_gain_end; | ||
201 | u32 eff3_gain_end; | ||
202 | u32 lpfQ; | ||
203 | u32 status; | ||
204 | u32 num_of_frames; | ||
205 | u32 loop_count; | ||
206 | u32 start; | ||
207 | u32 start_frac; | ||
208 | u32 delta; | ||
209 | u32 lpfK; | ||
210 | u32 eg_gain; | ||
211 | u32 left_gain; | ||
212 | u32 right_gain; | ||
213 | u32 eff1_gain; | ||
214 | u32 eff2_gain; | ||
215 | u32 eff3_gain; | ||
216 | u32 lpfD1; | ||
217 | u32 lpfD2; | ||
218 | }; | ||
219 | |||
220 | struct snd_ymfpci_capture_bank { | ||
221 | u32 base; /* 32-bit address */ | ||
222 | u32 loop_end; /* 32-bit offset */ | ||
223 | u32 start; /* 32-bit offset */ | ||
224 | u32 num_of_loops; /* counter */ | ||
225 | }; | ||
226 | |||
227 | struct snd_ymfpci_effect_bank { | ||
228 | u32 base; /* 32-bit address */ | ||
229 | u32 loop_end; /* 32-bit offset */ | ||
230 | u32 start; /* 32-bit offset */ | ||
231 | u32 temp; | ||
232 | }; | ||
233 | |||
234 | struct snd_ymfpci_pcm; | ||
235 | struct snd_ymfpci; | ||
236 | |||
237 | enum snd_ymfpci_voice_type { | ||
238 | YMFPCI_PCM, | ||
239 | YMFPCI_SYNTH, | ||
240 | YMFPCI_MIDI | ||
241 | }; | ||
242 | |||
243 | struct snd_ymfpci_voice { | ||
244 | struct snd_ymfpci *chip; | ||
245 | int number; | ||
246 | unsigned int use: 1, | ||
247 | pcm: 1, | ||
248 | synth: 1, | ||
249 | midi: 1; | ||
250 | struct snd_ymfpci_playback_bank *bank; | ||
251 | dma_addr_t bank_addr; | ||
252 | void (*interrupt)(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice); | ||
253 | struct snd_ymfpci_pcm *ypcm; | ||
254 | }; | ||
255 | |||
256 | enum snd_ymfpci_pcm_type { | ||
257 | PLAYBACK_VOICE, | ||
258 | CAPTURE_REC, | ||
259 | CAPTURE_AC97, | ||
260 | EFFECT_DRY_LEFT, | ||
261 | EFFECT_DRY_RIGHT, | ||
262 | EFFECT_EFF1, | ||
263 | EFFECT_EFF2, | ||
264 | EFFECT_EFF3 | ||
265 | }; | ||
266 | |||
267 | struct snd_ymfpci_pcm { | ||
268 | struct snd_ymfpci *chip; | ||
269 | enum snd_ymfpci_pcm_type type; | ||
270 | struct snd_pcm_substream *substream; | ||
271 | struct snd_ymfpci_voice *voices[2]; /* playback only */ | ||
272 | unsigned int running: 1, | ||
273 | use_441_slot: 1, | ||
274 | output_front: 1, | ||
275 | output_rear: 1, | ||
276 | swap_rear: 1; | ||
277 | unsigned int update_pcm_vol; | ||
278 | u32 period_size; /* cached from runtime->period_size */ | ||
279 | u32 buffer_size; /* cached from runtime->buffer_size */ | ||
280 | u32 period_pos; | ||
281 | u32 last_pos; | ||
282 | u32 capture_bank_number; | ||
283 | u32 shift; | ||
284 | }; | ||
285 | |||
286 | struct snd_ymfpci { | ||
287 | int irq; | ||
288 | |||
289 | unsigned int device_id; /* PCI device ID */ | ||
290 | unsigned char rev; /* PCI revision */ | ||
291 | unsigned long reg_area_phys; | ||
292 | void __iomem *reg_area_virt; | ||
293 | struct resource *res_reg_area; | ||
294 | struct resource *fm_res; | ||
295 | struct resource *mpu_res; | ||
296 | |||
297 | unsigned short old_legacy_ctrl; | ||
298 | #ifdef SUPPORT_JOYSTICK | ||
299 | struct gameport *gameport; | ||
300 | #endif | ||
301 | |||
302 | struct snd_dma_buffer work_ptr; | ||
303 | |||
304 | unsigned int bank_size_playback; | ||
305 | unsigned int bank_size_capture; | ||
306 | unsigned int bank_size_effect; | ||
307 | unsigned int work_size; | ||
308 | |||
309 | void *bank_base_playback; | ||
310 | void *bank_base_capture; | ||
311 | void *bank_base_effect; | ||
312 | void *work_base; | ||
313 | dma_addr_t bank_base_playback_addr; | ||
314 | dma_addr_t bank_base_capture_addr; | ||
315 | dma_addr_t bank_base_effect_addr; | ||
316 | dma_addr_t work_base_addr; | ||
317 | struct snd_dma_buffer ac3_tmp_base; | ||
318 | |||
319 | u32 *ctrl_playback; | ||
320 | struct snd_ymfpci_playback_bank *bank_playback[YDSXG_PLAYBACK_VOICES][2]; | ||
321 | struct snd_ymfpci_capture_bank *bank_capture[YDSXG_CAPTURE_VOICES][2]; | ||
322 | struct snd_ymfpci_effect_bank *bank_effect[YDSXG_EFFECT_VOICES][2]; | ||
323 | |||
324 | int start_count; | ||
325 | |||
326 | u32 active_bank; | ||
327 | struct snd_ymfpci_voice voices[64]; | ||
328 | int src441_used; | ||
329 | |||
330 | struct snd_ac97_bus *ac97_bus; | ||
331 | struct snd_ac97 *ac97; | ||
332 | struct snd_rawmidi *rawmidi; | ||
333 | struct snd_timer *timer; | ||
334 | unsigned int timer_ticks; | ||
335 | |||
336 | struct pci_dev *pci; | ||
337 | struct snd_card *card; | ||
338 | struct snd_pcm *pcm; | ||
339 | struct snd_pcm *pcm2; | ||
340 | struct snd_pcm *pcm_spdif; | ||
341 | struct snd_pcm *pcm_4ch; | ||
342 | struct snd_pcm_substream *capture_substream[YDSXG_CAPTURE_VOICES]; | ||
343 | struct snd_pcm_substream *effect_substream[YDSXG_EFFECT_VOICES]; | ||
344 | struct snd_kcontrol *ctl_vol_recsrc; | ||
345 | struct snd_kcontrol *ctl_vol_adcrec; | ||
346 | struct snd_kcontrol *ctl_vol_spdifrec; | ||
347 | unsigned short spdif_bits, spdif_pcm_bits; | ||
348 | struct snd_kcontrol *spdif_pcm_ctl; | ||
349 | int mode_dup4ch; | ||
350 | int rear_opened; | ||
351 | int spdif_opened; | ||
352 | struct snd_ymfpci_pcm_mixer { | ||
353 | u16 left; | ||
354 | u16 right; | ||
355 | struct snd_kcontrol *ctl; | ||
356 | } pcm_mixer[32]; | ||
357 | |||
358 | spinlock_t reg_lock; | ||
359 | spinlock_t voice_lock; | ||
360 | wait_queue_head_t interrupt_sleep; | ||
361 | atomic_t interrupt_sleep_count; | ||
362 | struct snd_info_entry *proc_entry; | ||
363 | const struct firmware *dsp_microcode; | ||
364 | const struct firmware *controller_microcode; | ||
365 | |||
366 | #ifdef CONFIG_PM | ||
367 | u32 *saved_regs; | ||
368 | u32 saved_ydsxgr_mode; | ||
369 | u16 saved_dsxg_legacy; | ||
370 | u16 saved_dsxg_elegacy; | ||
371 | #endif | ||
372 | }; | ||
373 | |||
374 | int snd_ymfpci_create(struct snd_card *card, | ||
375 | struct pci_dev *pci, | ||
376 | unsigned short old_legacy_ctrl, | ||
377 | struct snd_ymfpci ** rcodec); | ||
378 | void snd_ymfpci_free_gameport(struct snd_ymfpci *chip); | ||
379 | |||
380 | int snd_ymfpci_suspend(struct pci_dev *pci, pm_message_t state); | ||
381 | int snd_ymfpci_resume(struct pci_dev *pci); | ||
382 | |||
383 | int snd_ymfpci_pcm(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm); | ||
384 | int snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm); | ||
385 | int snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm); | ||
386 | int snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm); | ||
387 | int snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch); | ||
388 | int snd_ymfpci_timer(struct snd_ymfpci *chip, int device); | ||
389 | |||
390 | #endif /* __SOUND_YMFPCI_H */ | ||