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authorJames Courtier-Dutton <James@superbug.co.uk>2006-12-13 06:21:55 -0500
committerJaroslav Kysela <perex@suse.cz>2007-02-09 03:02:24 -0500
commitcbb7d8f9b7b0a9f51c9869d0da63ea75a2c95caf (patch)
tree6e98027b419273fe44b7d598b99910a93616e355 /include/sound/emu10k1.h
parent7c157069bc953c3cfb5926e92d358e46423bf942 (diff)
[ALSA] emu10k1: Update registers defines for the Audigy 2/emu10k2.5
Signed-off-by: James Courtier-Dutton <James@superbug.co.uk> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
Diffstat (limited to 'include/sound/emu10k1.h')
-rw-r--r--include/sound/emu10k1.h63
1 files changed, 55 insertions, 8 deletions
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h
index 32ce4bd31b46..adca71b20daa 100644
--- a/include/sound/emu10k1.h
+++ b/include/sound/emu10k1.h
@@ -460,6 +460,7 @@
460#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */ 460#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
461#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */ 461#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
462 462
463#define A_HR 0x0b /* High Resolution. 24bit playback from host to DSP. */
463#define MAPA 0x0c /* Cache map A */ 464#define MAPA 0x0c /* Cache map A */
464 465
465#define MAPB 0x0d /* Cache map B */ 466#define MAPB 0x0d /* Cache map B */
@@ -467,6 +468,8 @@
467#define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */ 468#define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
468#define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */ 469#define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
469 470
471/* 0x0e, 0x0f: Not used */
472
470#define ENVVOL 0x10 /* Volume envelope register */ 473#define ENVVOL 0x10 /* Volume envelope register */
471#define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */ 474#define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
472 /* 0x8000-n == 666*n usec delay */ 475 /* 0x8000-n == 666*n usec delay */
@@ -555,7 +558,7 @@
555 /* NOTE: All channels contain internal variables; do */ 558 /* NOTE: All channels contain internal variables; do */
556 /* not write to these locations. */ 559 /* not write to these locations. */
557 560
558/* 1f something */ 561/* 0x1f: not used */
559 562
560#define CD0 0x20 /* Cache data 0 register */ 563#define CD0 0x20 /* Cache data 0 register */
561#define CD1 0x21 /* Cache data 1 register */ 564#define CD1 0x21 /* Cache data 1 register */
@@ -625,6 +628,8 @@
625#define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */ 628#define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */
626#define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */ 629#define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */
627 630
631#define A_TBLSZ ` 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */
632
628#define TCBS 0x44 /* Tank cache buffer size register */ 633#define TCBS 0x44 /* Tank cache buffer size register */
629#define TCBS_MASK 0x00000007 /* Tank cache buffer size field */ 634#define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
630#define TCBS_BUFFSIZE_16K 0x00000000 635#define TCBS_BUFFSIZE_16K 0x00000000
@@ -645,7 +650,7 @@
645#define FXBA 0x47 /* FX Buffer Address */ 650#define FXBA 0x47 /* FX Buffer Address */
646#define FXBA_MASK 0xfffff000 /* 20 bit base address */ 651#define FXBA_MASK 0xfffff000 /* 20 bit base address */
647 652
648/* 0x48 something - word access, defaults to 3f */ 653#define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
649 654
650#define MICBS 0x49 /* Microphone buffer size register */ 655#define MICBS 0x49 /* Microphone buffer size register */
651 656
@@ -689,6 +694,18 @@
689#define ADCBS_BUFSIZE_57344 0x0000001e 694#define ADCBS_BUFSIZE_57344 0x0000001e
690#define ADCBS_BUFSIZE_65536 0x0000001f 695#define ADCBS_BUFSIZE_65536 0x0000001f
691 696
697/* Current Send B, A Amounts */
698#define A_CSBA 0x4c
699
700/* Current Send D, C Amounts */
701#define A_CSDC 0x4d
702
703/* Current Send F, E Amounts */
704#define A_CSFE 0x4e
705
706/* Current Send H, G Amounts */
707#define A_CSHG 0x4f
708
692 709
693#define CDCS 0x50 /* CD-ROM digital channel status register */ 710#define CDCS 0x50 /* CD-ROM digital channel status register */
694 711
@@ -696,6 +713,9 @@
696 713
697#define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ 714#define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
698 715
716/* S/PDIF Input C Channel Status */
717#define A_SPSC 0x52
718
699#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ 719#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
700 720
701#define A_DBG 0x53 721#define A_DBG 0x53
@@ -736,6 +756,8 @@
736#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */ 756#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
737#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */ 757#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
738 758
759/* 0x57: Not used */
760
739/* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */ 761/* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
740#define CLIEL 0x58 /* Channel loop interrupt enable low register */ 762#define CLIEL 0x58 /* Channel loop interrupt enable low register */
741 763
@@ -761,6 +783,9 @@
761#define AC97SLOT_CNTR 0x10 /* Center enable */ 783#define AC97SLOT_CNTR 0x10 /* Center enable */
762#define AC97SLOT_LFE 0x20 /* LFE enable */ 784#define AC97SLOT_LFE 0x20 /* LFE enable */
763 785
786/* PCB Revision */
787#define A_PCB 0x5f
788
764// NOTE: 0x60,61,62: 64-bit 789// NOTE: 0x60,61,62: 64-bit
765#define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */ 790#define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
766 791
@@ -808,9 +833,18 @@
808 833
809#define HLIPH 0x69 /* Channel half loop interrupt pending high register */ 834#define HLIPH 0x69 /* Channel half loop interrupt pending high register */
810 835
811// 0x6a,6b,6c used for some recording 836/* S/PDIF Host Record Index (bypasses SRC) */
812// 0x6d unused 837#define A_SPRI 0x6a
813// 0x6e,6f - tanktable base / offset 838/* S/PDIF Host Record Address */
839#define A_SPRA 0x6b
840/* S/PDIF Host Record Control */
841#define A_SPRC 0x6c
842/* Delayed Interrupt Counter & Enable */
843#define A_DICE 0x6d
844/* Tank Table Base */
845#define A_TTB 0x6e
846/* Tank Delay Offset */
847#define A_TDOF 0x6f
814 848
815/* This is the MPU port on the card (via the game port) */ 849/* This is the MPU port on the card (via the game port) */
816#define A_MUDATA1 0x70 850#define A_MUDATA1 0x70
@@ -828,6 +862,7 @@
828#define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */ 862#define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
829#define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */ 863#define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
830 864
865/* Extended Hardware Control */
831#define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */ 866#define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
832#define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */ 867#define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */
833#define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */ 868#define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */
@@ -850,8 +885,20 @@
850#define A_PCM_96000 0x00004000 885#define A_PCM_96000 0x00004000
851#define A_PCM_44100 0x00008000 886#define A_PCM_44100 0x00008000
852 887
853/* 0x77,0x78,0x79 "something i2s-related" - default to 0x01080000 on my audigy 2 ZS --rlrevell */ 888/* I2S0 Sample Rate Tracker Status */
854/* 0x7a, 0x7b - lookup tables */ 889#define A_SRT3 0x77
890
891/* I2S1 Sample Rate Tracker Status */
892#define A_SRT4 0x78
893
894/* I2S2 Sample Rate Tracker Status */
895#define A_SRT5 0x79
896/* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
897
898/* Tank Table DMA Address */
899#define A_TTDA 0x7a
900/* Tank Table DMA Data */
901#define A_TTDD 0x7b
855 902
856#define A_FXRT2 0x7c 903#define A_FXRT2 0x7c
857#define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */ 904#define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
@@ -873,7 +920,7 @@
873#define A_FXRT_CHANNELC 0x003f0000 920#define A_FXRT_CHANNELC 0x003f0000
874#define A_FXRT_CHANNELD 0x3f000000 921#define A_FXRT_CHANNELD 0x3f000000
875 922
876 923/* 0x7f: Not used */
877/* Each FX general purpose register is 32 bits in length, all bits are used */ 924/* Each FX general purpose register is 32 bits in length, all bits are used */
878#define FXGPREGBASE 0x100 /* FX general purpose registers base */ 925#define FXGPREGBASE 0x100 /* FX general purpose registers base */
879#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */ 926#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */