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authorThierry Reding <treding@nvidia.com>2014-07-11 07:19:06 -0400
committerThierry Reding <treding@nvidia.com>2014-07-17 08:58:43 -0400
commit7232398abc6a7186e315425638c367d50c674718 (patch)
tree874b08603b104c3b42a07cb7c1402a8f3bcf5ec0 /include/soc
parent24fa5af81059af90c723bec6aacc3cd2b2809d14 (diff)
ARM: tegra: Convert PMC to a driver
This commit converts the PMC support code to a platform driver. Because the boot process needs to call into this driver very early, also set up a minimal environment via an early initcall. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/soc')
-rw-r--r--include/soc/tegra/pm.h38
-rw-r--r--include/soc/tegra/pmc.h (renamed from include/soc/tegra/powergate.h)31
2 files changed, 65 insertions, 4 deletions
diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h
new file mode 100644
index 000000000000..30fe2078a547
--- /dev/null
+++ b/include/soc/tegra/pm.h
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2014 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __SOC_TEGRA_PM_H__
10#define __SOC_TEGRA_PM_H__
11
12enum tegra_suspend_mode {
13 TEGRA_SUSPEND_NONE = 0,
14 TEGRA_SUSPEND_LP2, /* CPU voltage off */
15 TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */
16 TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */
17 TEGRA_MAX_SUSPEND_MODE,
18};
19
20#ifdef CONFIG_PM_SLEEP
21enum tegra_suspend_mode
22tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode);
23
24/* low-level resume entry point */
25void tegra_resume(void);
26#else
27static inline enum tegra_suspend_mode
28tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode)
29{
30 return TEGRA_SUSPEND_NONE;
31}
32
33static inline void tegra_resume(void)
34{
35}
36#endif /* CONFIG_PM_SLEEP */
37
38#endif /* __SOC_TEGRA_PM_H__ */
diff --git a/include/soc/tegra/powergate.h b/include/soc/tegra/pmc.h
index c16912ed1a8d..65a93273e72f 100644
--- a/include/soc/tegra/powergate.h
+++ b/include/soc/tegra/pmc.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2010 Google, Inc 2 * Copyright (c) 2010 Google, Inc
3 * Copyright (c) 2014 NVIDIA Corporation
3 * 4 *
4 * Author: 5 * Author:
5 * Colin Cross <ccross@google.com> 6 * Colin Cross <ccross@google.com>
@@ -15,12 +16,34 @@
15 * 16 *
16 */ 17 */
17 18
18#ifndef __SOC_TEGRA_POWERGATE_H__ 19#ifndef __SOC_TEGRA_PMC_H__
19#define __SOC_TEGRA_POWERGATE_H__ 20#define __SOC_TEGRA_PMC_H__
21
22#include <linux/reboot.h>
23
24#include <soc/tegra/pm.h>
20 25
21struct clk; 26struct clk;
22struct reset_control; 27struct reset_control;
23 28
29void tegra_pmc_restart(enum reboot_mode mode, const char *cmd);
30
31#ifdef CONFIG_PM_SLEEP
32enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
33void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
34void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
35#endif /* CONFIG_PM_SLEEP */
36
37#ifdef CONFIG_SMP
38bool tegra_pmc_cpu_is_powered(int cpuid);
39int tegra_pmc_cpu_power_on(int cpuid);
40int tegra_pmc_cpu_remove_clamping(int cpuid);
41#endif /* CONFIG_SMP */
42
43/*
44 * powergate and I/O rail APIs
45 */
46
24#define TEGRA_POWERGATE_CPU 0 47#define TEGRA_POWERGATE_CPU 0
25#define TEGRA_POWERGATE_3D 1 48#define TEGRA_POWERGATE_3D 1
26#define TEGRA_POWERGATE_VENC 2 49#define TEGRA_POWERGATE_VENC 2
@@ -129,6 +152,6 @@ static inline int tegra_io_rail_power_off(int id)
129{ 152{
130 return -ENOSYS; 153 return -ENOSYS;
131} 154}
132#endif 155#endif /* CONFIG_ARCH_TEGRA */
133 156
134#endif /* __SOC_TEGRA_POWERGATE_H__ */ 157#endif /* __SOC_TEGRA_PMC_H__ */