diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
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committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/pcmcia/cisreg.h |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'include/pcmcia/cisreg.h')
-rw-r--r-- | include/pcmcia/cisreg.h | 120 |
1 files changed, 120 insertions, 0 deletions
diff --git a/include/pcmcia/cisreg.h b/include/pcmcia/cisreg.h new file mode 100644 index 000000000000..ddaad465502e --- /dev/null +++ b/include/pcmcia/cisreg.h | |||
@@ -0,0 +1,120 @@ | |||
1 | /* | ||
2 | * cisreg.h | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | * | ||
8 | * The initial developer of the original code is David A. Hinds | ||
9 | * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds | ||
10 | * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. | ||
11 | * | ||
12 | * (C) 1999 David A. Hinds | ||
13 | */ | ||
14 | |||
15 | #ifndef _LINUX_CISREG_H | ||
16 | #define _LINUX_CISREG_H | ||
17 | |||
18 | /* | ||
19 | * Offsets from ConfigBase for CIS registers | ||
20 | */ | ||
21 | #define CISREG_COR 0x00 | ||
22 | #define CISREG_CCSR 0x02 | ||
23 | #define CISREG_PRR 0x04 | ||
24 | #define CISREG_SCR 0x06 | ||
25 | #define CISREG_ESR 0x08 | ||
26 | #define CISREG_IOBASE_0 0x0a | ||
27 | #define CISREG_IOBASE_1 0x0c | ||
28 | #define CISREG_IOBASE_2 0x0e | ||
29 | #define CISREG_IOBASE_3 0x10 | ||
30 | #define CISREG_IOSIZE 0x12 | ||
31 | |||
32 | /* | ||
33 | * Configuration Option Register | ||
34 | */ | ||
35 | #define COR_CONFIG_MASK 0x3f | ||
36 | #define COR_MFC_CONFIG_MASK 0x38 | ||
37 | #define COR_FUNC_ENA 0x01 | ||
38 | #define COR_ADDR_DECODE 0x02 | ||
39 | #define COR_IREQ_ENA 0x04 | ||
40 | #define COR_LEVEL_REQ 0x40 | ||
41 | #define COR_SOFT_RESET 0x80 | ||
42 | |||
43 | /* | ||
44 | * Card Configuration and Status Register | ||
45 | */ | ||
46 | #define CCSR_INTR_ACK 0x01 | ||
47 | #define CCSR_INTR_PENDING 0x02 | ||
48 | #define CCSR_POWER_DOWN 0x04 | ||
49 | #define CCSR_AUDIO_ENA 0x08 | ||
50 | #define CCSR_IOIS8 0x20 | ||
51 | #define CCSR_SIGCHG_ENA 0x40 | ||
52 | #define CCSR_CHANGED 0x80 | ||
53 | |||
54 | /* | ||
55 | * Pin Replacement Register | ||
56 | */ | ||
57 | #define PRR_WP_STATUS 0x01 | ||
58 | #define PRR_READY_STATUS 0x02 | ||
59 | #define PRR_BVD2_STATUS 0x04 | ||
60 | #define PRR_BVD1_STATUS 0x08 | ||
61 | #define PRR_WP_EVENT 0x10 | ||
62 | #define PRR_READY_EVENT 0x20 | ||
63 | #define PRR_BVD2_EVENT 0x40 | ||
64 | #define PRR_BVD1_EVENT 0x80 | ||
65 | |||
66 | /* | ||
67 | * Socket and Copy Register | ||
68 | */ | ||
69 | #define SCR_SOCKET_NUM 0x0f | ||
70 | #define SCR_COPY_NUM 0x70 | ||
71 | |||
72 | /* | ||
73 | * Extended Status Register | ||
74 | */ | ||
75 | #define ESR_REQ_ATTN_ENA 0x01 | ||
76 | #define ESR_REQ_ATTN 0x10 | ||
77 | |||
78 | /* | ||
79 | * CardBus Function Status Registers | ||
80 | */ | ||
81 | #define CBFN_EVENT 0x00 | ||
82 | #define CBFN_MASK 0x04 | ||
83 | #define CBFN_STATE 0x08 | ||
84 | #define CBFN_FORCE 0x0c | ||
85 | |||
86 | /* | ||
87 | * These apply to all the CardBus function registers | ||
88 | */ | ||
89 | #define CBFN_WP 0x0001 | ||
90 | #define CBFN_READY 0x0002 | ||
91 | #define CBFN_BVD2 0x0004 | ||
92 | #define CBFN_BVD1 0x0008 | ||
93 | #define CBFN_GWAKE 0x0010 | ||
94 | #define CBFN_INTR 0x8000 | ||
95 | |||
96 | /* | ||
97 | * Extra bits in the Function Event Mask Register | ||
98 | */ | ||
99 | #define FEMR_BAM_ENA 0x0020 | ||
100 | #define FEMR_PWM_ENA 0x0040 | ||
101 | #define FEMR_WKUP_MASK 0x4000 | ||
102 | |||
103 | /* | ||
104 | * Indirect Addressing Registers for Zoomed Video: these are addresses | ||
105 | * in common memory space | ||
106 | */ | ||
107 | #define CISREG_ICTRL0 0x02 /* control registers */ | ||
108 | #define CISREG_ICTRL1 0x03 | ||
109 | #define CISREG_IADDR0 0x04 /* address registers */ | ||
110 | #define CISREG_IADDR1 0x05 | ||
111 | #define CISREG_IADDR2 0x06 | ||
112 | #define CISREG_IADDR3 0x07 | ||
113 | #define CISREG_IDATA0 0x08 /* data registers */ | ||
114 | #define CISREG_IDATA1 0x09 | ||
115 | |||
116 | #define ICTRL0_COMMON 0x01 | ||
117 | #define ICTRL0_AUTOINC 0x02 | ||
118 | #define ICTRL0_BYTEGRAN 0x04 | ||
119 | |||
120 | #endif /* _LINUX_CISREG_H */ | ||