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authorSathya Perla <sathyap@serverengines.com>2010-06-28 20:11:17 -0400
committerDavid S. Miller <davem@davemloft.net>2010-06-30 16:26:42 -0400
commitf3eb62d2cc7da7bea4b394dd06f6bc738aa284e7 (patch)
tree2e98c0b346690eeca0ea6cad6f8f21a9e16af476 /include/net
parent7e307c7ad5340b226966da6e564ec7f717da3adb (diff)
be2net: memory barrier fixes on IBM p7 platform
The ibm p7 architecure seems to reorder memory accesses more aggressively than previous ppc64 architectures. This requires memory barriers to ensure that rx/tx doorbells are pressed only after memory to be DMAed is written. Signed-off-by: Sathya Perla <sathyap@serverengines.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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