[media] omap3isp: Calculate vpclk_div for CSI-2

The video port clock is l3_ick divided by vpclk_div. This clock must be high
enough for the external pixel rate. The video port requires two clock cycles
to process a pixel.

Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>

1 files changed, 0 insertions, 2 deletions

diff --git a/include/media/omap3isp.h b/include/media/omap3isp.h
index 39e0748b0d31..0f0c08b48829 100644
--- a/include/media/omap3isp.h
+++ b/include/media/omap3isp.h
@@ -129,11 +129,9 @@ struct isp_ccp2_cfg {
 /**
  * struct isp_csi2_cfg - CSI2 interface configuration
  * @crc: Enable the cyclic redundancy check
- * @vpclk_div: Video port output clock control
  */
 struct isp_csi2_cfg {
         unsigned crc:1;
-        unsigned vpclk_div:2;
         struct isp_csiphy_lanes_cfg lanecfg;
 };