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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2008-10-14 20:31:54 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2008-10-14 20:31:54 -0400
commit6dc6472581f693b5fc95aebedf67b4960fb85cf0 (patch)
tree06a5a9a08519950575505273eabced331ed51405 /include/media/saa7115.h
parentee673eaa72d8d185012b1027a05e25aba18c267f (diff)
parent8acd3a60bcca17c6d89c73cee3ad6057eb83ba1e (diff)
Merge commit 'origin'
Manual fixup of conflicts on: arch/powerpc/include/asm/dcr-regs.h drivers/net/ibm_newemac/core.h
Diffstat (limited to 'include/media/saa7115.h')
-rw-r--r--include/media/saa7115.h19
1 files changed, 13 insertions, 6 deletions
diff --git a/include/media/saa7115.h b/include/media/saa7115.h
index f677dfb9d373..bab212719591 100644
--- a/include/media/saa7115.h
+++ b/include/media/saa7115.h
@@ -1,5 +1,5 @@
1/* 1/*
2 saa7115.h - definition for saa7113/4/5 inputs and frequency flags 2 saa7115.h - definition for saa7111/3/4/5 inputs and frequency flags
3 3
4 Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl) 4 Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
5 5
@@ -21,13 +21,13 @@
21#ifndef _SAA7115_H_ 21#ifndef _SAA7115_H_
22#define _SAA7115_H_ 22#define _SAA7115_H_
23 23
24/* SAA7113/4/5 HW inputs */ 24/* SAA7111/3/4/5 HW inputs */
25#define SAA7115_COMPOSITE0 0 25#define SAA7115_COMPOSITE0 0
26#define SAA7115_COMPOSITE1 1 26#define SAA7115_COMPOSITE1 1
27#define SAA7115_COMPOSITE2 2 27#define SAA7115_COMPOSITE2 2
28#define SAA7115_COMPOSITE3 3 28#define SAA7115_COMPOSITE3 3
29#define SAA7115_COMPOSITE4 4 /* not available for the saa7113 */ 29#define SAA7115_COMPOSITE4 4 /* not available for the saa7111/3 */
30#define SAA7115_COMPOSITE5 5 /* not available for the saa7113 */ 30#define SAA7115_COMPOSITE5 5 /* not available for the saa7111/3 */
31#define SAA7115_SVIDEO0 6 31#define SAA7115_SVIDEO0 6
32#define SAA7115_SVIDEO1 7 32#define SAA7115_SVIDEO1 7
33#define SAA7115_SVIDEO2 8 33#define SAA7115_SVIDEO2 8
@@ -42,8 +42,15 @@
42#define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */ 42#define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */
43#define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */ 43#define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */
44 44
45#define SAA7115_IPORT_ON 1 45#define SAA7115_IPORT_ON 1
46#define SAA7115_IPORT_OFF 0 46#define SAA7115_IPORT_OFF 0
47
48/* SAA7111 specific output flags */
49#define SAA7111_VBI_BYPASS 2
50#define SAA7111_FMT_YUV422 0x00
51#define SAA7111_FMT_RGB 0x40
52#define SAA7111_FMT_CCIR 0x80
53#define SAA7111_FMT_YUV411 0xc0
47 54
48#endif 55#endif
49 56