PCI: initialize and release SR-IOV capability

If a device has the SR-IOV capability, initialize it (set the ARI
Capable Hierarchy in the lowest numbered PF if necessary; calculate
the System Page Size for the VF MMIO, probe the VF Offset, Stride
and BARs). A lock for the VF bus allocation is also initialized if
a PF is the lowest numbered PF.

Reviewed-by: Matthew Wilcox <willy@linux.intel.com>
Signed-off-by: Yu Zhao <yu.zhao@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

2 files changed, 44 insertions, 0 deletions

diff --git a/include/linux/pci.h b/include/linux/pci.h
index 1f6c5ddaae36..8ce2f2d9ab63 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -93,6 +93,12 @@ enum {
         /* #6: expansion ROM resource */
         PCI_ROM_RESOURCE,
 
+        /* device specific resources */
+#ifdef CONFIG_PCI_IOV
+        PCI_IOV_RESOURCES,
+        PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
+#endif
+
         /* resources assigned to buses behind the bridge */
 #define PCI_BRIDGE_RESOURCE_NUM 4
 
@@ -180,6 +186,7 @@ struct pci_cap_saved_state {
 
 struct pcie_link_state;
 struct pci_vpd;
+struct pci_sriov;
 
 /*
  * The pci_dev structure is used to describe PCI devices.
@@ -257,6 +264,7 @@ struct pci_dev {
         unsigned int    is_managed:1;
         unsigned int    is_pcie:1;
         unsigned int    state_saved:1;
+        unsigned int    is_physfn:1;
         pci_dev_flags_t dev_flags;
         atomic_t        enable_cnt;     /* pci_enable_device has been called */
 
@@ -270,6 +278,9 @@ struct pci_dev {
         struct list_head msi_list;
 #endif
         struct pci_vpd *vpd;
+#ifdef CONFIG_PCI_IOV
+        struct pci_sriov *sriov;        /* SR-IOV capability related */
+#endif
 };
 
 extern struct pci_dev *alloc_pci_dev(void);
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index b647a4df59fc..d4e663877f45 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -375,6 +375,7 @@
 #define  PCI_EXP_TYPE_UPSTREAM  0x5     /* Upstream Port */
 #define  PCI_EXP_TYPE_DOWNSTREAM 0x6    /* Downstream Port */
 #define  PCI_EXP_TYPE_PCI_BRIDGE 0x7    /* PCI/PCI-X Bridge */
+#define  PCI_EXP_TYPE_RC_END    0x9     /* Root Complex Integrated Endpoint */
 #define PCI_EXP_FLAGS_SLOT      0x0100  /* Slot implemented */
 #define PCI_EXP_FLAGS_IRQ       0x3e00  /* Interrupt message number */
 #define PCI_EXP_DEVCAP          4       /* Device capabilities */
@@ -498,6 +499,7 @@
 #define PCI_EXT_CAP_ID_DSN      3
 #define PCI_EXT_CAP_ID_PWR      4
 #define PCI_EXT_CAP_ID_ARI      14
+#define PCI_EXT_CAP_ID_SRIOV    16
 
 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS    4       /* Uncorrectable Error Status */
@@ -615,4 +617,35 @@
 #define  PCI_ARI_CTRL_ACS       0x0002  /* ACS Function Groups Enable */
 #define  PCI_ARI_CTRL_FG(x)     (((x) >> 4) & 7) /* Function Group */
 
+/* Single Root I/O Virtualization */
+#define PCI_SRIOV_CAP           0x04    /* SR-IOV Capabilities */
+#define  PCI_SRIOV_CAP_VFM      0x01    /* VF Migration Capable */
+#define  PCI_SRIOV_CAP_INTR(x)  ((x) >> 21) /* Interrupt Message Number */
+#define PCI_SRIOV_CTRL          0x08    /* SR-IOV Control */
+#define  PCI_SRIOV_CTRL_VFE     0x01    /* VF Enable */
+#define  PCI_SRIOV_CTRL_VFM     0x02    /* VF Migration Enable */
+#define  PCI_SRIOV_CTRL_INTR    0x04    /* VF Migration Interrupt Enable */
+#define  PCI_SRIOV_CTRL_MSE     0x08    /* VF Memory Space Enable */
+#define  PCI_SRIOV_CTRL_ARI     0x10    /* ARI Capable Hierarchy */
+#define PCI_SRIOV_STATUS        0x0a    /* SR-IOV Status */
+#define  PCI_SRIOV_STATUS_VFM   0x01    /* VF Migration Status */
+#define PCI_SRIOV_INITIAL_VF    0x0c    /* Initial VFs */
+#define PCI_SRIOV_TOTAL_VF      0x0e    /* Total VFs */
+#define PCI_SRIOV_NUM_VF        0x10    /* Number of VFs */
+#define PCI_SRIOV_FUNC_LINK     0x12    /* Function Dependency Link */
+#define PCI_SRIOV_VF_OFFSET     0x14    /* First VF Offset */
+#define PCI_SRIOV_VF_STRIDE     0x16    /* Following VF Stride */
+#define PCI_SRIOV_VF_DID        0x1a    /* VF Device ID */
+#define PCI_SRIOV_SUP_PGSIZE    0x1c    /* Supported Page Sizes */
+#define PCI_SRIOV_SYS_PGSIZE    0x20    /* System Page Size */
+#define PCI_SRIOV_BAR           0x24    /* VF BAR0 */
+#define  PCI_SRIOV_NUM_BARS     6       /* Number of VF BARs */
+#define PCI_SRIOV_VFM           0x3c    /* VF Migration State Array Offset*/
+#define  PCI_SRIOV_VFM_BIR(x)   ((x) & 7)       /* State BIR */
+#define  PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7)     /* State Offset */
+#define  PCI_SRIOV_VFM_UA       0x0     /* Inactive.Unavailable */
+#define  PCI_SRIOV_VFM_MI       0x1     /* Dormant.MigrateIn */
+#define  PCI_SRIOV_VFM_MO       0x2     /* Active.MigrateOut */
+#define  PCI_SRIOV_VFM_AV       0x3     /* Active.Available */
+
 #endif /* LINUX_PCI_REGS_H */