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authorThomas Gleixner <tglx@linutronix.de>2013-09-17 14:53:05 -0400
committerThomas Gleixner <tglx@linutronix.de>2013-11-13 14:21:46 -0500
commit54197e43a4a9a0f3fc406d72d9815754e84fab1e (patch)
tree70db3c0a63b066ac7a8c9e7fabbb8127d73717da /include/linux
parent09f90f6685cd88b6b904c141035d096169958cc4 (diff)
hardirq: Make hardirq bits generic
There is no reason for per arch hardirq bits. Make them all generic Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/20130917183628.534494408@linutronix.de
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/preempt_mask.h30
1 files changed, 8 insertions, 22 deletions
diff --git a/include/linux/preempt_mask.h b/include/linux/preempt_mask.h
index 931bc616219f..810d7e386f20 100644
--- a/include/linux/preempt_mask.h
+++ b/include/linux/preempt_mask.h
@@ -11,36 +11,22 @@
11 * - bits 0-7 are the preemption count (max preemption depth: 256) 11 * - bits 0-7 are the preemption count (max preemption depth: 256)
12 * - bits 8-15 are the softirq count (max # of softirqs: 256) 12 * - bits 8-15 are the softirq count (max # of softirqs: 256)
13 * 13 *
14 * The hardirq count can in theory reach the same as NR_IRQS. 14 * The hardirq count could in theory be the same as the number of
15 * In reality, the number of nested IRQS is limited to the stack 15 * interrupts in the system, but we run all interrupt handlers with
16 * size as well. For archs with over 1000 IRQS it is not practical 16 * interrupts disabled, so we cannot have nesting interrupts. Though
17 * to expect that they will all nest. We give a max of 10 bits for 17 * there are a few palaeontologic drivers which reenable interrupts in
18 * hardirq nesting. An arch may choose to give less than 10 bits. 18 * the handler, so we need more than one bit here.
19 * m68k expects it to be 8.
20 *
21 * - bits 16-25 are the hardirq count (max # of nested hardirqs: 1024)
22 * - bit 26 is the NMI_MASK
23 * - bit 27 is the PREEMPT_ACTIVE flag
24 * 19 *
25 * PREEMPT_MASK: 0x000000ff 20 * PREEMPT_MASK: 0x000000ff
26 * SOFTIRQ_MASK: 0x0000ff00 21 * SOFTIRQ_MASK: 0x0000ff00
27 * HARDIRQ_MASK: 0x03ff0000 22 * HARDIRQ_MASK: 0x000f0000
28 * NMI_MASK: 0x04000000 23 * NMI_MASK: 0x00100000
29 */ 24 */
30#define PREEMPT_BITS 8 25#define PREEMPT_BITS 8
31#define SOFTIRQ_BITS 8 26#define SOFTIRQ_BITS 8
27#define HARDIRQ_BITS 4
32#define NMI_BITS 1 28#define NMI_BITS 1
33 29
34#define MAX_HARDIRQ_BITS 10
35
36#ifndef HARDIRQ_BITS
37# define HARDIRQ_BITS MAX_HARDIRQ_BITS
38#endif
39
40#if HARDIRQ_BITS > MAX_HARDIRQ_BITS
41#error HARDIRQ_BITS too high!
42#endif
43
44#define PREEMPT_SHIFT 0 30#define PREEMPT_SHIFT 0
45#define SOFTIRQ_SHIFT (PREEMPT_SHIFT + PREEMPT_BITS) 31#define SOFTIRQ_SHIFT (PREEMPT_SHIFT + PREEMPT_BITS)
46#define HARDIRQ_SHIFT (SOFTIRQ_SHIFT + SOFTIRQ_BITS) 32#define HARDIRQ_SHIFT (SOFTIRQ_SHIFT + SOFTIRQ_BITS)