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authorRafael J. Wysocki <rjw@sisk.pl>2008-07-06 21:36:24 -0400
committerJesse Barnes <jbarnes@virtuousgeek.org>2008-07-07 19:26:50 -0400
commit337001b6c42938f49a880b1b8306c3ed771a7e61 (patch)
tree0e704359c989beba626388cf2404f038e55f442e /include/linux
parent404cc2d8ce41ed4031958fba8e633767e8a2e028 (diff)
PCI: Simplify PCI device PM code
If the offset of PCI device's PM capability in its configuration space, the mask of states that the device supports PME# from and the D1 and D2 support bits are cached in the corresponding struct pci_dev, the PCI device PM code can be simplified quite a bit. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/pci.h8
-rw-r--r--include/linux/pci_regs.h1
2 files changed, 8 insertions, 1 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 52ac06dcce98..68a29f0f2748 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -177,6 +177,13 @@ struct pci_dev {
177 pci_power_t current_state; /* Current operating state. In ACPI-speak, 177 pci_power_t current_state; /* Current operating state. In ACPI-speak,
178 this is D0-D3, D0 being fully functional, 178 this is D0-D3, D0 being fully functional,
179 and D3 being off. */ 179 and D3 being off. */
180 int pm_cap; /* PM capability offset in the
181 configuration space */
182 unsigned int pme_support:5; /* Bitmask of states from which PME#
183 can be generated */
184 unsigned int d1_support:1; /* Low power state D1 is supported */
185 unsigned int d2_support:1; /* Low power state D2 is supported */
186 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
180 187
181#ifdef CONFIG_PCIEASPM 188#ifdef CONFIG_PCIEASPM
182 struct pcie_link_state *link_state; /* ASPM link state. */ 189 struct pcie_link_state *link_state; /* ASPM link state. */
@@ -201,7 +208,6 @@ struct pci_dev {
201 unsigned int is_added:1; 208 unsigned int is_added:1;
202 unsigned int is_busmaster:1; /* device is busmaster */ 209 unsigned int is_busmaster:1; /* device is busmaster */
203 unsigned int no_msi:1; /* device may not use msi */ 210 unsigned int no_msi:1; /* device may not use msi */
204 unsigned int no_d1d2:1; /* only allow d0 or d3 */
205 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ 211 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
206 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 212 unsigned int broken_parity_status:1; /* Device generates false positive parity */
207 unsigned int msi_enabled:1; 213 unsigned int msi_enabled:1;
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index c0c1223c9194..19958b929905 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -231,6 +231,7 @@
231#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ 231#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
232#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ 232#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
233#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ 233#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
234#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */
234#define PCI_PM_CTRL 4 /* PM control and status register */ 235#define PCI_PM_CTRL 4 /* PM control and status register */
235#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 236#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
236#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */ 237#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */