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authorAnant Gole <anantgole@ti.com>2009-10-06 22:59:47 -0400
committerDavid S. Miller <davem@davemloft.net>2009-10-08 01:02:53 -0400
commit3758bf25db8caeec667e4e56e030da0ec3060529 (patch)
tree5eacde81468c8e201086083a19456ba28e67e3e0 /include/linux
parent0cdc03698f2586923ad3b9fca06643ff5675f221 (diff)
can: add TI CAN (HECC) driver
TI HECC (High End CAN Controller) module is found on many TI devices. It has 32 hardware mailboxes with full implementation of CAN protocol 2.0B with bus speeds up to 1Mbps. Specifications of the module are available on TI web <http://www.ti.com> Signed-off-by: Anant Gole <anantgole@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/can/platform/ti_hecc.h40
1 files changed, 40 insertions, 0 deletions
diff --git a/include/linux/can/platform/ti_hecc.h b/include/linux/can/platform/ti_hecc.h
new file mode 100644
index 000000000000..4688c7bb1bd1
--- /dev/null
+++ b/include/linux/can/platform/ti_hecc.h
@@ -0,0 +1,40 @@
1/*
2 * TI HECC (High End CAN Controller) driver platform header
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed as is WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17/**
18 * struct hecc_platform_data - HECC Platform Data
19 *
20 * @scc_hecc_offset: mostly 0 - should really never change
21 * @scc_ram_offset: SCC RAM offset
22 * @hecc_ram_offset: HECC RAM offset
23 * @mbx_offset: Mailbox RAM offset
24 * @int_line: Interrupt line to use - 0 or 1
25 * @version: version for future use
26 *
27 * Platform data structure to get all platform specific settings.
28 * this structure also accounts the fact that the IP may have different
29 * RAM and mailbox offsets for different SOC's
30 */
31struct ti_hecc_platform_data {
32 u32 scc_hecc_offset;
33 u32 scc_ram_offset;
34 u32 hecc_ram_offset;
35 u32 mbx_offset;
36 u32 int_line;
37 u32 version;
38};
39
40