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authorLinus Torvalds <torvalds@linux-foundation.org>2012-03-28 16:56:35 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-03-28 16:56:35 -0400
commit30304e5a79d424eb2c8707b3ff0e9b8bf6ab3e8f (patch)
tree63968fb97b86861e31922515395feef8a110f884 /include/linux
parent750f77064a290beb162352077b52c61b04bcae0e (diff)
parentb8589e2a8065b8e7773742b60ae96b63b757bb69 (diff)
Merge tag 'mfd_3.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
Pull MFD changes from Samuel Ortiz: - 4 new drivers: Freescale i.MX on-chip Anatop, Ricoh's RC5T583 and TI's TPS65090 and TPS65217. - New variants support (8420, 8520 ab9540), cleanups and bug fixes for the abx500 and db8500 ST-E chipsets. - Some minor fixes and update for the wm8994 from Mark. - The beginning of a long term TWL cleanup effort coming from the TI folks. - Various fixes and cleanups for the s5m, TPS659xx, pm860x, and MAX8997 drivers. Fix up trivial conflicts due to duplicate patches and header file cleanups (<linux/device.h> removal etc). * tag 'mfd_3.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (97 commits) gpio/twl: Add DT support to gpio-twl4030 driver gpio/twl: Allocate irq_desc dynamically for SPARSE_IRQ support mfd: Detach twl6040 from the pmic mfd driver mfd: Replace twl-* pr_ macros by the dev_ equivalent and do various cleanups mfd: Micro-optimization on twl4030 IRQ handler mfd: Make twl4030 SIH SPARSE_IRQ capable mfd: Move twl-core IRQ allocation into twl[4030|6030]-irq files mfd: Remove references already defineid in header file from twl-core mfd: Remove unneeded header from twl-core mfd: Make twl-core not depend on pdata->irq_base/end ARM: OMAP2+: board-omap4-*: Do not use anymore TWL6030_IRQ_BASE in board files mfd: Return twl6030_mmc_card_detect IRQ for board setup Revert "mfd: Add platform data for MAX8997 haptic driver" mfd: Add support for TPS65090 mfd: Add some da9052-i2c section annotations mfd: Build rtc5t583 only if I2C config is selected to y. mfd: Add anatop mfd driver mfd: Fix compilation error in tps65910.h mfd: Add 8420 variant to db8500-prcmu mfd: Add 8520 PRCMU variant to db8500-prcmu ...
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/i2c/twl.h2
-rw-r--r--include/linux/mfd/88pm860x.h23
-rw-r--r--include/linux/mfd/abx500.h7
-rw-r--r--include/linux/mfd/abx500/ab8500-gpio.h4
-rw-r--r--include/linux/mfd/abx500/ab8500-sysctrl.h43
-rw-r--r--include/linux/mfd/abx500/ab8500.h208
-rw-r--r--include/linux/mfd/anatop.h40
-rw-r--r--include/linux/mfd/da9052/da9052.h2
-rw-r--r--include/linux/mfd/db8500-prcmu.h183
-rw-r--r--include/linux/mfd/dbx500-prcmu.h414
-rw-r--r--include/linux/mfd/mc13xxx.h16
-rw-r--r--include/linux/mfd/rc5t583.h295
-rw-r--r--include/linux/mfd/stmpe.h1
-rw-r--r--include/linux/mfd/tps65090.h46
-rw-r--r--include/linux/mfd/tps65217.h283
-rw-r--r--include/linux/mfd/tps65910.h3
-rw-r--r--include/linux/mfd/wm8994/pdata.h1
-rw-r--r--include/linux/regulator/ab8500.h70
18 files changed, 1480 insertions, 161 deletions
diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index 7fcab23c59ce..2463b6100333 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -761,7 +761,7 @@ struct twl_regulator_driver_data {
761 761
762/*----------------------------------------------------------------------*/ 762/*----------------------------------------------------------------------*/
763 763
764int twl4030_sih_setup(int module); 764int twl4030_sih_setup(struct device *dev, int module, int irq_base);
765 765
766/* Offsets to Power Registers */ 766/* Offsets to Power Registers */
767#define TWL4030_VDAC_DEV_GRP 0x3B 767#define TWL4030_VDAC_DEV_GRP 0x3B
diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h
index 92be3476c9f5..84d071ade1d8 100644
--- a/include/linux/mfd/88pm860x.h
+++ b/include/linux/mfd/88pm860x.h
@@ -263,6 +263,22 @@ enum {
263#define PM8607_PD_PREBIAS_MASK (0x1F << 0) 263#define PM8607_PD_PREBIAS_MASK (0x1F << 0)
264#define PM8607_PD_PRECHG_MASK (7 << 5) 264#define PM8607_PD_PRECHG_MASK (7 << 5)
265 265
266#define PM8606_REF_GP_OSC_OFF 0
267#define PM8606_REF_GP_OSC_ON 1
268#define PM8606_REF_GP_OSC_UNKNOWN 2
269
270/* Clients of reference group and 8MHz oscillator in 88PM8606 */
271enum pm8606_ref_gp_and_osc_clients {
272 REF_GP_NO_CLIENTS = 0,
273 WLED1_DUTY = (1<<0), /*PF 0x02.7:0*/
274 WLED2_DUTY = (1<<1), /*PF 0x04.7:0*/
275 WLED3_DUTY = (1<<2), /*PF 0x06.7:0*/
276 RGB1_ENABLE = (1<<3), /*PF 0x07.1*/
277 RGB2_ENABLE = (1<<4), /*PF 0x07.2*/
278 LDO_VBR_EN = (1<<5), /*PF 0x12.0*/
279 REF_GP_MAX_CLIENT = 0xFFFF
280};
281
266/* Interrupt Number in 88PM8607 */ 282/* Interrupt Number in 88PM8607 */
267enum { 283enum {
268 PM8607_IRQ_ONKEY, 284 PM8607_IRQ_ONKEY,
@@ -298,6 +314,7 @@ enum {
298struct pm860x_chip { 314struct pm860x_chip {
299 struct device *dev; 315 struct device *dev;
300 struct mutex irq_lock; 316 struct mutex irq_lock;
317 struct mutex osc_lock;
301 struct i2c_client *client; 318 struct i2c_client *client;
302 struct i2c_client *companion; /* companion chip client */ 319 struct i2c_client *companion; /* companion chip client */
303 struct regmap *regmap; 320 struct regmap *regmap;
@@ -305,12 +322,15 @@ struct pm860x_chip {
305 322
306 int buck3_double; /* DVC ramp slope double */ 323 int buck3_double; /* DVC ramp slope double */
307 unsigned short companion_addr; 324 unsigned short companion_addr;
325 unsigned short osc_vote;
308 int id; 326 int id;
309 int irq_mode; 327 int irq_mode;
310 int irq_base; 328 int irq_base;
311 int core_irq; 329 int core_irq;
312 unsigned char chip_version; 330 unsigned char chip_version;
331 unsigned char osc_status;
313 332
333 unsigned int wakeup_flag;
314}; 334};
315 335
316enum { 336enum {
@@ -369,6 +389,9 @@ struct pm860x_platform_data {
369 int num_regulators; 389 int num_regulators;
370}; 390};
371 391
392extern int pm8606_osc_enable(struct pm860x_chip *, unsigned short);
393extern int pm8606_osc_disable(struct pm860x_chip *, unsigned short);
394
372extern int pm860x_reg_read(struct i2c_client *, int); 395extern int pm860x_reg_read(struct i2c_client *, int);
373extern int pm860x_reg_write(struct i2c_client *, int, unsigned char); 396extern int pm860x_reg_write(struct i2c_client *, int, unsigned char);
374extern int pm860x_bulk_read(struct i2c_client *, int, int, unsigned char *); 397extern int pm860x_bulk_read(struct i2c_client *, int, int, unsigned char *);
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index e20dd6ead1d0..5fa697477b71 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -34,13 +34,6 @@ struct device;
34#define AB5500_1_1 0x21 34#define AB5500_1_1 0x21
35#define AB5500_2_0 0x24 35#define AB5500_2_0 0x24
36 36
37/* AB8500 CIDs*/
38#define AB8500_CUT1P0 0x10
39#define AB8500_CUT1P1 0x11
40#define AB8500_CUT2P0 0x20
41#define AB8500_CUT3P0 0x30
42#define AB8500_CUT3P3 0x33
43
44/* 37/*
45 * AB3100, EVENTA1, A2 and A3 event register flags 38 * AB3100, EVENTA1, A2 and A3 event register flags
46 * these are catenated into a single 32-bit flag in the code 39 * these are catenated into a single 32-bit flag in the code
diff --git a/include/linux/mfd/abx500/ab8500-gpio.h b/include/linux/mfd/abx500/ab8500-gpio.h
index 488a8c920a29..2387c207ea86 100644
--- a/include/linux/mfd/abx500/ab8500-gpio.h
+++ b/include/linux/mfd/abx500/ab8500-gpio.h
@@ -10,12 +10,14 @@
10 10
11/* 11/*
12 * Platform data to register a block: only the initial gpio/irq number. 12 * Platform data to register a block: only the initial gpio/irq number.
13 * Array sizes are large enough to contain all AB8500 and AB9540 GPIO
14 * registers.
13 */ 15 */
14 16
15struct ab8500_gpio_platform_data { 17struct ab8500_gpio_platform_data {
16 int gpio_base; 18 int gpio_base;
17 u32 irq_base; 19 u32 irq_base;
18 u8 config_reg[7]; 20 u8 config_reg[8];
19}; 21};
20 22
21#endif /* _AB8500_GPIO_H */ 23#endif /* _AB8500_GPIO_H */
diff --git a/include/linux/mfd/abx500/ab8500-sysctrl.h b/include/linux/mfd/abx500/ab8500-sysctrl.h
index 10da0291f8f8..10eb50973c39 100644
--- a/include/linux/mfd/abx500/ab8500-sysctrl.h
+++ b/include/linux/mfd/abx500/ab8500-sysctrl.h
@@ -71,6 +71,13 @@ static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
71#define AB8500_SWATCTRL 0x230 71#define AB8500_SWATCTRL 0x230
72#define AB8500_HIQCLKCTRL 0x232 72#define AB8500_HIQCLKCTRL 0x232
73#define AB8500_VSIMSYSCLKCTRL 0x233 73#define AB8500_VSIMSYSCLKCTRL 0x233
74#define AB9540_SYSCLK12BUFCTRL 0x234
75#define AB9540_SYSCLK12CONFCTRL 0x235
76#define AB9540_SYSCLK12BUFCTRL2 0x236
77#define AB9540_SYSCLK12BUF1VALID 0x237
78#define AB9540_SYSCLK12BUF2VALID 0x238
79#define AB9540_SYSCLK12BUF3VALID 0x239
80#define AB9540_SYSCLK12BUF4VALID 0x23A
74 81
75/* Bits */ 82/* Bits */
76#define AB8500_TURNONSTATUS_PORNVBAT BIT(0) 83#define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
@@ -251,4 +258,40 @@ static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
251#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6) 258#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6)
252#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7) 259#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7)
253 260
261#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA BIT(0)
262#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA BIT(1)
263#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA BIT(2)
264#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA BIT(3)
265#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFENA_MASK 0x0F
266#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE BIT(4)
267#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE BIT(5)
268#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE BIT(6)
269#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE BIT(7)
270#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFSTRE_MASK 0xF0
271
272#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
273#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
274#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C
275#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2
276#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
277#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
278#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
279
280#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA BIT(0)
281#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA BIT(1)
282#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA BIT(2)
283#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA BIT(3)
284
285#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_MASK 0xFF
286#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_SHIFT 0
287
288#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_MASK 0xFF
289#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_SHIFT 0
290
291#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_MASK 0xFF
292#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_SHIFT 0
293
294#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF
295#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0
296
254#endif /* __AB8500_SYSCTRL_H */ 297#endif /* __AB8500_SYSCTRL_H */
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h
index dca94396190d..fccc3002f271 100644
--- a/include/linux/mfd/abx500/ab8500.h
+++ b/include/linux/mfd/abx500/ab8500.h
@@ -12,6 +12,29 @@
12struct device; 12struct device;
13 13
14/* 14/*
15 * AB IC versions
16 *
17 * AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a
18 * non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the
19 * print of version string.
20 */
21enum ab8500_version {
22 AB8500_VERSION_AB8500 = 0x0,
23 AB8500_VERSION_AB8505 = 0x1,
24 AB8500_VERSION_AB9540 = 0x2,
25 AB8500_VERSION_AB8540 = 0x3,
26 AB8500_VERSION_UNDEFINED,
27};
28
29/* AB8500 CIDs*/
30#define AB8500_CUTEARLY 0x00
31#define AB8500_CUT1P0 0x10
32#define AB8500_CUT1P1 0x11
33#define AB8500_CUT2P0 0x20
34#define AB8500_CUT3P0 0x30
35#define AB8500_CUT3P3 0x33
36
37/*
15 * AB8500 bank addresses 38 * AB8500 bank addresses
16 */ 39 */
17#define AB8500_SYS_CTRL1_BLOCK 0x1 40#define AB8500_SYS_CTRL1_BLOCK 0x1
@@ -37,30 +60,34 @@ struct device;
37 60
38/* 61/*
39 * Interrupts 62 * Interrupts
63 * Values used to index into array ab8500_irq_regoffset[] defined in
64 * drivers/mdf/ab8500-core.c
40 */ 65 */
41 66/* Definitions for AB8500 and AB9540 */
42#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 67/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
43#define AB8500_INT_UN_PLUG_TV_DET 1 68#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */
44#define AB8500_INT_PLUG_TV_DET 2 69#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540 */
70#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540 */
45#define AB8500_INT_TEMP_WARM 3 71#define AB8500_INT_TEMP_WARM 3
46#define AB8500_INT_PON_KEY2DB_F 4 72#define AB8500_INT_PON_KEY2DB_F 4
47#define AB8500_INT_PON_KEY2DB_R 5 73#define AB8500_INT_PON_KEY2DB_R 5
48#define AB8500_INT_PON_KEY1DB_F 6 74#define AB8500_INT_PON_KEY1DB_F 6
49#define AB8500_INT_PON_KEY1DB_R 7 75#define AB8500_INT_PON_KEY1DB_R 7
76/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
50#define AB8500_INT_BATT_OVV 8 77#define AB8500_INT_BATT_OVV 8
51#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 78#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505 */
52#define AB8500_INT_MAIN_CH_PLUG_DET 11 79#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505 */
53#define AB8500_INT_USB_ID_DET_F 12
54#define AB8500_INT_USB_ID_DET_R 13
55#define AB8500_INT_VBUS_DET_F 14 80#define AB8500_INT_VBUS_DET_F 14
56#define AB8500_INT_VBUS_DET_R 15 81#define AB8500_INT_VBUS_DET_R 15
82/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
57#define AB8500_INT_VBUS_CH_DROP_END 16 83#define AB8500_INT_VBUS_CH_DROP_END 16
58#define AB8500_INT_RTC_60S 17 84#define AB8500_INT_RTC_60S 17
59#define AB8500_INT_RTC_ALARM 18 85#define AB8500_INT_RTC_ALARM 18
60#define AB8500_INT_BAT_CTRL_INDB 20 86#define AB8500_INT_BAT_CTRL_INDB 20
61#define AB8500_INT_CH_WD_EXP 21 87#define AB8500_INT_CH_WD_EXP 21
62#define AB8500_INT_VBUS_OVV 22 88#define AB8500_INT_VBUS_OVV 22
63#define AB8500_INT_MAIN_CH_DROP_END 23 89#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540 */
90/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
64#define AB8500_INT_CCN_CONV_ACC 24 91#define AB8500_INT_CCN_CONV_ACC 24
65#define AB8500_INT_INT_AUD 25 92#define AB8500_INT_INT_AUD 25
66#define AB8500_INT_CCEOC 26 93#define AB8500_INT_CCEOC 26
@@ -69,7 +96,8 @@ struct device;
69#define AB8500_INT_LOW_BAT_R 29 96#define AB8500_INT_LOW_BAT_R 29
70#define AB8500_INT_BUP_CHG_NOT_OK 30 97#define AB8500_INT_BUP_CHG_NOT_OK 30
71#define AB8500_INT_BUP_CHG_OK 31 98#define AB8500_INT_BUP_CHG_OK 31
72#define AB8500_INT_GP_HW_ADC_CONV_END 32 99/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
100#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505 */
73#define AB8500_INT_ACC_DETECT_1DB_F 33 101#define AB8500_INT_ACC_DETECT_1DB_F 33
74#define AB8500_INT_ACC_DETECT_1DB_R 34 102#define AB8500_INT_ACC_DETECT_1DB_R 34
75#define AB8500_INT_ACC_DETECT_22DB_F 35 103#define AB8500_INT_ACC_DETECT_22DB_F 35
@@ -77,38 +105,43 @@ struct device;
77#define AB8500_INT_ACC_DETECT_21DB_F 37 105#define AB8500_INT_ACC_DETECT_21DB_F 37
78#define AB8500_INT_ACC_DETECT_21DB_R 38 106#define AB8500_INT_ACC_DETECT_21DB_R 38
79#define AB8500_INT_GP_SW_ADC_CONV_END 39 107#define AB8500_INT_GP_SW_ADC_CONV_END 39
80#define AB8500_INT_GPIO6R 40 108/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
81#define AB8500_INT_GPIO7R 41 109#define AB8500_INT_GPIO6R 40 /* not 8505/9540 */
82#define AB8500_INT_GPIO8R 42 110#define AB8500_INT_GPIO7R 41 /* not 8505/9540 */
83#define AB8500_INT_GPIO9R 43 111#define AB8500_INT_GPIO8R 42 /* not 8505/9540 */
112#define AB8500_INT_GPIO9R 43 /* not 8505/9540 */
84#define AB8500_INT_GPIO10R 44 113#define AB8500_INT_GPIO10R 44
85#define AB8500_INT_GPIO11R 45 114#define AB8500_INT_GPIO11R 45
86#define AB8500_INT_GPIO12R 46 115#define AB8500_INT_GPIO12R 46 /* not 8505 */
87#define AB8500_INT_GPIO13R 47 116#define AB8500_INT_GPIO13R 47
88#define AB8500_INT_GPIO24R 48 117/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
89#define AB8500_INT_GPIO25R 49 118#define AB8500_INT_GPIO24R 48 /* not 8505 */
90#define AB8500_INT_GPIO36R 50 119#define AB8500_INT_GPIO25R 49 /* not 8505 */
91#define AB8500_INT_GPIO37R 51 120#define AB8500_INT_GPIO36R 50 /* not 8505/9540 */
92#define AB8500_INT_GPIO38R 52 121#define AB8500_INT_GPIO37R 51 /* not 8505/9540 */
93#define AB8500_INT_GPIO39R 53 122#define AB8500_INT_GPIO38R 52 /* not 8505/9540 */
123#define AB8500_INT_GPIO39R 53 /* not 8505/9540 */
94#define AB8500_INT_GPIO40R 54 124#define AB8500_INT_GPIO40R 54
95#define AB8500_INT_GPIO41R 55 125#define AB8500_INT_GPIO41R 55
96#define AB8500_INT_GPIO6F 56 126/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
97#define AB8500_INT_GPIO7F 57 127#define AB8500_INT_GPIO6F 56 /* not 8505/9540 */
98#define AB8500_INT_GPIO8F 58 128#define AB8500_INT_GPIO7F 57 /* not 8505/9540 */
99#define AB8500_INT_GPIO9F 59 129#define AB8500_INT_GPIO8F 58 /* not 8505/9540 */
130#define AB8500_INT_GPIO9F 59 /* not 8505/9540 */
100#define AB8500_INT_GPIO10F 60 131#define AB8500_INT_GPIO10F 60
101#define AB8500_INT_GPIO11F 61 132#define AB8500_INT_GPIO11F 61
102#define AB8500_INT_GPIO12F 62 133#define AB8500_INT_GPIO12F 62 /* not 8505 */
103#define AB8500_INT_GPIO13F 63 134#define AB8500_INT_GPIO13F 63
104#define AB8500_INT_GPIO24F 64 135/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
105#define AB8500_INT_GPIO25F 65 136#define AB8500_INT_GPIO24F 64 /* not 8505 */
106#define AB8500_INT_GPIO36F 66 137#define AB8500_INT_GPIO25F 65 /* not 8505 */
107#define AB8500_INT_GPIO37F 67 138#define AB8500_INT_GPIO36F 66 /* not 8505/9540 */
108#define AB8500_INT_GPIO38F 68 139#define AB8500_INT_GPIO37F 67 /* not 8505/9540 */
109#define AB8500_INT_GPIO39F 69 140#define AB8500_INT_GPIO38F 68 /* not 8505/9540 */
141#define AB8500_INT_GPIO39F 69 /* not 8505/9540 */
110#define AB8500_INT_GPIO40F 70 142#define AB8500_INT_GPIO40F 70
111#define AB8500_INT_GPIO41F 71 143#define AB8500_INT_GPIO41F 71
144/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
112#define AB8500_INT_ADP_SOURCE_ERROR 72 145#define AB8500_INT_ADP_SOURCE_ERROR 72
113#define AB8500_INT_ADP_SINK_ERROR 73 146#define AB8500_INT_ADP_SINK_ERROR 73
114#define AB8500_INT_ADP_PROBE_PLUG 74 147#define AB8500_INT_ADP_PROBE_PLUG 74
@@ -116,30 +149,67 @@ struct device;
116#define AB8500_INT_ADP_SENSE_OFF 76 149#define AB8500_INT_ADP_SENSE_OFF 76
117#define AB8500_INT_USB_PHY_POWER_ERR 78 150#define AB8500_INT_USB_PHY_POWER_ERR 78
118#define AB8500_INT_USB_LINK_STATUS 79 151#define AB8500_INT_USB_LINK_STATUS 79
152/* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */
119#define AB8500_INT_BTEMP_LOW 80 153#define AB8500_INT_BTEMP_LOW 80
120#define AB8500_INT_BTEMP_LOW_MEDIUM 81 154#define AB8500_INT_BTEMP_LOW_MEDIUM 81
121#define AB8500_INT_BTEMP_MEDIUM_HIGH 82 155#define AB8500_INT_BTEMP_MEDIUM_HIGH 82
122#define AB8500_INT_BTEMP_HIGH 83 156#define AB8500_INT_BTEMP_HIGH 83
123#define AB8500_INT_USB_CHARGER_NOT_OK 89 157/* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */
158#define AB8500_INT_SRP_DETECT 88
159#define AB8500_INT_USB_CHARGER_NOT_OKR 89
124#define AB8500_INT_ID_WAKEUP_R 90 160#define AB8500_INT_ID_WAKEUP_R 90
125#define AB8500_INT_ID_DET_R1R 92 161#define AB8500_INT_ID_DET_R1R 92
126#define AB8500_INT_ID_DET_R2R 93 162#define AB8500_INT_ID_DET_R2R 93
127#define AB8500_INT_ID_DET_R3R 94 163#define AB8500_INT_ID_DET_R3R 94
128#define AB8500_INT_ID_DET_R4R 95 164#define AB8500_INT_ID_DET_R4R 95
165/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
129#define AB8500_INT_ID_WAKEUP_F 96 166#define AB8500_INT_ID_WAKEUP_F 96
130#define AB8500_INT_ID_DET_R1F 98 167#define AB8500_INT_ID_DET_R1F 98
131#define AB8500_INT_ID_DET_R2F 99 168#define AB8500_INT_ID_DET_R2F 99
132#define AB8500_INT_ID_DET_R3F 100 169#define AB8500_INT_ID_DET_R3F 100
133#define AB8500_INT_ID_DET_R4F 101 170#define AB8500_INT_ID_DET_R4F 101
134#define AB8500_INT_USB_CHG_DET_DONE 102 171#define AB8500_INT_CHAUTORESTARTAFTSEC 102
172#define AB8500_INT_CHSTOPBYSEC 103
173/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
135#define AB8500_INT_USB_CH_TH_PROT_F 104 174#define AB8500_INT_USB_CH_TH_PROT_F 104
136#define AB8500_INT_USB_CH_TH_PROT_R 105 175#define AB8500_INT_USB_CH_TH_PROT_R 105
137#define AB8500_INT_MAIN_CH_TH_PROT_F 106 176#define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */
138#define AB8500_INT_MAIN_CH_TH_PROT_R 107 177#define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */
139#define AB8500_INT_USB_CHARGER_NOT_OKF 111 178#define AB8500_INT_CHCURLIMNOHSCHIRP 109
179#define AB8500_INT_CHCURLIMHSCHIRP 110
180#define AB8500_INT_XTAL32K_KO 111
181
182/* Definitions for AB9540 */
183/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
184#define AB9540_INT_GPIO50R 113
185#define AB9540_INT_GPIO51R 114 /* not 8505 */
186#define AB9540_INT_GPIO52R 115
187#define AB9540_INT_GPIO53R 116
188#define AB9540_INT_GPIO54R 117 /* not 8505 */
189#define AB9540_INT_IEXT_CH_RF_BFN_R 118
190#define AB9540_INT_IEXT_CH_RF_BFN_F 119
191/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
192#define AB9540_INT_GPIO50F 121
193#define AB9540_INT_GPIO51F 122 /* not 8505 */
194#define AB9540_INT_GPIO52F 123
195#define AB9540_INT_GPIO53F 124
196#define AB9540_INT_GPIO54F 125 /* not 8505 */
140 197
198/*
199 * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
200 * entire platform. This is a "compile time" constant so this must be set to
201 * the largest possible value that may be encountered with different AB SOCs.
202 * Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
203 * which is larger.
204 */
141#define AB8500_NR_IRQS 112 205#define AB8500_NR_IRQS 112
206#define AB8505_NR_IRQS 128
207#define AB9540_NR_IRQS 128
208/* This is set to the roof of any AB8500 chip variant IRQ counts */
209#define AB8500_MAX_NR_IRQS AB9540_NR_IRQS
210
142#define AB8500_NUM_IRQ_REGS 14 211#define AB8500_NUM_IRQ_REGS 14
212#define AB9540_NUM_IRQ_REGS 17
143 213
144/** 214/**
145 * struct ab8500 - ab8500 internal structure 215 * struct ab8500 - ab8500 internal structure
@@ -147,13 +217,18 @@ struct device;
147 * @lock: read/write operations lock 217 * @lock: read/write operations lock
148 * @irq_lock: genirq bus lock 218 * @irq_lock: genirq bus lock
149 * @irq: irq line 219 * @irq: irq line
220 * @version: chip version id (e.g. ab8500 or ab9540)
150 * @chip_id: chip revision id 221 * @chip_id: chip revision id
151 * @write: register write 222 * @write: register write
223 * @write_masked: masked register write
152 * @read: register read 224 * @read: register read
153 * @rx_buf: rx buf for SPI 225 * @rx_buf: rx buf for SPI
154 * @tx_buf: tx buf for SPI 226 * @tx_buf: tx buf for SPI
155 * @mask: cache of IRQ regs for bus lock 227 * @mask: cache of IRQ regs for bus lock
156 * @oldmask: cache of previous IRQ regs for bus lock 228 * @oldmask: cache of previous IRQ regs for bus lock
229 * @mask_size: Actual number of valid entries in mask[], oldmask[] and
230 * irq_reg_offset
231 * @irq_reg_offset: Array of offsets into IRQ registers
157 */ 232 */
158struct ab8500 { 233struct ab8500 {
159 struct device *dev; 234 struct device *dev;
@@ -162,16 +237,20 @@ struct ab8500 {
162 237
163 int irq_base; 238 int irq_base;
164 int irq; 239 int irq;
240 enum ab8500_version version;
165 u8 chip_id; 241 u8 chip_id;
166 242
167 int (*write) (struct ab8500 *a8500, u16 addr, u8 data); 243 int (*write)(struct ab8500 *ab8500, u16 addr, u8 data);
168 int (*read) (struct ab8500 *a8500, u16 addr); 244 int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data);
245 int (*read)(struct ab8500 *ab8500, u16 addr);
169 246
170 unsigned long tx_buf[4]; 247 unsigned long tx_buf[4];
171 unsigned long rx_buf[4]; 248 unsigned long rx_buf[4];
172 249
173 u8 mask[AB8500_NUM_IRQ_REGS]; 250 u8 *mask;
174 u8 oldmask[AB8500_NUM_IRQ_REGS]; 251 u8 *oldmask;
252 int mask_size;
253 const int *irq_reg_offset;
175}; 254};
176 255
177struct regulator_reg_init; 256struct regulator_reg_init;
@@ -197,7 +276,52 @@ struct ab8500_platform_data {
197 struct ab8500_gpio_platform_data *gpio; 276 struct ab8500_gpio_platform_data *gpio;
198}; 277};
199 278
200extern int __devinit ab8500_init(struct ab8500 *ab8500); 279extern int __devinit ab8500_init(struct ab8500 *ab8500,
280 enum ab8500_version version);
201extern int __devexit ab8500_exit(struct ab8500 *ab8500); 281extern int __devexit ab8500_exit(struct ab8500 *ab8500);
202 282
283static inline int is_ab8500(struct ab8500 *ab)
284{
285 return ab->version == AB8500_VERSION_AB8500;
286}
287
288static inline int is_ab8505(struct ab8500 *ab)
289{
290 return ab->version == AB8500_VERSION_AB8505;
291}
292
293static inline int is_ab9540(struct ab8500 *ab)
294{
295 return ab->version == AB8500_VERSION_AB9540;
296}
297
298static inline int is_ab8540(struct ab8500 *ab)
299{
300 return ab->version == AB8500_VERSION_AB8540;
301}
302
303/* exclude also ab8505, ab9540... */
304static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab)
305{
306 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0));
307}
308
309/* exclude also ab8505, ab9540... */
310static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab)
311{
312 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1));
313}
314
315/* exclude also ab8505, ab9540... */
316static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab)
317{
318 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0));
319}
320
321/* exclude also ab8505, ab9540... */
322static inline int is_ab8500_2p0(struct ab8500 *ab)
323{
324 return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
325}
326
203#endif /* MFD_AB8500_H */ 327#endif /* MFD_AB8500_H */
diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
new file mode 100644
index 000000000000..22c1007d3ec5
--- /dev/null
+++ b/include/linux/mfd/anatop.h
@@ -0,0 +1,40 @@
1/*
2 * anatop.h - Anatop MFD driver
3 *
4 * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
5 * Copyright (C) 2012 Linaro
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef __LINUX_MFD_ANATOP_H
23#define __LINUX_MFD_ANATOP_H
24
25#include <linux/spinlock.h>
26
27/**
28 * anatop - MFD data
29 * @ioreg: ioremap register
30 * @reglock: spinlock for register read/write
31 */
32struct anatop {
33 void *ioreg;
34 spinlock_t reglock;
35};
36
37extern u32 anatop_get_bits(struct anatop *, u32, int, int);
38extern void anatop_set_bits(struct anatop *, u32, int, int, u32);
39
40#endif /* __LINUX_MFD_ANATOP_H */
diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h
index 5702d1be13b4..7ffbd6e9e7fc 100644
--- a/include/linux/mfd/da9052/da9052.h
+++ b/include/linux/mfd/da9052/da9052.h
@@ -76,8 +76,6 @@ enum da9052_chip_id {
76struct da9052_pdata; 76struct da9052_pdata;
77 77
78struct da9052 { 78struct da9052 {
79 struct mutex io_lock;
80
81 struct device *dev; 79 struct device *dev;
82 struct regmap *regmap; 80 struct regmap *regmap;
83 81
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
index 60d27f7bfc1f..b3a43b1263fe 100644
--- a/include/linux/mfd/db8500-prcmu.h
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -11,6 +11,24 @@
11#define __MFD_DB8500_PRCMU_H 11#define __MFD_DB8500_PRCMU_H
12 12
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14#include <linux/bitops.h>
15
16/*
17 * Registers
18 */
19#define DB8500_PRCM_GPIOCR 0x138
20#define DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0 BIT(0)
21#define DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD BIT(9)
22#define DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 BIT(11)
23#define DB8500_PRCM_GPIOCR_SPI2_SELECT BIT(23)
24
25#define DB8500_PRCM_LINE_VALUE 0x170
26#define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3)
27
28#define DB8500_PRCM_DSI_SW_RESET 0x324
29#define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
30#define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
31#define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
14 32
15/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */ 33/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
16 34
@@ -421,40 +439,22 @@ enum auto_enable {
421/* End of file previously known as prcmu-fw-defs_v1.h */ 439/* End of file previously known as prcmu-fw-defs_v1.h */
422 440
423/** 441/**
424 * enum hw_acc_dev - enum for hw accelerators 442 * enum prcmu_power_status - results from set_power_state
425 * @HW_ACC_SVAMMDSP: for SVAMMDSP 443 * @PRCMU_SLEEP_OK: Sleep went ok
426 * @HW_ACC_SVAPIPE: for SVAPIPE 444 * @PRCMU_DEEP_SLEEP_OK: DeepSleep went ok
427 * @HW_ACC_SIAMMDSP: for SIAMMDSP 445 * @PRCMU_IDLE_OK: Idle went ok
428 * @HW_ACC_SIAPIPE: for SIAPIPE 446 * @PRCMU_DEEPIDLE_OK: DeepIdle went ok
429 * @HW_ACC_SGA: for SGA 447 * @PRCMU_PRCMU2ARMPENDINGIT_ER: Pending interrupt detected
430 * @HW_ACC_B2R2: for B2R2 448 * @PRCMU_ARMPENDINGIT_ER: Pending interrupt detected
431 * @HW_ACC_MCDE: for MCDE
432 * @HW_ACC_ESRAM1: for ESRAM1
433 * @HW_ACC_ESRAM2: for ESRAM2
434 * @HW_ACC_ESRAM3: for ESRAM3
435 * @HW_ACC_ESRAM4: for ESRAM4
436 * @NUM_HW_ACC: number of hardware accelerators
437 *
438 * Different hw accelerators which can be turned ON/
439 * OFF or put into retention (MMDSPs and ESRAMs).
440 * Used with EPOD API.
441 * 449 *
442 * NOTE! Deprecated, to be removed when all users switched over to use the
443 * regulator API.
444 */ 450 */
445enum hw_acc_dev { 451enum prcmu_power_status {
446 HW_ACC_SVAMMDSP, 452 PRCMU_SLEEP_OK = 0xf3,
447 HW_ACC_SVAPIPE, 453 PRCMU_DEEP_SLEEP_OK = 0xf6,
448 HW_ACC_SIAMMDSP, 454 PRCMU_IDLE_OK = 0xf0,
449 HW_ACC_SIAPIPE, 455 PRCMU_DEEPIDLE_OK = 0xe3,
450 HW_ACC_SGA, 456 PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91,
451 HW_ACC_B2R2, 457 PRCMU_ARMPENDINGIT_ER = 0x93,
452 HW_ACC_MCDE,
453 HW_ACC_ESRAM1,
454 HW_ACC_ESRAM2,
455 HW_ACC_ESRAM3,
456 HW_ACC_ESRAM4,
457 NUM_HW_ACC
458}; 458};
459 459
460/* 460/*
@@ -493,6 +493,20 @@ struct prcmu_auto_pm_config {
493 u8 sva_policy; 493 u8 sva_policy;
494}; 494};
495 495
496#define PRCMU_FW_PROJECT_U8500 2
497#define PRCMU_FW_PROJECT_U9500 4
498#define PRCMU_FW_PROJECT_U8500_C2 7
499#define PRCMU_FW_PROJECT_U9500_C2 11
500#define PRCMU_FW_PROJECT_U8520 13
501#define PRCMU_FW_PROJECT_U8420 14
502
503struct prcmu_fw_version {
504 u8 project;
505 u8 api_version;
506 u8 func_version;
507 u8 errata;
508};
509
496#ifdef CONFIG_MFD_DB8500_PRCMU 510#ifdef CONFIG_MFD_DB8500_PRCMU
497 511
498void db8500_prcmu_early_init(void); 512void db8500_prcmu_early_init(void);
@@ -500,42 +514,41 @@ int prcmu_set_rc_a2p(enum romcode_write);
500enum romcode_read prcmu_get_rc_p2a(void); 514enum romcode_read prcmu_get_rc_p2a(void);
501enum ap_pwrst prcmu_get_xp70_current_state(void); 515enum ap_pwrst prcmu_get_xp70_current_state(void);
502bool prcmu_has_arm_maxopp(void); 516bool prcmu_has_arm_maxopp(void);
503bool prcmu_is_u8400(void); 517struct prcmu_fw_version *prcmu_get_fw_version(void);
504int prcmu_set_ape_opp(u8 opp);
505int prcmu_get_ape_opp(void);
506int prcmu_request_ape_opp_100_voltage(bool enable); 518int prcmu_request_ape_opp_100_voltage(bool enable);
507int prcmu_release_usb_wakeup_state(void); 519int prcmu_release_usb_wakeup_state(void);
508int prcmu_set_ddr_opp(u8 opp);
509int prcmu_get_ddr_opp(void);
510/* NOTE! Use regulator framework instead */
511int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
512void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 520void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
513 struct prcmu_auto_pm_config *idle); 521 struct prcmu_auto_pm_config *idle);
514bool prcmu_is_auto_pm_enabled(void); 522bool prcmu_is_auto_pm_enabled(void);
515 523
516int prcmu_config_clkout(u8 clkout, u8 source, u8 div); 524int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
517int prcmu_set_clock_divider(u8 clock, u8 divider); 525int prcmu_set_clock_divider(u8 clock, u8 divider);
518int prcmu_config_hotdog(u8 threshold); 526int db8500_prcmu_config_hotdog(u8 threshold);
519int prcmu_config_hotmon(u8 low, u8 high); 527int db8500_prcmu_config_hotmon(u8 low, u8 high);
520int prcmu_start_temp_sense(u16 cycles32k); 528int db8500_prcmu_start_temp_sense(u16 cycles32k);
521int prcmu_stop_temp_sense(void); 529int db8500_prcmu_stop_temp_sense(void);
522int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); 530int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
523int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); 531int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
524 532
525void prcmu_ac_wake_req(void); 533void prcmu_ac_wake_req(void);
526void prcmu_ac_sleep_req(void); 534void prcmu_ac_sleep_req(void);
527void prcmu_modem_reset(void); 535void db8500_prcmu_modem_reset(void);
528void prcmu_enable_spi2(void);
529void prcmu_disable_spi2(void);
530 536
531int prcmu_config_a9wdog(u8 num, bool sleep_auto_off); 537int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
532int prcmu_enable_a9wdog(u8 id); 538int db8500_prcmu_enable_a9wdog(u8 id);
533int prcmu_disable_a9wdog(u8 id); 539int db8500_prcmu_disable_a9wdog(u8 id);
534int prcmu_kick_a9wdog(u8 id); 540int db8500_prcmu_kick_a9wdog(u8 id);
535int prcmu_load_a9wdog(u8 id, u32 val); 541int db8500_prcmu_load_a9wdog(u8 id, u32 val);
536 542
537void db8500_prcmu_system_reset(u16 reset_code); 543void db8500_prcmu_system_reset(u16 reset_code);
538int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll); 544int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
545u8 db8500_prcmu_get_power_state_result(void);
546int db8500_prcmu_gic_decouple(void);
547int db8500_prcmu_gic_recouple(void);
548int db8500_prcmu_copy_gic_settings(void);
549bool db8500_prcmu_gic_pending_irq(void);
550bool db8500_prcmu_pending_irq(void);
551bool db8500_prcmu_is_cpu_in_wfi(int cpu);
539void db8500_prcmu_enable_wakeups(u32 wakeups); 552void db8500_prcmu_enable_wakeups(u32 wakeups);
540int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state); 553int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
541int db8500_prcmu_request_clock(u8 clock, bool enable); 554int db8500_prcmu_request_clock(u8 clock, bool enable);
@@ -549,6 +562,14 @@ u16 db8500_prcmu_get_reset_code(void);
549bool db8500_prcmu_is_ac_wake_requested(void); 562bool db8500_prcmu_is_ac_wake_requested(void);
550int db8500_prcmu_set_arm_opp(u8 opp); 563int db8500_prcmu_set_arm_opp(u8 opp);
551int db8500_prcmu_get_arm_opp(void); 564int db8500_prcmu_get_arm_opp(void);
565int db8500_prcmu_set_ape_opp(u8 opp);
566int db8500_prcmu_get_ape_opp(void);
567int db8500_prcmu_set_ddr_opp(u8 opp);
568int db8500_prcmu_get_ddr_opp(void);
569
570u32 db8500_prcmu_read(unsigned int reg);
571void db8500_prcmu_write(unsigned int reg, u32 value);
572void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
552 573
553#else /* !CONFIG_MFD_DB8500_PRCMU */ 574#else /* !CONFIG_MFD_DB8500_PRCMU */
554 575
@@ -574,17 +595,17 @@ static inline bool prcmu_has_arm_maxopp(void)
574 return false; 595 return false;
575} 596}
576 597
577static inline bool prcmu_is_u8400(void) 598static inline struct prcmu_fw_version *prcmu_get_fw_version(void)
578{ 599{
579 return false; 600 return NULL;
580} 601}
581 602
582static inline int prcmu_set_ape_opp(u8 opp) 603static inline int db8500_prcmu_set_ape_opp(u8 opp)
583{ 604{
584 return 0; 605 return 0;
585} 606}
586 607
587static inline int prcmu_get_ape_opp(void) 608static inline int db8500_prcmu_get_ape_opp(void)
588{ 609{
589 return APE_100_OPP; 610 return APE_100_OPP;
590} 611}
@@ -599,21 +620,16 @@ static inline int prcmu_release_usb_wakeup_state(void)
599 return 0; 620 return 0;
600} 621}
601 622
602static inline int prcmu_set_ddr_opp(u8 opp) 623static inline int db8500_prcmu_set_ddr_opp(u8 opp)
603{ 624{
604 return 0; 625 return 0;
605} 626}
606 627
607static inline int prcmu_get_ddr_opp(void) 628static inline int db8500_prcmu_get_ddr_opp(void)
608{ 629{
609 return DDR_100_OPP; 630 return DDR_100_OPP;
610} 631}
611 632
612static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
613{
614 return 0;
615}
616
617static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 633static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
618 struct prcmu_auto_pm_config *idle) 634 struct prcmu_auto_pm_config *idle)
619{ 635{
@@ -634,22 +650,22 @@ static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
634 return 0; 650 return 0;
635} 651}
636 652
637static inline int prcmu_config_hotdog(u8 threshold) 653static inline int db8500_prcmu_config_hotdog(u8 threshold)
638{ 654{
639 return 0; 655 return 0;
640} 656}
641 657
642static inline int prcmu_config_hotmon(u8 low, u8 high) 658static inline int db8500_prcmu_config_hotmon(u8 low, u8 high)
643{ 659{
644 return 0; 660 return 0;
645} 661}
646 662
647static inline int prcmu_start_temp_sense(u16 cycles32k) 663static inline int db8500_prcmu_start_temp_sense(u16 cycles32k)
648{ 664{
649 return 0; 665 return 0;
650} 666}
651 667
652static inline int prcmu_stop_temp_sense(void) 668static inline int db8500_prcmu_stop_temp_sense(void)
653{ 669{
654 return 0; 670 return 0;
655} 671}
@@ -668,22 +684,17 @@ static inline void prcmu_ac_wake_req(void) {}
668 684
669static inline void prcmu_ac_sleep_req(void) {} 685static inline void prcmu_ac_sleep_req(void) {}
670 686
671static inline void prcmu_modem_reset(void) {} 687static inline void db8500_prcmu_modem_reset(void) {}
672 688
673static inline int prcmu_enable_spi2(void) 689static inline void db8500_prcmu_system_reset(u16 reset_code) {}
674{
675 return 0;
676}
677 690
678static inline int prcmu_disable_spi2(void) 691static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
692 bool keep_ap_pll)
679{ 693{
680 return 0; 694 return 0;
681} 695}
682 696
683static inline void db8500_prcmu_system_reset(u16 reset_code) {} 697static inline u8 db8500_prcmu_get_power_state_result(void)
684
685static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
686 bool keep_ap_pll)
687{ 698{
688 return 0; 699 return 0;
689} 700}
@@ -729,27 +740,27 @@ static inline u16 db8500_prcmu_get_reset_code(void)
729 return 0; 740 return 0;
730} 741}
731 742
732static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 743static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
733{ 744{
734 return 0; 745 return 0;
735} 746}
736 747
737static inline int prcmu_enable_a9wdog(u8 id) 748static inline int db8500_prcmu_enable_a9wdog(u8 id)
738{ 749{
739 return 0; 750 return 0;
740} 751}
741 752
742static inline int prcmu_disable_a9wdog(u8 id) 753static inline int db8500_prcmu_disable_a9wdog(u8 id)
743{ 754{
744 return 0; 755 return 0;
745} 756}
746 757
747static inline int prcmu_kick_a9wdog(u8 id) 758static inline int db8500_prcmu_kick_a9wdog(u8 id)
748{ 759{
749 return 0; 760 return 0;
750} 761}
751 762
752static inline int prcmu_load_a9wdog(u8 id, u32 val) 763static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val)
753{ 764{
754 return 0; 765 return 0;
755} 766}
@@ -769,6 +780,16 @@ static inline int db8500_prcmu_get_arm_opp(void)
769 return 0; 780 return 0;
770} 781}
771 782
783static inline u32 db8500_prcmu_read(unsigned int reg)
784{
785 return 0;
786}
787
788static inline void db8500_prcmu_write(unsigned int reg, u32 value) {}
789
790static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask,
791 u32 value) {}
792
772#endif /* !CONFIG_MFD_DB8500_PRCMU */ 793#endif /* !CONFIG_MFD_DB8500_PRCMU */
773 794
774#endif /* __MFD_DB8500_PRCMU_H */ 795#endif /* __MFD_DB8500_PRCMU_H */
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index bac942f959c1..d7674eb7305f 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -10,7 +10,7 @@
10 10
11#include <linux/interrupt.h> 11#include <linux/interrupt.h>
12#include <linux/notifier.h> 12#include <linux/notifier.h>
13#include <asm/mach-types.h> 13#include <linux/err.h>
14 14
15/* PRCMU Wakeup defines */ 15/* PRCMU Wakeup defines */
16enum prcmu_wakeup_index { 16enum prcmu_wakeup_index {
@@ -80,6 +80,29 @@ enum prcmu_wakeup_index {
80#define EPOD_STATE_ON_CLK_OFF 0x03 80#define EPOD_STATE_ON_CLK_OFF 0x03
81#define EPOD_STATE_ON 0x04 81#define EPOD_STATE_ON 0x04
82 82
83/* DB5500 CLKOUT IDs */
84enum {
85 DB5500_CLKOUT0 = 0,
86 DB5500_CLKOUT1,
87};
88
89/* DB5500 CLKOUTx sources */
90enum {
91 DB5500_CLKOUT_REF_CLK_SEL0,
92 DB5500_CLKOUT_RTC_CLK0_SEL0,
93 DB5500_CLKOUT_ULP_CLK_SEL0,
94 DB5500_CLKOUT_STATIC0,
95 DB5500_CLKOUT_REFCLK,
96 DB5500_CLKOUT_ULPCLK,
97 DB5500_CLKOUT_ARMCLK,
98 DB5500_CLKOUT_SYSACC0CLK,
99 DB5500_CLKOUT_SOC0PLLCLK,
100 DB5500_CLKOUT_SOC1PLLCLK,
101 DB5500_CLKOUT_DDRPLLCLK,
102 DB5500_CLKOUT_TVCLK,
103 DB5500_CLKOUT_IRDACLK,
104};
105
83/* 106/*
84 * CLKOUT sources 107 * CLKOUT sources
85 */ 108 */
@@ -111,6 +134,7 @@ enum prcmu_clock {
111 PRCMU_MSP1CLK, 134 PRCMU_MSP1CLK,
112 PRCMU_I2CCLK, 135 PRCMU_I2CCLK,
113 PRCMU_SDMMCCLK, 136 PRCMU_SDMMCCLK,
137 PRCMU_SPARE1CLK,
114 PRCMU_SLIMCLK, 138 PRCMU_SLIMCLK,
115 PRCMU_PER1CLK, 139 PRCMU_PER1CLK,
116 PRCMU_PER2CLK, 140 PRCMU_PER2CLK,
@@ -139,12 +163,20 @@ enum prcmu_clock {
139 PRCMU_IRRCCLK, 163 PRCMU_IRRCCLK,
140 PRCMU_SIACLK, 164 PRCMU_SIACLK,
141 PRCMU_SVACLK, 165 PRCMU_SVACLK,
166 PRCMU_ACLK,
142 PRCMU_NUM_REG_CLOCKS, 167 PRCMU_NUM_REG_CLOCKS,
143 PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS, 168 PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
169 PRCMU_CDCLK,
144 PRCMU_TIMCLK, 170 PRCMU_TIMCLK,
145 PRCMU_PLLSOC0, 171 PRCMU_PLLSOC0,
146 PRCMU_PLLSOC1, 172 PRCMU_PLLSOC1,
147 PRCMU_PLLDDR, 173 PRCMU_PLLDDR,
174 PRCMU_PLLDSI,
175 PRCMU_DSI0CLK,
176 PRCMU_DSI1CLK,
177 PRCMU_DSI0ESCCLK,
178 PRCMU_DSI1ESCCLK,
179 PRCMU_DSI2ESCCLK,
148}; 180};
149 181
150/** 182/**
@@ -153,12 +185,14 @@ enum prcmu_clock {
153 * @APE_NO_CHANGE: The APE operating point is unchanged 185 * @APE_NO_CHANGE: The APE operating point is unchanged
154 * @APE_100_OPP: The new APE operating point is ape100opp 186 * @APE_100_OPP: The new APE operating point is ape100opp
155 * @APE_50_OPP: 50% 187 * @APE_50_OPP: 50%
188 * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
156 */ 189 */
157enum ape_opp { 190enum ape_opp {
158 APE_OPP_INIT = 0x00, 191 APE_OPP_INIT = 0x00,
159 APE_NO_CHANGE = 0x01, 192 APE_NO_CHANGE = 0x01,
160 APE_100_OPP = 0x02, 193 APE_100_OPP = 0x02,
161 APE_50_OPP = 0x03 194 APE_50_OPP = 0x03,
195 APE_50_PARTLY_25_OPP = 0xFF,
162}; 196};
163 197
164/** 198/**
@@ -218,9 +252,11 @@ enum ddr_pwrst {
218 252
219#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) 253#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
220 254
255#include <mach/id.h>
256
221static inline void __init prcmu_early_init(void) 257static inline void __init prcmu_early_init(void)
222{ 258{
223 if (machine_is_u5500()) 259 if (cpu_is_u5500())
224 return db5500_prcmu_early_init(); 260 return db5500_prcmu_early_init();
225 else 261 else
226 return db8500_prcmu_early_init(); 262 return db8500_prcmu_early_init();
@@ -229,7 +265,7 @@ static inline void __init prcmu_early_init(void)
229static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 265static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
230 bool keep_ap_pll) 266 bool keep_ap_pll)
231{ 267{
232 if (machine_is_u5500()) 268 if (cpu_is_u5500())
233 return db5500_prcmu_set_power_state(state, keep_ulp_clk, 269 return db5500_prcmu_set_power_state(state, keep_ulp_clk,
234 keep_ap_pll); 270 keep_ap_pll);
235 else 271 else
@@ -237,9 +273,65 @@ static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
237 keep_ap_pll); 273 keep_ap_pll);
238} 274}
239 275
276static inline u8 prcmu_get_power_state_result(void)
277{
278 if (cpu_is_u5500())
279 return -EINVAL;
280 else
281 return db8500_prcmu_get_power_state_result();
282}
283
284static inline int prcmu_gic_decouple(void)
285{
286 if (cpu_is_u5500())
287 return -EINVAL;
288 else
289 return db8500_prcmu_gic_decouple();
290}
291
292static inline int prcmu_gic_recouple(void)
293{
294 if (cpu_is_u5500())
295 return -EINVAL;
296 else
297 return db8500_prcmu_gic_recouple();
298}
299
300static inline bool prcmu_gic_pending_irq(void)
301{
302 if (cpu_is_u5500())
303 return -EINVAL;
304 else
305 return db8500_prcmu_gic_pending_irq();
306}
307
308static inline bool prcmu_is_cpu_in_wfi(int cpu)
309{
310 if (cpu_is_u5500())
311 return -EINVAL;
312 else
313 return db8500_prcmu_is_cpu_in_wfi(cpu);
314}
315
316static inline int prcmu_copy_gic_settings(void)
317{
318 if (cpu_is_u5500())
319 return -EINVAL;
320 else
321 return db8500_prcmu_copy_gic_settings();
322}
323
324static inline bool prcmu_pending_irq(void)
325{
326 if (cpu_is_u5500())
327 return -EINVAL;
328 else
329 return db8500_prcmu_pending_irq();
330}
331
240static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) 332static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
241{ 333{
242 if (machine_is_u5500()) 334 if (cpu_is_u5500())
243 return -EINVAL; 335 return -EINVAL;
244 else 336 else
245 return db8500_prcmu_set_epod(epod_id, epod_state); 337 return db8500_prcmu_set_epod(epod_id, epod_state);
@@ -247,7 +339,7 @@ static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
247 339
248static inline void prcmu_enable_wakeups(u32 wakeups) 340static inline void prcmu_enable_wakeups(u32 wakeups)
249{ 341{
250 if (machine_is_u5500()) 342 if (cpu_is_u5500())
251 db5500_prcmu_enable_wakeups(wakeups); 343 db5500_prcmu_enable_wakeups(wakeups);
252 else 344 else
253 db8500_prcmu_enable_wakeups(wakeups); 345 db8500_prcmu_enable_wakeups(wakeups);
@@ -260,7 +352,7 @@ static inline void prcmu_disable_wakeups(void)
260 352
261static inline void prcmu_config_abb_event_readout(u32 abb_events) 353static inline void prcmu_config_abb_event_readout(u32 abb_events)
262{ 354{
263 if (machine_is_u5500()) 355 if (cpu_is_u5500())
264 db5500_prcmu_config_abb_event_readout(abb_events); 356 db5500_prcmu_config_abb_event_readout(abb_events);
265 else 357 else
266 db8500_prcmu_config_abb_event_readout(abb_events); 358 db8500_prcmu_config_abb_event_readout(abb_events);
@@ -268,7 +360,7 @@ static inline void prcmu_config_abb_event_readout(u32 abb_events)
268 360
269static inline void prcmu_get_abb_event_buffer(void __iomem **buf) 361static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
270{ 362{
271 if (machine_is_u5500()) 363 if (cpu_is_u5500())
272 db5500_prcmu_get_abb_event_buffer(buf); 364 db5500_prcmu_get_abb_event_buffer(buf);
273 else 365 else
274 db8500_prcmu_get_abb_event_buffer(buf); 366 db8500_prcmu_get_abb_event_buffer(buf);
@@ -276,25 +368,40 @@ static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
276 368
277int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); 369int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
278int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); 370int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
371int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
279 372
280int prcmu_config_clkout(u8 clkout, u8 source, u8 div); 373int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
281 374
282static inline int prcmu_request_clock(u8 clock, bool enable) 375static inline int prcmu_request_clock(u8 clock, bool enable)
283{ 376{
284 if (machine_is_u5500()) 377 if (cpu_is_u5500())
285 return db5500_prcmu_request_clock(clock, enable); 378 return db5500_prcmu_request_clock(clock, enable);
286 else 379 else
287 return db8500_prcmu_request_clock(clock, enable); 380 return db8500_prcmu_request_clock(clock, enable);
288} 381}
289 382
290int prcmu_set_ape_opp(u8 opp); 383unsigned long prcmu_clock_rate(u8 clock);
291int prcmu_get_ape_opp(void); 384long prcmu_round_clock_rate(u8 clock, unsigned long rate);
292int prcmu_set_ddr_opp(u8 opp); 385int prcmu_set_clock_rate(u8 clock, unsigned long rate);
293int prcmu_get_ddr_opp(void); 386
387static inline int prcmu_set_ddr_opp(u8 opp)
388{
389 if (cpu_is_u5500())
390 return -EINVAL;
391 else
392 return db8500_prcmu_set_ddr_opp(opp);
393}
394static inline int prcmu_get_ddr_opp(void)
395{
396 if (cpu_is_u5500())
397 return -EINVAL;
398 else
399 return db8500_prcmu_get_ddr_opp();
400}
294 401
295static inline int prcmu_set_arm_opp(u8 opp) 402static inline int prcmu_set_arm_opp(u8 opp)
296{ 403{
297 if (machine_is_u5500()) 404 if (cpu_is_u5500())
298 return -EINVAL; 405 return -EINVAL;
299 else 406 else
300 return db8500_prcmu_set_arm_opp(opp); 407 return db8500_prcmu_set_arm_opp(opp);
@@ -302,15 +409,31 @@ static inline int prcmu_set_arm_opp(u8 opp)
302 409
303static inline int prcmu_get_arm_opp(void) 410static inline int prcmu_get_arm_opp(void)
304{ 411{
305 if (machine_is_u5500()) 412 if (cpu_is_u5500())
306 return -EINVAL; 413 return -EINVAL;
307 else 414 else
308 return db8500_prcmu_get_arm_opp(); 415 return db8500_prcmu_get_arm_opp();
309} 416}
310 417
418static inline int prcmu_set_ape_opp(u8 opp)
419{
420 if (cpu_is_u5500())
421 return -EINVAL;
422 else
423 return db8500_prcmu_set_ape_opp(opp);
424}
425
426static inline int prcmu_get_ape_opp(void)
427{
428 if (cpu_is_u5500())
429 return -EINVAL;
430 else
431 return db8500_prcmu_get_ape_opp();
432}
433
311static inline void prcmu_system_reset(u16 reset_code) 434static inline void prcmu_system_reset(u16 reset_code)
312{ 435{
313 if (machine_is_u5500()) 436 if (cpu_is_u5500())
314 return db5500_prcmu_system_reset(reset_code); 437 return db5500_prcmu_system_reset(reset_code);
315 else 438 else
316 return db8500_prcmu_system_reset(reset_code); 439 return db8500_prcmu_system_reset(reset_code);
@@ -318,7 +441,7 @@ static inline void prcmu_system_reset(u16 reset_code)
318 441
319static inline u16 prcmu_get_reset_code(void) 442static inline u16 prcmu_get_reset_code(void)
320{ 443{
321 if (machine_is_u5500()) 444 if (cpu_is_u5500())
322 return db5500_prcmu_get_reset_code(); 445 return db5500_prcmu_get_reset_code();
323 else 446 else
324 return db8500_prcmu_get_reset_code(); 447 return db8500_prcmu_get_reset_code();
@@ -326,10 +449,17 @@ static inline u16 prcmu_get_reset_code(void)
326 449
327void prcmu_ac_wake_req(void); 450void prcmu_ac_wake_req(void);
328void prcmu_ac_sleep_req(void); 451void prcmu_ac_sleep_req(void);
329void prcmu_modem_reset(void); 452static inline void prcmu_modem_reset(void)
453{
454 if (cpu_is_u5500())
455 return;
456 else
457 return db8500_prcmu_modem_reset();
458}
459
330static inline bool prcmu_is_ac_wake_requested(void) 460static inline bool prcmu_is_ac_wake_requested(void)
331{ 461{
332 if (machine_is_u5500()) 462 if (cpu_is_u5500())
333 return db5500_prcmu_is_ac_wake_requested(); 463 return db5500_prcmu_is_ac_wake_requested();
334 else 464 else
335 return db8500_prcmu_is_ac_wake_requested(); 465 return db8500_prcmu_is_ac_wake_requested();
@@ -337,7 +467,7 @@ static inline bool prcmu_is_ac_wake_requested(void)
337 467
338static inline int prcmu_set_display_clocks(void) 468static inline int prcmu_set_display_clocks(void)
339{ 469{
340 if (machine_is_u5500()) 470 if (cpu_is_u5500())
341 return db5500_prcmu_set_display_clocks(); 471 return db5500_prcmu_set_display_clocks();
342 else 472 else
343 return db8500_prcmu_set_display_clocks(); 473 return db8500_prcmu_set_display_clocks();
@@ -345,7 +475,7 @@ static inline int prcmu_set_display_clocks(void)
345 475
346static inline int prcmu_disable_dsipll(void) 476static inline int prcmu_disable_dsipll(void)
347{ 477{
348 if (machine_is_u5500()) 478 if (cpu_is_u5500())
349 return db5500_prcmu_disable_dsipll(); 479 return db5500_prcmu_disable_dsipll();
350 else 480 else
351 return db8500_prcmu_disable_dsipll(); 481 return db8500_prcmu_disable_dsipll();
@@ -353,7 +483,7 @@ static inline int prcmu_disable_dsipll(void)
353 483
354static inline int prcmu_enable_dsipll(void) 484static inline int prcmu_enable_dsipll(void)
355{ 485{
356 if (machine_is_u5500()) 486 if (cpu_is_u5500())
357 return db5500_prcmu_enable_dsipll(); 487 return db5500_prcmu_enable_dsipll();
358 else 488 else
359 return db8500_prcmu_enable_dsipll(); 489 return db8500_prcmu_enable_dsipll();
@@ -361,11 +491,107 @@ static inline int prcmu_enable_dsipll(void)
361 491
362static inline int prcmu_config_esram0_deep_sleep(u8 state) 492static inline int prcmu_config_esram0_deep_sleep(u8 state)
363{ 493{
364 if (machine_is_u5500()) 494 if (cpu_is_u5500())
365 return -EINVAL; 495 return -EINVAL;
366 else 496 else
367 return db8500_prcmu_config_esram0_deep_sleep(state); 497 return db8500_prcmu_config_esram0_deep_sleep(state);
368} 498}
499
500static inline int prcmu_config_hotdog(u8 threshold)
501{
502 if (cpu_is_u5500())
503 return -EINVAL;
504 else
505 return db8500_prcmu_config_hotdog(threshold);
506}
507
508static inline int prcmu_config_hotmon(u8 low, u8 high)
509{
510 if (cpu_is_u5500())
511 return -EINVAL;
512 else
513 return db8500_prcmu_config_hotmon(low, high);
514}
515
516static inline int prcmu_start_temp_sense(u16 cycles32k)
517{
518 if (cpu_is_u5500())
519 return -EINVAL;
520 else
521 return db8500_prcmu_start_temp_sense(cycles32k);
522}
523
524static inline int prcmu_stop_temp_sense(void)
525{
526 if (cpu_is_u5500())
527 return -EINVAL;
528 else
529 return db8500_prcmu_stop_temp_sense();
530}
531
532static inline u32 prcmu_read(unsigned int reg)
533{
534 if (cpu_is_u5500())
535 return -EINVAL;
536 else
537 return db8500_prcmu_read(reg);
538}
539
540static inline void prcmu_write(unsigned int reg, u32 value)
541{
542 if (cpu_is_u5500())
543 return;
544 else
545 db8500_prcmu_write(reg, value);
546}
547
548static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
549{
550 if (cpu_is_u5500())
551 return;
552 else
553 db8500_prcmu_write_masked(reg, mask, value);
554}
555
556static inline int prcmu_enable_a9wdog(u8 id)
557{
558 if (cpu_is_u5500())
559 return -EINVAL;
560 else
561 return db8500_prcmu_enable_a9wdog(id);
562}
563
564static inline int prcmu_disable_a9wdog(u8 id)
565{
566 if (cpu_is_u5500())
567 return -EINVAL;
568 else
569 return db8500_prcmu_disable_a9wdog(id);
570}
571
572static inline int prcmu_kick_a9wdog(u8 id)
573{
574 if (cpu_is_u5500())
575 return -EINVAL;
576 else
577 return db8500_prcmu_kick_a9wdog(id);
578}
579
580static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
581{
582 if (cpu_is_u5500())
583 return -EINVAL;
584 else
585 return db8500_prcmu_load_a9wdog(id, timeout);
586}
587
588static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
589{
590 if (cpu_is_u5500())
591 return -EINVAL;
592 else
593 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
594}
369#else 595#else
370 596
371static inline void __init prcmu_early_init(void) {} 597static inline void __init prcmu_early_init(void) {}
@@ -395,6 +621,12 @@ static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
395 return -ENOSYS; 621 return -ENOSYS;
396} 622}
397 623
624static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
625 u8 size)
626{
627 return -ENOSYS;
628}
629
398static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) 630static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
399{ 631{
400 return 0; 632 return 0;
@@ -405,6 +637,21 @@ static inline int prcmu_request_clock(u8 clock, bool enable)
405 return 0; 637 return 0;
406} 638}
407 639
640static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
641{
642 return 0;
643}
644
645static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
646{
647 return 0;
648}
649
650static inline unsigned long prcmu_clock_rate(u8 clock)
651{
652 return 0;
653}
654
408static inline int prcmu_set_ape_opp(u8 opp) 655static inline int prcmu_set_ape_opp(u8 opp)
409{ 656{
410 return 0; 657 return 0;
@@ -480,14 +727,133 @@ static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
480 *buf = NULL; 727 *buf = NULL;
481} 728}
482 729
730static inline int prcmu_config_hotdog(u8 threshold)
731{
732 return 0;
733}
734
735static inline int prcmu_config_hotmon(u8 low, u8 high)
736{
737 return 0;
738}
739
740static inline int prcmu_start_temp_sense(u16 cycles32k)
741{
742 return 0;
743}
744
745static inline int prcmu_stop_temp_sense(void)
746{
747 return 0;
748}
749
750static inline u32 prcmu_read(unsigned int reg)
751{
752 return 0;
753}
754
755static inline void prcmu_write(unsigned int reg, u32 value) {}
756
757static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
758
759#endif
760
761static inline void prcmu_set(unsigned int reg, u32 bits)
762{
763 prcmu_write_masked(reg, bits, bits);
764}
765
766static inline void prcmu_clear(unsigned int reg, u32 bits)
767{
768 prcmu_write_masked(reg, bits, 0);
769}
770
771#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
772
773/**
774 * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
775 */
776static inline void prcmu_enable_spi2(void)
777{
778 if (cpu_is_u8500())
779 prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
780}
781
782/**
783 * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
784 */
785static inline void prcmu_disable_spi2(void)
786{
787 if (cpu_is_u8500())
788 prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
789}
790
791/**
792 * prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD
793 * and UARTMOD on OtherAlternateC3.
794 */
795static inline void prcmu_enable_stm_mod_uart(void)
796{
797 if (cpu_is_u8500()) {
798 prcmu_set(DB8500_PRCM_GPIOCR,
799 (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
800 DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
801 }
802}
803
804/**
805 * prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD
806 * and UARTMOD on OtherAlternateC3.
807 */
808static inline void prcmu_disable_stm_mod_uart(void)
809{
810 if (cpu_is_u8500()) {
811 prcmu_clear(DB8500_PRCM_GPIOCR,
812 (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
813 DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
814 }
815}
816
817/**
818 * prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1.
819 */
820static inline void prcmu_enable_stm_ape(void)
821{
822 if (cpu_is_u8500()) {
823 prcmu_set(DB8500_PRCM_GPIOCR,
824 DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
825 }
826}
827
828/**
829 * prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1.
830 */
831static inline void prcmu_disable_stm_ape(void)
832{
833 if (cpu_is_u8500()) {
834 prcmu_clear(DB8500_PRCM_GPIOCR,
835 DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
836 }
837}
838
839#else
840
841static inline void prcmu_enable_spi2(void) {}
842static inline void prcmu_disable_spi2(void) {}
843static inline void prcmu_enable_stm_mod_uart(void) {}
844static inline void prcmu_disable_stm_mod_uart(void) {}
845static inline void prcmu_enable_stm_ape(void) {}
846static inline void prcmu_disable_stm_ape(void) {}
847
483#endif 848#endif
484 849
485/* PRCMU QoS APE OPP class */ 850/* PRCMU QoS APE OPP class */
486#define PRCMU_QOS_APE_OPP 1 851#define PRCMU_QOS_APE_OPP 1
487#define PRCMU_QOS_DDR_OPP 2 852#define PRCMU_QOS_DDR_OPP 2
853#define PRCMU_QOS_ARM_OPP 3
488#define PRCMU_QOS_DEFAULT_VALUE -1 854#define PRCMU_QOS_DEFAULT_VALUE -1
489 855
490#ifdef CONFIG_UX500_PRCMU_QOS_POWER 856#ifdef CONFIG_DBX500_PRCMU_QOS_POWER
491 857
492unsigned long prcmu_qos_get_cpufreq_opp_delay(void); 858unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
493void prcmu_qos_set_cpufreq_opp_delay(unsigned long); 859void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h
index b86ee45c8b03..10e038bac8dd 100644
--- a/include/linux/mfd/mc13xxx.h
+++ b/include/linux/mfd/mc13xxx.h
@@ -38,7 +38,8 @@ int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq);
38int mc13xxx_get_flags(struct mc13xxx *mc13xxx); 38int mc13xxx_get_flags(struct mc13xxx *mc13xxx);
39 39
40int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, 40int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx,
41 unsigned int mode, unsigned int channel, unsigned int *sample); 41 unsigned int mode, unsigned int channel,
42 u8 ato, bool atox, unsigned int *sample);
42 43
43#define MC13XXX_IRQ_ADCDONE 0 44#define MC13XXX_IRQ_ADCDONE 0
44#define MC13XXX_IRQ_ADCBISDONE 1 45#define MC13XXX_IRQ_ADCBISDONE 1
@@ -157,6 +158,18 @@ struct mc13xxx_buttons_platform_data {
157 unsigned short b3on_key; 158 unsigned short b3on_key;
158}; 159};
159 160
161struct mc13xxx_ts_platform_data {
162 /* Delay between Touchscreen polarization and ADC Conversion.
163 * Given in clock ticks of a 32 kHz clock which gives a granularity of
164 * about 30.5ms */
165 u8 ato;
166
167#define MC13783_TS_ATO_FIRST false
168#define MC13783_TS_ATO_EACH true
169 /* Use the ATO delay only for the first conversion or for each one */
170 bool atox;
171};
172
160struct mc13xxx_platform_data { 173struct mc13xxx_platform_data {
161#define MC13XXX_USE_TOUCHSCREEN (1 << 0) 174#define MC13XXX_USE_TOUCHSCREEN (1 << 0)
162#define MC13XXX_USE_CODEC (1 << 1) 175#define MC13XXX_USE_CODEC (1 << 1)
@@ -167,6 +180,7 @@ struct mc13xxx_platform_data {
167 struct mc13xxx_regulator_platform_data regulators; 180 struct mc13xxx_regulator_platform_data regulators;
168 struct mc13xxx_leds_platform_data *leds; 181 struct mc13xxx_leds_platform_data *leds;
169 struct mc13xxx_buttons_platform_data *buttons; 182 struct mc13xxx_buttons_platform_data *buttons;
183 struct mc13xxx_ts_platform_data touch;
170}; 184};
171 185
172#define MC13XXX_ADC_MODE_TS 1 186#define MC13XXX_ADC_MODE_TS 1
diff --git a/include/linux/mfd/rc5t583.h b/include/linux/mfd/rc5t583.h
new file mode 100644
index 000000000000..a2c61609d21d
--- /dev/null
+++ b/include/linux/mfd/rc5t583.h
@@ -0,0 +1,295 @@
1/*
2 * Core driver interface to access RICOH_RC5T583 power management chip.
3 *
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * Author: Laxman dewangan <ldewangan@nvidia.com>
6 *
7 * Based on code
8 * Copyright (C) 2011 RICOH COMPANY,LTD
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 */
23
24#ifndef __LINUX_MFD_RC5T583_H
25#define __LINUX_MFD_RC5T583_H
26
27#include <linux/mutex.h>
28#include <linux/types.h>
29
30#define RC5T583_MAX_REGS 0xF8
31
32/* Maximum number of main interrupts */
33#define MAX_MAIN_INTERRUPT 5
34#define RC5T583_MAX_GPEDGE_REG 2
35#define RC5T583_MAX_INTERRUPT_MASK_REGS 9
36
37/* Interrupt enable register */
38#define RC5T583_INT_EN_SYS1 0x19
39#define RC5T583_INT_EN_SYS2 0x1D
40#define RC5T583_INT_EN_DCDC 0x41
41#define RC5T583_INT_EN_RTC 0xED
42#define RC5T583_INT_EN_ADC1 0x90
43#define RC5T583_INT_EN_ADC2 0x91
44#define RC5T583_INT_EN_ADC3 0x92
45
46/* Interrupt status registers (monitor regs in Ricoh)*/
47#define RC5T583_INTC_INTPOL 0xAD
48#define RC5T583_INTC_INTEN 0xAE
49#define RC5T583_INTC_INTMON 0xAF
50
51#define RC5T583_INT_MON_GRP 0xAF
52#define RC5T583_INT_MON_SYS1 0x1B
53#define RC5T583_INT_MON_SYS2 0x1F
54#define RC5T583_INT_MON_DCDC 0x43
55#define RC5T583_INT_MON_RTC 0xEE
56
57/* Interrupt clearing registers */
58#define RC5T583_INT_IR_SYS1 0x1A
59#define RC5T583_INT_IR_SYS2 0x1E
60#define RC5T583_INT_IR_DCDC 0x42
61#define RC5T583_INT_IR_RTC 0xEE
62#define RC5T583_INT_IR_ADCL 0x94
63#define RC5T583_INT_IR_ADCH 0x95
64#define RC5T583_INT_IR_ADCEND 0x96
65#define RC5T583_INT_IR_GPIOR 0xA9
66#define RC5T583_INT_IR_GPIOF 0xAA
67
68/* Sleep sequence registers */
69#define RC5T583_SLPSEQ1 0x21
70#define RC5T583_SLPSEQ2 0x22
71#define RC5T583_SLPSEQ3 0x23
72#define RC5T583_SLPSEQ4 0x24
73#define RC5T583_SLPSEQ5 0x25
74#define RC5T583_SLPSEQ6 0x26
75#define RC5T583_SLPSEQ7 0x27
76#define RC5T583_SLPSEQ8 0x28
77#define RC5T583_SLPSEQ9 0x29
78#define RC5T583_SLPSEQ10 0x2A
79#define RC5T583_SLPSEQ11 0x2B
80
81/* Regulator registers */
82#define RC5T583_REG_DC0CTL 0x30
83#define RC5T583_REG_DC0DAC 0x31
84#define RC5T583_REG_DC0LATCTL 0x32
85#define RC5T583_REG_SR0CTL 0x33
86
87#define RC5T583_REG_DC1CTL 0x34
88#define RC5T583_REG_DC1DAC 0x35
89#define RC5T583_REG_DC1LATCTL 0x36
90#define RC5T583_REG_SR1CTL 0x37
91
92#define RC5T583_REG_DC2CTL 0x38
93#define RC5T583_REG_DC2DAC 0x39
94#define RC5T583_REG_DC2LATCTL 0x3A
95#define RC5T583_REG_SR2CTL 0x3B
96
97#define RC5T583_REG_DC3CTL 0x3C
98#define RC5T583_REG_DC3DAC 0x3D
99#define RC5T583_REG_DC3LATCTL 0x3E
100#define RC5T583_REG_SR3CTL 0x3F
101
102
103#define RC5T583_REG_LDOEN1 0x50
104#define RC5T583_REG_LDOEN2 0x51
105#define RC5T583_REG_LDODIS1 0x52
106#define RC5T583_REG_LDODIS2 0x53
107
108#define RC5T583_REG_LDO0DAC 0x54
109#define RC5T583_REG_LDO1DAC 0x55
110#define RC5T583_REG_LDO2DAC 0x56
111#define RC5T583_REG_LDO3DAC 0x57
112#define RC5T583_REG_LDO4DAC 0x58
113#define RC5T583_REG_LDO5DAC 0x59
114#define RC5T583_REG_LDO6DAC 0x5A
115#define RC5T583_REG_LDO7DAC 0x5B
116#define RC5T583_REG_LDO8DAC 0x5C
117#define RC5T583_REG_LDO9DAC 0x5D
118
119#define RC5T583_REG_DC0DAC_DS 0x60
120#define RC5T583_REG_DC1DAC_DS 0x61
121#define RC5T583_REG_DC2DAC_DS 0x62
122#define RC5T583_REG_DC3DAC_DS 0x63
123
124#define RC5T583_REG_LDO0DAC_DS 0x64
125#define RC5T583_REG_LDO1DAC_DS 0x65
126#define RC5T583_REG_LDO2DAC_DS 0x66
127#define RC5T583_REG_LDO3DAC_DS 0x67
128#define RC5T583_REG_LDO4DAC_DS 0x68
129#define RC5T583_REG_LDO5DAC_DS 0x69
130#define RC5T583_REG_LDO6DAC_DS 0x6A
131#define RC5T583_REG_LDO7DAC_DS 0x6B
132#define RC5T583_REG_LDO8DAC_DS 0x6C
133#define RC5T583_REG_LDO9DAC_DS 0x6D
134
135/* GPIO register base address */
136#define RC5T583_GPIO_IOSEL 0xA0
137#define RC5T583_GPIO_PDEN 0xA1
138#define RC5T583_GPIO_IOOUT 0xA2
139#define RC5T583_GPIO_PGSEL 0xA3
140#define RC5T583_GPIO_GPINV 0xA4
141#define RC5T583_GPIO_GPDEB 0xA5
142#define RC5T583_GPIO_GPEDGE1 0xA6
143#define RC5T583_GPIO_GPEDGE2 0xA7
144#define RC5T583_GPIO_EN_INT 0xA8
145#define RC5T583_GPIO_MON_IOIN 0xAB
146#define RC5T583_GPIO_GPOFUNC 0xAC
147
148/* RICOH_RC5T583 IRQ definitions */
149enum {
150 RC5T583_IRQ_ONKEY,
151 RC5T583_IRQ_ACOK,
152 RC5T583_IRQ_LIDOPEN,
153 RC5T583_IRQ_PREOT,
154 RC5T583_IRQ_CLKSTP,
155 RC5T583_IRQ_ONKEY_OFF,
156 RC5T583_IRQ_WD,
157 RC5T583_IRQ_EN_PWRREQ1,
158 RC5T583_IRQ_EN_PWRREQ2,
159 RC5T583_IRQ_PRE_VINDET,
160
161 RC5T583_IRQ_DC0LIM,
162 RC5T583_IRQ_DC1LIM,
163 RC5T583_IRQ_DC2LIM,
164 RC5T583_IRQ_DC3LIM,
165
166 RC5T583_IRQ_CTC,
167 RC5T583_IRQ_YALE,
168 RC5T583_IRQ_DALE,
169 RC5T583_IRQ_WALE,
170
171 RC5T583_IRQ_AIN1L,
172 RC5T583_IRQ_AIN2L,
173 RC5T583_IRQ_AIN3L,
174 RC5T583_IRQ_VBATL,
175 RC5T583_IRQ_VIN3L,
176 RC5T583_IRQ_VIN8L,
177 RC5T583_IRQ_AIN1H,
178 RC5T583_IRQ_AIN2H,
179 RC5T583_IRQ_AIN3H,
180 RC5T583_IRQ_VBATH,
181 RC5T583_IRQ_VIN3H,
182 RC5T583_IRQ_VIN8H,
183 RC5T583_IRQ_ADCEND,
184
185 RC5T583_IRQ_GPIO0,
186 RC5T583_IRQ_GPIO1,
187 RC5T583_IRQ_GPIO2,
188 RC5T583_IRQ_GPIO3,
189 RC5T583_IRQ_GPIO4,
190 RC5T583_IRQ_GPIO5,
191 RC5T583_IRQ_GPIO6,
192 RC5T583_IRQ_GPIO7,
193
194 /* Should be last entry */
195 RC5T583_MAX_IRQS,
196};
197
198/* Ricoh583 gpio definitions */
199enum {
200 RC5T583_GPIO0,
201 RC5T583_GPIO1,
202 RC5T583_GPIO2,
203 RC5T583_GPIO3,
204 RC5T583_GPIO4,
205 RC5T583_GPIO5,
206 RC5T583_GPIO6,
207 RC5T583_GPIO7,
208
209 /* Should be last entry */
210 RC5T583_MAX_GPIO,
211};
212
213enum {
214 RC5T583_DS_NONE,
215 RC5T583_DS_DC0,
216 RC5T583_DS_DC1,
217 RC5T583_DS_DC2,
218 RC5T583_DS_DC3,
219 RC5T583_DS_LDO0,
220 RC5T583_DS_LDO1,
221 RC5T583_DS_LDO2,
222 RC5T583_DS_LDO3,
223 RC5T583_DS_LDO4,
224 RC5T583_DS_LDO5,
225 RC5T583_DS_LDO6,
226 RC5T583_DS_LDO7,
227 RC5T583_DS_LDO8,
228 RC5T583_DS_LDO9,
229 RC5T583_DS_PSO0,
230 RC5T583_DS_PSO1,
231 RC5T583_DS_PSO2,
232 RC5T583_DS_PSO3,
233 RC5T583_DS_PSO4,
234 RC5T583_DS_PSO5,
235 RC5T583_DS_PSO6,
236 RC5T583_DS_PSO7,
237
238 /* Should be last entry */
239 RC5T583_DS_MAX,
240};
241
242/*
243 * Ricoh pmic RC5T583 supports sleep through two external controls.
244 * The output of gpios and regulator can be enable/disable through
245 * this external signals.
246 */
247enum {
248 RC5T583_EXT_PWRREQ1_CONTROL = 0x1,
249 RC5T583_EXT_PWRREQ2_CONTROL = 0x2,
250};
251
252struct rc5t583 {
253 struct device *dev;
254 struct regmap *regmap;
255 int chip_irq;
256 int irq_base;
257 struct mutex irq_lock;
258 unsigned long group_irq_en[MAX_MAIN_INTERRUPT];
259
260 /* For main interrupt bits in INTC */
261 uint8_t intc_inten_reg;
262
263 /* For group interrupt bits and address */
264 uint8_t irq_en_reg[RC5T583_MAX_INTERRUPT_MASK_REGS];
265
266 /* For gpio edge */
267 uint8_t gpedge_reg[RC5T583_MAX_GPEDGE_REG];
268};
269
270/*
271 * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
272 * The board specific data is provided through this structure.
273 * @irq_base: Irq base number on which this device registers their interrupts.
274 * @enable_shutdown: Enable shutdown through the input pin "shutdown".
275 */
276
277struct rc5t583_platform_data {
278 int irq_base;
279 bool enable_shutdown;
280};
281
282int rc5t583_write(struct device *dev, u8 reg, uint8_t val);
283int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val);
284int rc5t583_set_bits(struct device *dev, unsigned int reg,
285 unsigned int bit_mask);
286int rc5t583_clear_bits(struct device *dev, unsigned int reg,
287 unsigned int bit_mask);
288int rc5t583_update(struct device *dev, unsigned int reg,
289 unsigned int val, unsigned int mask);
290int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id,
291 int ext_pwr_req, int deepsleep_slot_nr);
292int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base);
293int rc5t583_irq_exit(struct rc5t583 *rc5t583);
294
295#endif
diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
index 8c54de674b4b..8516fd1eaabc 100644
--- a/include/linux/mfd/stmpe.h
+++ b/include/linux/mfd/stmpe.h
@@ -28,6 +28,7 @@ enum stmpe_partnum {
28 STMPE1601, 28 STMPE1601,
29 STMPE2401, 29 STMPE2401,
30 STMPE2403, 30 STMPE2403,
31 STMPE_NBR_PARTS
31}; 32};
32 33
33/* 34/*
diff --git a/include/linux/mfd/tps65090.h b/include/linux/mfd/tps65090.h
new file mode 100644
index 000000000000..38e31c55adbb
--- /dev/null
+++ b/include/linux/mfd/tps65090.h
@@ -0,0 +1,46 @@
1/*
2 * Core driver interface for TI TPS65090 PMIC family
3 *
4 * Copyright (C) 2012 NVIDIA Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 *
20 */
21
22#ifndef __LINUX_MFD_TPS65090_H
23#define __LINUX_MFD_TPS65090_H
24
25struct tps65090_subdev_info {
26 int id;
27 const char *name;
28 void *platform_data;
29};
30
31struct tps65090_platform_data {
32 int irq_base;
33 int num_subdevs;
34 struct tps65090_subdev_info *subdevs;
35};
36
37/*
38 * NOTE: the functions below are not intended for use outside
39 * of the TPS65090 sub-device drivers
40 */
41extern int tps65090_write(struct device *dev, int reg, uint8_t val);
42extern int tps65090_read(struct device *dev, int reg, uint8_t *val);
43extern int tps65090_set_bits(struct device *dev, int reg, uint8_t bit_num);
44extern int tps65090_clr_bits(struct device *dev, int reg, uint8_t bit_num);
45
46#endif /*__LINUX_MFD_TPS65090_H */
diff --git a/include/linux/mfd/tps65217.h b/include/linux/mfd/tps65217.h
new file mode 100644
index 000000000000..e030ef9a64ee
--- /dev/null
+++ b/include/linux/mfd/tps65217.h
@@ -0,0 +1,283 @@
1/*
2 * linux/mfd/tps65217.h
3 *
4 * Functions to access TPS65217 power management chip.
5 *
6 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#ifndef __LINUX_MFD_TPS65217_H
19#define __LINUX_MFD_TPS65217_H
20
21#include <linux/i2c.h>
22#include <linux/regulator/driver.h>
23#include <linux/regulator/machine.h>
24
25/* I2C ID for TPS65217 part */
26#define TPS65217_I2C_ID 0x24
27
28/* All register addresses */
29#define TPS65217_REG_CHIPID 0X00
30#define TPS65217_REG_PPATH 0X01
31#define TPS65217_REG_INT 0X02
32#define TPS65217_REG_CHGCONFIG0 0X03
33#define TPS65217_REG_CHGCONFIG1 0X04
34#define TPS65217_REG_CHGCONFIG2 0X05
35#define TPS65217_REG_CHGCONFIG3 0X06
36#define TPS65217_REG_WLEDCTRL1 0X07
37#define TPS65217_REG_WLEDCTRL2 0X08
38#define TPS65217_REG_MUXCTRL 0X09
39#define TPS65217_REG_STATUS 0X0A
40#define TPS65217_REG_PASSWORD 0X0B
41#define TPS65217_REG_PGOOD 0X0C
42#define TPS65217_REG_DEFPG 0X0D
43#define TPS65217_REG_DEFDCDC1 0X0E
44#define TPS65217_REG_DEFDCDC2 0X0F
45#define TPS65217_REG_DEFDCDC3 0X10
46#define TPS65217_REG_DEFSLEW 0X11
47#define TPS65217_REG_DEFLDO1 0X12
48#define TPS65217_REG_DEFLDO2 0X13
49#define TPS65217_REG_DEFLS1 0X14
50#define TPS65217_REG_DEFLS2 0X15
51#define TPS65217_REG_ENABLE 0X16
52#define TPS65217_REG_DEFUVLO 0X18
53#define TPS65217_REG_SEQ1 0X19
54#define TPS65217_REG_SEQ2 0X1A
55#define TPS65217_REG_SEQ3 0X1B
56#define TPS65217_REG_SEQ4 0X1C
57#define TPS65217_REG_SEQ5 0X1D
58#define TPS65217_REG_SEQ6 0X1E
59
60/* Register field definitions */
61#define TPS65217_CHIPID_CHIP_MASK 0xF0
62#define TPS65217_CHIPID_REV_MASK 0x0F
63
64#define TPS65217_PPATH_ACSINK_ENABLE BIT(7)
65#define TPS65217_PPATH_USBSINK_ENABLE BIT(6)
66#define TPS65217_PPATH_AC_PW_ENABLE BIT(5)
67#define TPS65217_PPATH_USB_PW_ENABLE BIT(4)
68#define TPS65217_PPATH_AC_CURRENT_MASK 0x0C
69#define TPS65217_PPATH_USB_CURRENT_MASK 0x03
70
71#define TPS65217_INT_PBM BIT(6)
72#define TPS65217_INT_ACM BIT(5)
73#define TPS65217_INT_USBM BIT(4)
74#define TPS65217_INT_PBI BIT(2)
75#define TPS65217_INT_ACI BIT(1)
76#define TPS65217_INT_USBI BIT(0)
77
78#define TPS65217_CHGCONFIG0_TREG BIT(7)
79#define TPS65217_CHGCONFIG0_DPPM BIT(6)
80#define TPS65217_CHGCONFIG0_TSUSP BIT(5)
81#define TPS65217_CHGCONFIG0_TERMI BIT(4)
82#define TPS65217_CHGCONFIG0_ACTIVE BIT(3)
83#define TPS65217_CHGCONFIG0_CHGTOUT BIT(2)
84#define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1)
85#define TPS65217_CHGCONFIG0_BATTEMP BIT(0)
86
87#define TPS65217_CHGCONFIG1_TMR_MASK 0xC0
88#define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5)
89#define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4)
90#define TPS65217_CHGCONFIG1_RESET BIT(3)
91#define TPS65217_CHGCONFIG1_TERM BIT(2)
92#define TPS65217_CHGCONFIG1_SUSP BIT(1)
93#define TPS65217_CHGCONFIG1_CHG_EN BIT(0)
94
95#define TPS65217_CHGCONFIG2_DYNTMR BIT(7)
96#define TPS65217_CHGCONFIG2_VPREGHG BIT(6)
97#define TPS65217_CHGCONFIG2_VOREG_MASK 0x30
98
99#define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0
100#define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30
101#define TPS65217_CHGCONFIG2_PCHRGT BIT(3)
102#define TPS65217_CHGCONFIG2_TERMIF 0x06
103#define TPS65217_CHGCONFIG2_TRANGE BIT(0)
104
105#define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3)
106#define TPS65217_WLEDCTRL1_ISEL BIT(2)
107#define TPS65217_WLEDCTRL1_FDIM_MASK 0x03
108
109#define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F
110
111#define TPS65217_MUXCTRL_MUX_MASK 0x07
112
113#define TPS65217_STATUS_OFF BIT(7)
114#define TPS65217_STATUS_ACPWR BIT(3)
115#define TPS65217_STATUS_USBPWR BIT(2)
116#define TPS65217_STATUS_PB BIT(0)
117
118#define TPS65217_PASSWORD_REGS_UNLOCK 0x7D
119
120#define TPS65217_PGOOD_LDO3_PG BIT(6)
121#define TPS65217_PGOOD_LDO4_PG BIT(5)
122#define TPS65217_PGOOD_DC1_PG BIT(4)
123#define TPS65217_PGOOD_DC2_PG BIT(3)
124#define TPS65217_PGOOD_DC3_PG BIT(2)
125#define TPS65217_PGOOD_LDO1_PG BIT(1)
126#define TPS65217_PGOOD_LDO2_PG BIT(0)
127
128#define TPS65217_DEFPG_LDO1PGM BIT(3)
129#define TPS65217_DEFPG_LDO2PGM BIT(2)
130#define TPS65217_DEFPG_PGDLY_MASK 0x03
131
132#define TPS65217_DEFDCDCX_XADJX BIT(7)
133#define TPS65217_DEFDCDCX_DCDC_MASK 0x3F
134
135#define TPS65217_DEFSLEW_GO BIT(7)
136#define TPS65217_DEFSLEW_GODSBL BIT(6)
137#define TPS65217_DEFSLEW_PFM_EN1 BIT(5)
138#define TPS65217_DEFSLEW_PFM_EN2 BIT(4)
139#define TPS65217_DEFSLEW_PFM_EN3 BIT(3)
140#define TPS65217_DEFSLEW_SLEW_MASK 0x07
141
142#define TPS65217_DEFLDO1_LDO1_MASK 0x0F
143
144#define TPS65217_DEFLDO2_TRACK BIT(6)
145#define TPS65217_DEFLDO2_LDO2_MASK 0x3F
146
147#define TPS65217_DEFLDO3_LDO3_EN BIT(5)
148#define TPS65217_DEFLDO3_LDO3_MASK 0x1F
149
150#define TPS65217_DEFLDO4_LDO4_EN BIT(5)
151#define TPS65217_DEFLDO4_LDO4_MASK 0x1F
152
153#define TPS65217_ENABLE_LS1_EN BIT(6)
154#define TPS65217_ENABLE_LS2_EN BIT(5)
155#define TPS65217_ENABLE_DC1_EN BIT(4)
156#define TPS65217_ENABLE_DC2_EN BIT(3)
157#define TPS65217_ENABLE_DC3_EN BIT(2)
158#define TPS65217_ENABLE_LDO1_EN BIT(1)
159#define TPS65217_ENABLE_LDO2_EN BIT(0)
160
161#define TPS65217_DEFUVLO_UVLOHYS BIT(2)
162#define TPS65217_DEFUVLO_UVLO_MASK 0x03
163
164#define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0
165#define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F
166
167#define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0
168#define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F
169
170#define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0
171#define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F
172
173#define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0
174
175#define TPS65217_SEQ5_DLY1_MASK 0xC0
176#define TPS65217_SEQ5_DLY2_MASK 0x30
177#define TPS65217_SEQ5_DLY3_MASK 0x0C
178#define TPS65217_SEQ5_DLY4_MASK 0x03
179
180#define TPS65217_SEQ6_DLY5_MASK 0xC0
181#define TPS65217_SEQ6_DLY6_MASK 0x30
182#define TPS65217_SEQ6_SEQUP BIT(2)
183#define TPS65217_SEQ6_SEQDWN BIT(1)
184#define TPS65217_SEQ6_INSTDWN BIT(0)
185
186#define TPS65217_MAX_REGISTER 0x1E
187#define TPS65217_PROTECT_NONE 0
188#define TPS65217_PROTECT_L1 1
189#define TPS65217_PROTECT_L2 2
190
191
192enum tps65217_regulator_id {
193 /* DCDC's */
194 TPS65217_DCDC_1,
195 TPS65217_DCDC_2,
196 TPS65217_DCDC_3,
197 /* LDOs */
198 TPS65217_LDO_1,
199 TPS65217_LDO_2,
200 TPS65217_LDO_3,
201 TPS65217_LDO_4,
202};
203
204#define TPS65217_MAX_REG_ID TPS65217_LDO_4
205
206/* Number of step-down converters available */
207#define TPS65217_NUM_DCDC 3
208/* Number of LDO voltage regulators available */
209#define TPS65217_NUM_LDO 4
210/* Number of total regulators available */
211#define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
212
213/**
214 * struct tps65217_board - packages regulator init data
215 * @tps65217_regulator_data: regulator initialization values
216 *
217 * Board data may be used to initialize regulator.
218 */
219struct tps65217_board {
220 struct regulator_init_data *tps65217_init_data;
221};
222
223/**
224 * struct tps_info - packages regulator constraints
225 * @name: Voltage regulator name
226 * @min_uV: minimum micro volts
227 * @max_uV: minimum micro volts
228 * @vsel_to_uv: Function pointer to get voltage from selector
229 * @uv_to_vsel: Function pointer to get selector from voltage
230 * @table: Table for non-uniform voltage step-size
231 * @table_len: Length of the voltage table
232 * @enable_mask: Regulator enable mask bits
233 * @set_vout_reg: Regulator output voltage set register
234 * @set_vout_mask: Regulator output voltage set mask
235 *
236 * This data is used to check the regualtor voltage limits while setting.
237 */
238struct tps_info {
239 const char *name;
240 int min_uV;
241 int max_uV;
242 int (*vsel_to_uv)(unsigned int vsel);
243 int (*uv_to_vsel)(int uV, unsigned int *vsel);
244 const int *table;
245 unsigned int table_len;
246 unsigned int enable_mask;
247 unsigned int set_vout_reg;
248 unsigned int set_vout_mask;
249};
250
251/**
252 * struct tps65217 - tps65217 sub-driver chip access routines
253 *
254 * Device data may be used to access the TPS65217 chip
255 */
256
257struct tps65217 {
258 struct device *dev;
259 struct tps65217_board *pdata;
260 struct regulator_desc desc[TPS65217_NUM_REGULATOR];
261 struct regulator_dev *rdev[TPS65217_NUM_REGULATOR];
262 struct tps_info *info[TPS65217_NUM_REGULATOR];
263 struct regmap *regmap;
264
265 /* Client devices */
266 struct platform_device *regulator_pdev[TPS65217_NUM_REGULATOR];
267};
268
269static inline struct tps65217 *dev_to_tps65217(struct device *dev)
270{
271 return dev_get_drvdata(dev);
272}
273
274int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
275 unsigned int *val);
276int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
277 unsigned int val, unsigned int level);
278int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
279 unsigned int mask, unsigned int val, unsigned int level);
280int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
281 unsigned int mask, unsigned int level);
282
283#endif /* __LINUX_MFD_TPS65217_H */
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
index 76700b5eee92..e34886397f90 100644
--- a/include/linux/mfd/tps65910.h
+++ b/include/linux/mfd/tps65910.h
@@ -17,6 +17,8 @@
17#ifndef __LINUX_MFD_TPS65910_H 17#ifndef __LINUX_MFD_TPS65910_H
18#define __LINUX_MFD_TPS65910_H 18#define __LINUX_MFD_TPS65910_H
19 19
20#include <linux/gpio.h>
21
20/* TPS chip id list */ 22/* TPS chip id list */
21#define TPS65910 0 23#define TPS65910 0
22#define TPS65911 1 24#define TPS65911 1
@@ -796,6 +798,7 @@ struct tps65910_board {
796struct tps65910 { 798struct tps65910 {
797 struct device *dev; 799 struct device *dev;
798 struct i2c_client *i2c_client; 800 struct i2c_client *i2c_client;
801 struct regmap *regmap;
799 struct mutex io_mutex; 802 struct mutex io_mutex;
800 unsigned int id; 803 unsigned int id;
801 int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest); 804 int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h
index dc3e05011689..893267bb6229 100644
--- a/include/linux/mfd/wm8994/pdata.h
+++ b/include/linux/mfd/wm8994/pdata.h
@@ -22,7 +22,6 @@ struct wm8994_ldo_pdata {
22 /** GPIOs to enable regulator, 0 or less if not available */ 22 /** GPIOs to enable regulator, 0 or less if not available */
23 int enable; 23 int enable;
24 24
25 const char *supply;
26 const struct regulator_init_data *init_data; 25 const struct regulator_init_data *init_data;
27}; 26};
28 27
diff --git a/include/linux/regulator/ab8500.h b/include/linux/regulator/ab8500.h
index 76579f964a29..7bd73bbdfd1b 100644
--- a/include/linux/regulator/ab8500.h
+++ b/include/linux/regulator/ab8500.h
@@ -26,7 +26,26 @@ enum ab8500_regulator_id {
26 AB8500_NUM_REGULATORS, 26 AB8500_NUM_REGULATORS,
27}; 27};
28 28
29/* AB8500 register initialization */ 29/* AB9450 regulators */
30enum ab9540_regulator_id {
31 AB9540_LDO_AUX1,
32 AB9540_LDO_AUX2,
33 AB9540_LDO_AUX3,
34 AB9540_LDO_AUX4,
35 AB9540_LDO_INTCORE,
36 AB9540_LDO_TVOUT,
37 AB9540_LDO_USB,
38 AB9540_LDO_AUDIO,
39 AB9540_LDO_ANAMIC1,
40 AB9540_LDO_ANAMIC2,
41 AB9540_LDO_DMIC,
42 AB9540_LDO_ANA,
43 AB9540_SYSCLKREQ_2,
44 AB9540_SYSCLKREQ_4,
45 AB9540_NUM_REGULATORS,
46};
47
48/* AB8500 and AB9540 register initialization */
30struct ab8500_regulator_reg_init { 49struct ab8500_regulator_reg_init {
31 int id; 50 int id;
32 u8 value; 51 u8 value;
@@ -71,4 +90,53 @@ enum ab8500_regulator_reg {
71 AB8500_NUM_REGULATOR_REGISTERS, 90 AB8500_NUM_REGULATOR_REGISTERS,
72}; 91};
73 92
93
94/* AB9540 registers */
95enum ab9540_regulator_reg {
96 AB9540_REGUREQUESTCTRL1,
97 AB9540_REGUREQUESTCTRL2,
98 AB9540_REGUREQUESTCTRL3,
99 AB9540_REGUREQUESTCTRL4,
100 AB9540_REGUSYSCLKREQ1HPVALID1,
101 AB9540_REGUSYSCLKREQ1HPVALID2,
102 AB9540_REGUHWHPREQ1VALID1,
103 AB9540_REGUHWHPREQ1VALID2,
104 AB9540_REGUHWHPREQ2VALID1,
105 AB9540_REGUHWHPREQ2VALID2,
106 AB9540_REGUSWHPREQVALID1,
107 AB9540_REGUSWHPREQVALID2,
108 AB9540_REGUSYSCLKREQVALID1,
109 AB9540_REGUSYSCLKREQVALID2,
110 AB9540_REGUVAUX4REQVALID,
111 AB9540_REGUMISC1,
112 AB9540_VAUDIOSUPPLY,
113 AB9540_REGUCTRL1VAMIC,
114 AB9540_VSMPS1REGU,
115 AB9540_VSMPS2REGU,
116 AB9540_VSMPS3REGU, /* NOTE! PRCMU register */
117 AB9540_VPLLVANAREGU,
118 AB9540_EXTSUPPLYREGU,
119 AB9540_VAUX12REGU,
120 AB9540_VRF1VAUX3REGU,
121 AB9540_VSMPS1SEL1,
122 AB9540_VSMPS1SEL2,
123 AB9540_VSMPS1SEL3,
124 AB9540_VSMPS2SEL1,
125 AB9540_VSMPS2SEL2,
126 AB9540_VSMPS2SEL3,
127 AB9540_VSMPS3SEL1, /* NOTE! PRCMU register */
128 AB9540_VSMPS3SEL2, /* NOTE! PRCMU register */
129 AB9540_VAUX1SEL,
130 AB9540_VAUX2SEL,
131 AB9540_VRF1VAUX3SEL,
132 AB9540_REGUCTRL2SPARE,
133 AB9540_VAUX4REQCTRL,
134 AB9540_VAUX4REGU,
135 AB9540_VAUX4SEL,
136 AB9540_REGUCTRLDISCH,
137 AB9540_REGUCTRLDISCH2,
138 AB9540_REGUCTRLDISCH3,
139 AB9540_NUM_REGULATOR_REGISTERS,
140};
141
74#endif 142#endif
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