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authorYu Zhao <yu.zhao@intel.com>2009-05-18 01:51:32 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2009-05-18 06:25:54 -0400
commit302b4215daa0a704c843da40fd2529e5757a72da (patch)
tree1bc40108fceafd3fbc9faee38c971fa94d560b13 /include/linux
parentdd7264355a203c3456dbba04db471947d3b55e7e (diff)
PCI: support the ATS capability
The PCIe ATS capability makes the Endpoint be able to request the DMA address translation from the IOMMU and cache the translation in the device side, thus alleviate IOMMU pressure and improve the hardware performance in the I/O virtualization environment. Signed-off-by: Yu Zhao <yu.zhao@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/pci.h2
-rw-r--r--include/linux/pci_regs.h10
2 files changed, 12 insertions, 0 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 72698d89e767..bd3e4a798c43 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -188,6 +188,7 @@ struct pci_cap_saved_state {
188struct pcie_link_state; 188struct pcie_link_state;
189struct pci_vpd; 189struct pci_vpd;
190struct pci_sriov; 190struct pci_sriov;
191struct pci_ats;
191 192
192/* 193/*
193 * The pci_dev structure is used to describe PCI devices. 194 * The pci_dev structure is used to describe PCI devices.
@@ -285,6 +286,7 @@ struct pci_dev {
285 struct pci_sriov *sriov; /* SR-IOV capability related */ 286 struct pci_sriov *sriov; /* SR-IOV capability related */
286 struct pci_dev *physfn; /* the PF this VF is associated with */ 287 struct pci_dev *physfn; /* the PF this VF is associated with */
287 }; 288 };
289 struct pci_ats *ats; /* Address Translation Service */
288#endif 290#endif
289}; 291};
290 292
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index e4d08c1b2e0b..c03189c56c7a 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -501,6 +501,7 @@
501#define PCI_EXT_CAP_ID_DSN 3 501#define PCI_EXT_CAP_ID_DSN 3
502#define PCI_EXT_CAP_ID_PWR 4 502#define PCI_EXT_CAP_ID_PWR 4
503#define PCI_EXT_CAP_ID_ARI 14 503#define PCI_EXT_CAP_ID_ARI 14
504#define PCI_EXT_CAP_ID_ATS 15
504#define PCI_EXT_CAP_ID_SRIOV 16 505#define PCI_EXT_CAP_ID_SRIOV 16
505 506
506/* Advanced Error Reporting */ 507/* Advanced Error Reporting */
@@ -619,6 +620,15 @@
619#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ 620#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
620#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ 621#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
621 622
623/* Address Translation Service */
624#define PCI_ATS_CAP 0x04 /* ATS Capability Register */
625#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */
626#define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */
627#define PCI_ATS_CTRL 0x06 /* ATS Control Register */
628#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
629#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */
630#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */
631
622/* Single Root I/O Virtualization */ 632/* Single Root I/O Virtualization */
623#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 633#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
624#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ 634#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */