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authorLinus Torvalds <torvalds@linux-foundation.org>2008-08-07 21:14:07 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-08-07 21:14:07 -0400
commit273b2578392bbf6e5c47a8a3d1ee461ce6fc7182 (patch)
tree1b00bd21574b1f8db084be4f682d7251a3a0ff3e /include/linux
parent8e43e12d638f732fa32600c324711f4be8fe0b1d (diff)
parent06a91a02e9b249695f964bb59c8b02152c21e90c (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband: IB/mad: Test ib_create_send_mad() return with IS_ERR(), not == NULL IB/mlx4: Allow 4K messages for UD QPs mlx4_core: Add ethernet fields to CQE struct IB/ipath: Fix printk format warnings RDMA/cxgb3: Fix deadlock initializing iw_cxgb3 device RDMA/cxgb3: Fix up MW access rights RDMA/cxgb3: Fix QP capabilities RDMA/cma: Remove padding arrays by using struct sockaddr_storage IB/ipath: Use unsigned long for irq flags IPoIB/cm: Set correct SG list in ipoib_cm_init_rx_wr()
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/mlx4/cq.h36
1 files changed, 24 insertions, 12 deletions
diff --git a/include/linux/mlx4/cq.h b/include/linux/mlx4/cq.h
index 071cf96cf01f..6f65b2c8bb89 100644
--- a/include/linux/mlx4/cq.h
+++ b/include/linux/mlx4/cq.h
@@ -39,17 +39,18 @@
39#include <linux/mlx4/doorbell.h> 39#include <linux/mlx4/doorbell.h>
40 40
41struct mlx4_cqe { 41struct mlx4_cqe {
42 __be32 my_qpn; 42 __be32 vlan_my_qpn;
43 __be32 immed_rss_invalid; 43 __be32 immed_rss_invalid;
44 __be32 g_mlpath_rqpn; 44 __be32 g_mlpath_rqpn;
45 u8 sl; 45 __be16 sl_vid;
46 u8 reserved1;
47 __be16 rlid; 46 __be16 rlid;
48 __be32 ipoib_status; 47 __be16 status;
48 u8 ipv6_ext_mask;
49 u8 badfcs_enc;
49 __be32 byte_cnt; 50 __be32 byte_cnt;
50 __be16 wqe_index; 51 __be16 wqe_index;
51 __be16 checksum; 52 __be16 checksum;
52 u8 reserved2[3]; 53 u8 reserved[3];
53 u8 owner_sr_opcode; 54 u8 owner_sr_opcode;
54}; 55};
55 56
@@ -64,6 +65,11 @@ struct mlx4_err_cqe {
64}; 65};
65 66
66enum { 67enum {
68 MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29,
69 MLX4_CQE_QPN_MASK = 0xffffff,
70};
71
72enum {
67 MLX4_CQE_OWNER_MASK = 0x80, 73 MLX4_CQE_OWNER_MASK = 0x80,
68 MLX4_CQE_IS_SEND_MASK = 0x40, 74 MLX4_CQE_IS_SEND_MASK = 0x40,
69 MLX4_CQE_OPCODE_MASK = 0x1f 75 MLX4_CQE_OPCODE_MASK = 0x1f
@@ -86,13 +92,19 @@ enum {
86}; 92};
87 93
88enum { 94enum {
89 MLX4_CQE_IPOIB_STATUS_IPV4 = 1 << 22, 95 MLX4_CQE_STATUS_IPV4 = 1 << 6,
90 MLX4_CQE_IPOIB_STATUS_IPV4F = 1 << 23, 96 MLX4_CQE_STATUS_IPV4F = 1 << 7,
91 MLX4_CQE_IPOIB_STATUS_IPV6 = 1 << 24, 97 MLX4_CQE_STATUS_IPV6 = 1 << 8,
92 MLX4_CQE_IPOIB_STATUS_IPV4OPT = 1 << 25, 98 MLX4_CQE_STATUS_IPV4OPT = 1 << 9,
93 MLX4_CQE_IPOIB_STATUS_TCP = 1 << 26, 99 MLX4_CQE_STATUS_TCP = 1 << 10,
94 MLX4_CQE_IPOIB_STATUS_UDP = 1 << 27, 100 MLX4_CQE_STATUS_UDP = 1 << 11,
95 MLX4_CQE_IPOIB_STATUS_IPOK = 1 << 28, 101 MLX4_CQE_STATUS_IPOK = 1 << 12,
102};
103
104enum {
105 MLX4_CQE_LLC = 1,
106 MLX4_CQE_SNAP = 1 << 1,
107 MLX4_CQE_BAD_FCS = 1 << 4,
96}; 108};
97 109
98static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd, 110static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,