diff options
author | Samuel Ortiz <sameo@openedhand.com> | 2008-06-20 05:12:21 -0400 |
---|---|---|
committer | Samuel Ortiz <samuel@sortiz.org> | 2008-07-20 13:55:14 -0400 |
commit | 3b8139f8b1457af7b5295d97050b3f9a2545a17a (patch) | |
tree | f487a026aee9fbf2c0dceb5352a76bd33c09cfa0 /include/linux | |
parent | 24f4f2eef2714bddd6fdb823be53fc2ee69699e0 (diff) |
mfd: Use uppercase only for asic3 macros and defines
Let's be consistent and use uppercase only, for both macro and defines.
Signed-off-by: Samuel Ortiz <sameo@openedhand.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Diffstat (limited to 'include/linux')
-rw-r--r-- | include/linux/mfd/asic3.h | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h index 7e47cfb0c440..6461a2ae69a2 100644 --- a/include/linux/mfd/asic3.h +++ b/include/linux/mfd/asic3.h | |||
@@ -45,39 +45,39 @@ struct asic3_platform_data { | |||
45 | /* All offsets below are specified with this address bus shift */ | 45 | /* All offsets below are specified with this address bus shift */ |
46 | #define ASIC3_DEFAULT_ADDR_SHIFT 2 | 46 | #define ASIC3_DEFAULT_ADDR_SHIFT 2 |
47 | 47 | ||
48 | #define ASIC3_OFFSET(base, reg) (ASIC3_##base##_Base + ASIC3_##base##_##reg) | 48 | #define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg) |
49 | #define ASIC3_GPIO_OFFSET(base, reg) \ | 49 | #define ASIC3_GPIO_OFFSET(base, reg) \ |
50 | (ASIC3_GPIO_##base##_Base + ASIC3_GPIO_##reg) | 50 | (ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg) |
51 | 51 | ||
52 | #define ASIC3_GPIO_A_Base 0x0000 | 52 | #define ASIC3_GPIO_A_BASE 0x0000 |
53 | #define ASIC3_GPIO_B_Base 0x0100 | 53 | #define ASIC3_GPIO_B_BASE 0x0100 |
54 | #define ASIC3_GPIO_C_Base 0x0200 | 54 | #define ASIC3_GPIO_C_BASE 0x0200 |
55 | #define ASIC3_GPIO_D_Base 0x0300 | 55 | #define ASIC3_GPIO_D_BASE 0x0300 |
56 | 56 | ||
57 | #define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4) | 57 | #define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4) |
58 | #define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \ | 58 | #define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \ |
59 | (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4))) | 59 | (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4))) |
60 | #define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio)) | 60 | #define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio)) |
61 | #define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_Base + (((gpio) >> 4) * 0x0100)) | 61 | #define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100)) |
62 | #define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_Base + ((bank) * 0x100)) | 62 | #define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100)) |
63 | 63 | ||
64 | #define ASIC3_GPIO_Mask 0x00 /* R/W 0:don't mask */ | 64 | #define ASIC3_GPIO_MASK 0x00 /* R/W 0:don't mask */ |
65 | #define ASIC3_GPIO_Direction 0x04 /* R/W 0:input */ | 65 | #define ASIC3_GPIO_DIRECTION 0x04 /* R/W 0:input */ |
66 | #define ASIC3_GPIO_Out 0x08 /* R/W 0:output low */ | 66 | #define ASIC3_GPIO_OUT 0x08 /* R/W 0:output low */ |
67 | #define ASIC3_GPIO_TriggerType 0x0c /* R/W 0:level */ | 67 | #define ASIC3_GPIO_TRIGGER_TYPE 0x0c /* R/W 0:level */ |
68 | #define ASIC3_GPIO_EdgeTrigger 0x10 /* R/W 0:falling */ | 68 | #define ASIC3_GPIO_EDGE_TRIGGER 0x10 /* R/W 0:falling */ |
69 | #define ASIC3_GPIO_LevelTrigger 0x14 /* R/W 0:low level detect */ | 69 | #define ASIC3_GPIO_LEVEL_TRIGGER 0x14 /* R/W 0:low level detect */ |
70 | #define ASIC3_GPIO_SleepMask 0x18 /* R/W 0:don't mask in sleep mode */ | 70 | #define ASIC3_GPIO_SLEEP_MASK 0x18 /* R/W 0:don't mask in sleep mode */ |
71 | #define ASIC3_GPIO_SleepOut 0x1c /* R/W level 0:low in sleep mode */ | 71 | #define ASIC3_GPIO_SLEEP_OUT 0x1c /* R/W level 0:low in sleep mode */ |
72 | #define ASIC3_GPIO_BattFaultOut 0x20 /* R/W level 0:low in batt_fault */ | 72 | #define ASIC3_GPIO_BAT_FAULT_OUT 0x20 /* R/W level 0:low in batt_fault */ |
73 | #define ASIC3_GPIO_IntStatus 0x24 /* R/W 0:none, 1:detect */ | 73 | #define ASIC3_GPIO_INT_STATUS 0x24 /* R/W 0:none, 1:detect */ |
74 | #define ASIC3_GPIO_AltFunction 0x28 /* R/W 1:LED register control */ | 74 | #define ASIC3_GPIO_ALT_FUNCTION 0x28 /* R/W 1:LED register control */ |
75 | #define ASIC3_GPIO_SleepConf 0x2c /* | 75 | #define ASIC3_GPIO_SLEEP_CONF 0x2c /* |
76 | * R/W bit 1: autosleep | 76 | * R/W bit 1: autosleep |
77 | * 0: disable gposlpout in normal mode, | 77 | * 0: disable gposlpout in normal mode, |
78 | * enable gposlpout in sleep mode. | 78 | * enable gposlpout in sleep mode. |
79 | */ | 79 | */ |
80 | #define ASIC3_GPIO_Status 0x30 /* R Pin status */ | 80 | #define ASIC3_GPIO_STATUS 0x30 /* R Pin status */ |
81 | 81 | ||
82 | /* | 82 | /* |
83 | * ASIC3 GPIO config | 83 | * ASIC3 GPIO config |
@@ -137,7 +137,7 @@ struct asic3_platform_data { | |||
137 | #define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */ | 137 | #define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */ |
138 | #define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */ | 138 | #define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */ |
139 | 139 | ||
140 | #define ASIC3_CLOCK_Base 0x0A00 | 140 | #define ASIC3_CLOCK_BASE 0x0A00 |
141 | #define ASIC3_CLOCK_CDEX 0x00 | 141 | #define ASIC3_CLOCK_CDEX 0x00 |
142 | #define ASIC3_CLOCK_SEL 0x04 | 142 | #define ASIC3_CLOCK_SEL 0x04 |
143 | 143 | ||
@@ -168,12 +168,12 @@ struct asic3_platform_data { | |||
168 | #define CLOCK_SEL_CX (1 << 2) | 168 | #define CLOCK_SEL_CX (1 << 2) |
169 | 169 | ||
170 | 170 | ||
171 | #define ASIC3_INTR_Base 0x0B00 | 171 | #define ASIC3_INTR_BASE 0x0B00 |
172 | 172 | ||
173 | #define ASIC3_INTR_IntMask 0x00 /* Interrupt mask control */ | 173 | #define ASIC3_INTR_INT_MASK 0x00 /* Interrupt mask control */ |
174 | #define ASIC3_INTR_PIntStat 0x04 /* Peripheral interrupt status */ | 174 | #define ASIC3_INTR_P_INT_STAT 0x04 /* Peripheral interrupt status */ |
175 | #define ASIC3_INTR_IntCPS 0x08 /* Interrupt timer clock pre-scale */ | 175 | #define ASIC3_INTR_INT_CPS 0x08 /* Interrupt timer clock pre-scale */ |
176 | #define ASIC3_INTR_IntTBS 0x0c /* Interrupt timer set */ | 176 | #define ASIC3_INTR_INT_TBS 0x0c /* Interrupt timer set */ |
177 | 177 | ||
178 | #define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */ | 178 | #define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */ |
179 | #define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */ | 179 | #define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */ |