[media] v4l2-dv-timings.h: definitions for CEA-861 and VESA DMT timings

This header contains the timings for the common CEA-861 and all VESA
DMT formats for use with the V4L2 dv_timings API.

Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Reviewed-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

2 files changed, 817 insertions, 0 deletions

diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index 3c9b616c834a..d38b3a8fb380 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -382,6 +382,7 @@ header-y += usbdevice_fs.h
 header-y += utime.h
 header-y += utsname.h
 header-y += uvcvideo.h
+header-y += v4l2-dv-timings.h
 header-y += v4l2-mediabus.h
 header-y += v4l2-subdev.h
 header-y += veth.h
diff --git a/include/linux/v4l2-dv-timings.h b/include/linux/v4l2-dv-timings.h
new file mode 100644
index 000000000000..9ef8172e5ed0
--- /dev/null
+++ b/include/linux/v4l2-dv-timings.h
@@ -0,0 +1,816 @@
+/*
+ * V4L2 DV timings header.
+ *
+ * Copyright (C) 2012  Hans Verkuil <hans.verkuil@cisco.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+
+#ifndef _V4L2_DV_TIMINGS_H
+#define _V4L2_DV_TIMINGS_H
+
+#if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6))
+/* Sadly gcc versions older than 4.6 have a bug in how they initialize
+   anonymous unions where they require additional curly brackets.
+   This violates the C1x standard. This workaround adds the curly brackets
+   if needed. */
+#define V4L2_INIT_BT_TIMINGS(_width, args...) \
+        { .bt = { _width , ## args } }
+#else
+#define V4L2_INIT_BT_TIMINGS(_width, args...) \
+        .bt = { _width , ## args }
+#endif
+
+/* CEA-861-E timings (i.e. standard HDTV timings) */
+
+#define V4L2_DV_BT_CEA_640X480P59_94 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
+                25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \
+                V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \
+}
+
+#define V4L2_DV_BT_CEA_720X480P59_94 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
+                27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, 0) \
+}
+
+#define V4L2_DV_BT_CEA_720X576P50 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
+                27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, 0) \
+}
+
+#define V4L2_DV_BT_CEA_1280X720P24 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+                V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+                59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
+                V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
+                V4L2_DV_FL_CAN_REDUCE_FPS) \
+}
+
+#define V4L2_DV_BT_CEA_1280X720P25 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+                V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+                74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, 0) \
+}
+
+#define V4L2_DV_BT_CEA_1280X720P30 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+                V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+                74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
+}
+
+#define V4L2_DV_BT_CEA_1280X720P50 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+                V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+                74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, 0) \
+}
+
+#define V4L2_DV_BT_CEA_1280X720P60 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
+                V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+                74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
+}
+
+#define V4L2_DV_BT_CEA_1920X1080P24 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+                V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+                74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
+}
+
+#define V4L2_DV_BT_CEA_1920X1080P25 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+                V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+                74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, 0) \
+}
+
+#define V4L2_DV_BT_CEA_1920X1080P30 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+                V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+                74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
+}
+
+#define V4L2_DV_BT_CEA_1920X1080I50 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
+                V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+                74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
+                V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
+}
+
+#define V4L2_DV_BT_CEA_1920X1080P50 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+                V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+                148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
+                V4L2_DV_BT_STD_CEA861, 0) \
+}
+
+#define V4L2_DV_BT_CEA_1920X1080I60 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
+                V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+                74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
+                V4L2_DV_BT_STD_CEA861, \
+                V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE) \
+}
+
+#define V4L2_DV_BT_CEA_1920X1080P60 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+                V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+                148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
+                V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
+                V4L2_DV_FL_CAN_REDUCE_FPS) \
+}
+
+
+/* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
+
+#define V4L2_DV_BT_DMT_640X350P85 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
+                31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \
+                V4L2_DV_BT_STD_DMT, 0) \
+}
+
+#define V4L2_DV_BT_DMT_640X400P85 { \
+        .type = V4L2_DV_BT_656_1120, \
+        V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
+                31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \
+                V4L2_DV_BT_STD_DMT, 0) \
+}
+
+#define V4L2_DV_BT_DMT_720X400P85 { \