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authorVinod Koul <vinod.koul@intel.com>2013-09-02 08:10:40 -0400
committerVinod Koul <vinod.koul@intel.com>2013-09-02 08:10:40 -0400
commit355cdafe14d72c616dc804a756f3af4f4df4fe8c (patch)
tree592ef60b65da9a539daa84f5d1cf52cf483b362b /include/linux
parent4770ee44359ad454992d544cf14f8d330a93f5ca (diff)
parentca38ff133eb85b64e62b508a7726ea0247edd359 (diff)
Merge branch 'topic/api_caps' into for-linus
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/dmaengine.h44
1 files changed, 44 insertions, 0 deletions
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index c271608e862e..13ac4f553227 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -370,6 +370,33 @@ struct dma_slave_config {
370 unsigned int slave_id; 370 unsigned int slave_id;
371}; 371};
372 372
373/* struct dma_slave_caps - expose capabilities of a slave channel only
374 *
375 * @src_addr_widths: bit mask of src addr widths the channel supports
376 * @dstn_addr_widths: bit mask of dstn addr widths the channel supports
377 * @directions: bit mask of slave direction the channel supported
378 * since the enum dma_transfer_direction is not defined as bits for each
379 * type of direction, the dma controller should fill (1 << <TYPE>) and same
380 * should be checked by controller as well
381 * @cmd_pause: true, if pause and thereby resume is supported
382 * @cmd_terminate: true, if terminate cmd is supported
383 *
384 * @max_sg_nr: maximum number of SG segments supported
385 * 0 for no maximum
386 * @max_sg_len: maximum length of a SG segment supported
387 * 0 for no maximum
388 */
389struct dma_slave_caps {
390 u32 src_addr_widths;
391 u32 dstn_addr_widths;
392 u32 directions;
393 bool cmd_pause;
394 bool cmd_terminate;
395
396 u32 max_sg_nr;
397 u32 max_sg_len;
398};
399
373static inline const char *dma_chan_name(struct dma_chan *chan) 400static inline const char *dma_chan_name(struct dma_chan *chan)
374{ 401{
375 return dev_name(&chan->dev->device); 402 return dev_name(&chan->dev->device);
@@ -532,6 +559,7 @@ struct dma_tx_state {
532 * struct with auxiliary transfer status information, otherwise the call 559 * struct with auxiliary transfer status information, otherwise the call
533 * will just return a simple status code 560 * will just return a simple status code
534 * @device_issue_pending: push pending transactions to hardware 561 * @device_issue_pending: push pending transactions to hardware
562 * @device_slave_caps: return the slave channel capabilities
535 */ 563 */
536struct dma_device { 564struct dma_device {
537 565
@@ -597,6 +625,7 @@ struct dma_device {
597 dma_cookie_t cookie, 625 dma_cookie_t cookie,
598 struct dma_tx_state *txstate); 626 struct dma_tx_state *txstate);
599 void (*device_issue_pending)(struct dma_chan *chan); 627 void (*device_issue_pending)(struct dma_chan *chan);
628 int (*device_slave_caps)(struct dma_chan *chan, struct dma_slave_caps *caps);
600}; 629};
601 630
602static inline int dmaengine_device_control(struct dma_chan *chan, 631static inline int dmaengine_device_control(struct dma_chan *chan,
@@ -670,6 +699,21 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
670 return chan->device->device_prep_interleaved_dma(chan, xt, flags); 699 return chan->device->device_prep_interleaved_dma(chan, xt, flags);
671} 700}
672 701
702static inline int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
703{
704 if (!chan || !caps)
705 return -EINVAL;
706
707 /* check if the channel supports slave transactions */
708 if (!test_bit(DMA_SLAVE, chan->device->cap_mask.bits))
709 return -ENXIO;
710
711 if (chan->device->device_slave_caps)
712 return chan->device->device_slave_caps(chan, caps);
713
714 return -ENXIO;
715}
716
673static inline int dmaengine_terminate_all(struct dma_chan *chan) 717static inline int dmaengine_terminate_all(struct dma_chan *chan)
674{ 718{
675 return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0); 719 return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);