[PATCH] I2O: changed I2O API to create I2O messages in kernel memory

Changed the I2O API to create I2O messages first in kernel memory and then
transfer it at once over the PCI bus instead of sending each quad-word over
the PCI bus.

Signed-off-by: Markus Lidel <Markus.Lidel@shadowconnect.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 552 insertions, 423 deletions

diff --git a/include/linux/i2o.h b/include/linux/i2o.h
index d79c8a4bc4f8..9e359a981221 100644
--- a/include/linux/i2o.h
+++ b/include/linux/i2o.h
@@ -30,6 +30,7 @@
 #include <linux/string.h>
 #include <linux/slab.h>
 #include <linux/workqueue.h>    /* work_struct */
+#include <linux/mempool.h>
 
 #include <asm/io.h>
 #include <asm/semaphore.h>      /* Needed for MUTEX init macros */
@@ -38,6 +39,355 @@
 #define I2O_QUEUE_EMPTY         0xffffffff
 
 /*
+ *      Cache strategies
+ */
+
+/*      The NULL strategy leaves everything up to the controller. This tends to be a
+ *      pessimal but functional choice.
+ */
+#define CACHE_NULL              0
+/*      Prefetch data when reading. We continually attempt to load the next 32 sectors
+ *      into the controller cache.
+ */
+#define CACHE_PREFETCH          1
+/*      Prefetch data when reading. We sometimes attempt to load the next 32 sectors
+ *      into the controller cache. When an I/O is less <= 8K we assume its probably
+ *      not sequential and don't prefetch (default)
+ */
+#define CACHE_SMARTFETCH        2
+/*      Data is written to the cache and then out on to the disk. The I/O must be
+ *      physically on the medium before the write is acknowledged (default without
+ *      NVRAM)
+ */
+#define CACHE_WRITETHROUGH      17
+/*      Data is written to the cache and then out on to the disk. The controller
+ *      is permitted to write back the cache any way it wants. (default if battery
+ *      backed NVRAM is present). It can be useful to set this for swap regardless of
+ *      battery state.
+ */
+#define CACHE_WRITEBACK         18
+/*      Optimise for under powered controllers, especially on RAID1 and RAID0. We
+ *      write large I/O's directly to disk bypassing the cache to avoid the extra
+ *      memory copy hits. Small writes are writeback cached
+ */
+#define CACHE_SMARTBACK         19
+/*      Optimise for under powered controllers, especially on RAID1 and RAID0. We
+ *      write large I/O's directly to disk bypassing the cache to avoid the extra
+ *      memory copy hits. Small writes are writethrough cached. Suitable for devices
+ *      lacking battery backup
+ */
+#define CACHE_SMARTTHROUGH      20
+
+/*
+ *      Ioctl structures
+ */
+
+#define         BLKI2OGRSTRAT   _IOR('2', 1, int)
+#define         BLKI2OGWSTRAT   _IOR('2', 2, int)
+#define         BLKI2OSRSTRAT   _IOW('2', 3, int)
+#define         BLKI2OSWSTRAT   _IOW('2', 4, int)
+
+/*
+ *      I2O Function codes
+ */
+
+/*
+ *      Executive Class
+ */
+#define I2O_CMD_ADAPTER_ASSIGN          0xB3
+#define I2O_CMD_ADAPTER_READ            0xB2
+#define I2O_CMD_ADAPTER_RELEASE         0xB5
+#define I2O_CMD_BIOS_INFO_SET           0xA5
+#define I2O_CMD_BOOT_DEVICE_SET         0xA7
+#define I2O_CMD_CONFIG_VALIDATE         0xBB
+#define I2O_CMD_CONN_SETUP              0xCA
+#define I2O_CMD_DDM_DESTROY             0xB1
+#define I2O_CMD_DDM_ENABLE              0xD5
+#define I2O_CMD_DDM_QUIESCE             0xC7
+#define I2O_CMD_DDM_RESET               0xD9
+#define I2O_CMD_DDM_SUSPEND             0xAF
+#define I2O_CMD_DEVICE_ASSIGN           0xB7
+#define I2O_CMD_DEVICE_RELEASE          0xB9
+#define I2O_CMD_HRT_GET                 0xA8
+#define I2O_CMD_ADAPTER_CLEAR           0xBE
+#define I2O_CMD_ADAPTER_CONNECT         0xC9
+#define I2O_CMD_ADAPTER_RESET           0xBD
+#define I2O_CMD_LCT_NOTIFY              0xA2
+#define I2O_CMD_OUTBOUND_INIT           0xA1
+#define I2O_CMD_PATH_ENABLE             0xD3
+#define I2O_CMD_PATH_QUIESCE            0xC5
+#define I2O_CMD_PATH_RESET              0xD7
+#define I2O_CMD_STATIC_MF_CREATE        0xDD
+#define I2O_CMD_STATIC_MF_RELEASE       0xDF
+#define I2O_CMD_STATUS_GET              0xA0
+#define I2O_CMD_SW_DOWNLOAD             0xA9
+#define I2O_CMD_SW_UPLOAD               0xAB
+#define I2O_CMD_SW_REMOVE               0xAD
+#define I2O_CMD_SYS_ENABLE              0xD1
+#define I2O_CMD_SYS_MODIFY              0xC1
+#define I2O_CMD_SYS_QUIESCE             0xC3
+#define I2O_CMD_SYS_TAB_SET             0xA3
+
+/*
+ * Utility Class
+ */
+#define I2O_CMD_UTIL_NOP                0x00
+#define I2O_CMD_UTIL_ABORT              0x01
+#define I2O_CMD_UTIL_CLAIM              0x09
+#define I2O_CMD_UTIL_RELEASE            0x0B
+#define I2O_CMD_UTIL_PARAMS_GET         0x06
+#define I2O_CMD_UTIL_PARAMS_SET         0x05
+#define I2O_CMD_UTIL_EVT_REGISTER       0x13
+#define I2O_CMD_UTIL_EVT_ACK            0x14
+#define I2O_CMD_UTIL_CONFIG_DIALOG      0x10
+#define I2O_CMD_UTIL_DEVICE_RESERVE     0x0D
+#define I2O_CMD_UTIL_DEVICE_RELEASE     0x0F
+#define I2O_CMD_UTIL_LOCK               0x17
+#define I2O_CMD_UTIL_LOCK_RELEASE       0x19
+#define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15
+
+/*
+ * SCSI Host Bus Adapter Class
+ */
+#define I2O_CMD_SCSI_EXEC               0x81
+#define I2O_CMD_SCSI_ABORT              0x83
+#define I2O_CMD_SCSI_BUSRESET           0x27
+
+/*
+ * Bus Adapter Class
+ */
+#define I2O_CMD_BUS_ADAPTER_RESET       0x85
+#define I2O_CMD_BUS_RESET               0x87
+#define I2O_CMD_BUS_SCAN                0x89
+#define I2O_CMD_BUS_QUIESCE             0x8b
+
+/*
+ * Random Block Storage Class
+ */
+#define I2O_CMD_BLOCK_READ              0x30
+#define I2O_CMD_BLOCK_WRITE             0x31
+#define I2O_CMD_BLOCK_CFLUSH            0x37
+#define I2O_CMD_BLOCK_MLOCK             0x49
+#define I2O_CMD_BLOCK_MUNLOCK           0x4B
+#define I2O_CMD_BLOCK_MMOUNT            0x41
+#define I2O_CMD_BLOCK_MEJECT            0x43
+#define I2O_CMD_BLOCK_POWER             0x70
+
+#define I2O_CMD_PRIVATE                 0xFF
+
+/* Command status values  */
+
+#define I2O_CMD_IN_PROGRESS     0x01
+#define I2O_CMD_REJECTED        0x02
+#define I2O_CMD_FAILED          0x03
+#define I2O_CMD_COMPLETED       0x04
+
+/* I2O API function return values */
+
+#define I2O_RTN_NO_ERROR                        0
+#define I2O_RTN_NOT_INIT                        1
+#define I2O_RTN_FREE_Q_EMPTY                    2
+#define I2O_RTN_TCB_ERROR                       3
+#define I2O_RTN_TRANSACTION_ERROR               4
+#define I2O_RTN_ADAPTER_ALREADY_INIT            5
+#define I2O_RTN_MALLOC_ERROR                    6
+#define I2O_RTN_ADPTR_NOT_REGISTERED            7
+#define I2O_RTN_MSG_REPLY_TIMEOUT               8
+#define I2O_RTN_NO_STATUS                       9
+#define I2O_RTN_NO_FIRM_VER                     10
+#define I2O_RTN_NO_LINK_SPEED                   11
+
+/* Reply message status defines for all messages */
+
+#define I2O_REPLY_STATUS_SUCCESS                        0x00
+#define I2O_REPLY_STATUS_ABORT_DIRTY                    0x01
+#define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER         0x02
+#define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER         0x03
+#define I2O_REPLY_STATUS_ERROR_DIRTY                    0x04
+#define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER         0x05
+#define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER         0x06
+#define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY            0x08
+#define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09
+#define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A
+#define I2O_REPLY_STATUS_TRANSACTION_ERROR              0x0B
+#define I2O_REPLY_STATUS_PROGRESS_REPORT                0x80
+
+/* Status codes and Error Information for Parameter functions */
+
+#define I2O_PARAMS_STATUS_SUCCESS               0x00
+#define I2O_PARAMS_STATUS_BAD_KEY_ABORT         0x01
+#define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE      0x02
+#define I2O_PARAMS_STATUS_BUFFER_FULL           0x03
+#define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL      0x04
+#define I2O_PARAMS_STATUS_FIELD_UNREADABLE      0x05
+#define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE     0x06
+#define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS   0x07
+#define I2O_PARAMS_STATUS_INVALID_GROUP_ID      0x08
+#define I2O_PARAMS_STATUS_INVALID_OPERATION     0x09
+#define I2O_PARAMS_STATUS_NO_KEY_FIELD          0x0A
+#define I2O_PARAMS_STATUS_NO_SUCH_FIELD         0x0B
+#define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP     0x0C
+#define I2O_PARAMS_STATUS_OPERATION_ERROR       0x0D
+#define I2O_PARAMS_STATUS_SCALAR_ERROR          0x0E
+#define I2O_PARAMS_STATUS_TABLE_ERROR           0x0F
+#define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE      0x10
+
+/* DetailedStatusCode defines for Executive, DDM, Util and Transaction error
+ * messages: Table 3-2 Detailed Status Codes.*/
+
+#define I2O_DSC_SUCCESS                        0x0000
+#define I2O_DSC_BAD_KEY                        0x0002
+#define I2O_DSC_TCL_ERROR                      0x0003
+#define I2O_DSC_REPLY_BUFFER_FULL              0x0004
+#define I2O_DSC_NO_SUCH_PAGE                   0x0005
+#define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT     0x0006
+#define I2O_DSC_INSUFFICIENT_RESOURCE_HARD     0x0007
+#define I2O_DSC_CHAIN_BUFFER_TOO_LARGE         0x0009
+#define I2O_DSC_UNSUPPORTED_FUNCTION           0x000A
+#define I2O_DSC_DEVICE_LOCKED                  0x000B
+#define I2O_DSC_DEVICE_RESET                   0x000C
+#define I2O_DSC_INAPPROPRIATE_FUNCTION         0x000D
+#define I2O_DSC_INVALID_INITIATOR_ADDRESS      0x000E
+#define I2O_DSC_INVALID_MESSAGE_FLAGS          0x000F
+#define I2O_DSC_INVALID_OFFSET                 0x0010
+#define I2O_DSC_INVALID_PARAMETER              0x0011
+#define I2O_DSC_INVALID_REQUEST                0x0012
+#define I2O_DSC_INVALID_TARGET_ADDRESS         0x0013
+#define I2O_DSC_MESSAGE_TOO_LARGE              0x0014
+#define I2O_DSC_MESSAGE_TOO_SMALL              0x0015
+#define I2O_DSC_MISSING_PARAMETER              0x0016
+#define I2O_DSC_TIMEOUT                        0x0017
+#define I2O_DSC_UNKNOWN_ERROR                  0x0018
+#define I2O_DSC_UNKNOWN_FUNCTION               0x0019
+#define I2O_DSC_UNSUPPORTED_VERSION            0x001A
+#define I2O_DSC_DEVICE_BUSY                    0x001B
+#define I2O_DSC_DEVICE_NOT_AVAILABLE           0x001C
+
+/* DetailedStatusCode defines for Block Storage Operation: Table 6-7 Detailed
+   Status Codes.*/
+
+#define I2O_BSA_DSC_SUCCESS               0x0000
+#define I2O_BSA_DSC_MEDIA_ERROR           0x0001
+#define I2O_BSA_DSC_ACCESS_ERROR          0x0002
+#define I2O_BSA_DSC_DEVICE_FAILURE        0x0003
+#define I2O_BSA_DSC_DEVICE_NOT_READY      0x0004
+#define I2O_BSA_DSC_MEDIA_NOT_PRESENT     0x0005
+#define I2O_BSA_DSC_MEDIA_LOCKED          0x0006
+#define I2O_BSA_DSC_MEDIA_FAILURE         0x0007
+#define I2O_BSA_DSC_PROTOCOL_FAILURE      0x0008
+#define I2O_BSA_DSC_BUS_FAILURE           0x0009
+#define I2O_BSA_DSC_ACCESS_VIOLATION      0x000A
+#define I2O_BSA_DSC_WRITE_PROTECTED       0x000B
+#define I2O_BSA_DSC_DEVICE_RESET          0x000C
+#define I2O_BSA_DSC_VOLUME_CHANGED        0x000D
+#define I2O_BSA_DSC_TIMEOUT               0x000E
+
+/* FailureStatusCodes, Table 3-3 Message Failure Codes */
+
+#define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED             0x81
+#define I2O_FSC_TRANSPORT_SERVICE_TERMINATED            0x82
+#define I2O_FSC_TRANSPORT_CONGESTION                    0x83
+#define I2O_FSC_TRANSPORT_FAILURE                       0x84
+#define I2O_FSC_TRANSPORT_STATE_ERROR                   0x85
+#define I2O_FSC_TRANSPORT_TIME_OUT                      0x86
+#define I2O_FSC_TRANSPORT_ROUTING_FAILURE               0x87
+#define I2O_FSC_TRANSPORT_INVALID_VERSION               0x88
+#define I2O_FSC_TRANSPORT_INVALID_OFFSET                0x89
+#define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS             0x8A
+#define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL               0x8B
+#define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE               0x8C
+#define I2O_FSC_TRANSPORT_INVALID_TARGET_ID             0x8D
+#define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID          0x8E
+#define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT     0x8F
+#define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE               0xFF
+
+/* Device Claim Types */
+#define I2O_CLAIM_PRIMARY                                       0x01000000
+#define I2O_CLAIM_MANAGEMENT                                    0x02000000
+#define I2O_CLAIM_AUTHORIZED                                    0x03000000
+#define I2O_CLAIM_SECONDARY                                     0x04000000
+
+/* Message header defines for VersionOffset */
+#define I2OVER15        0x0001
+#define I2OVER20        0x0002
+
+/* Default is 1.5 */
+#define I2OVERSION      I2OVER15
+
+#define SGL_OFFSET_0    I2OVERSION
+#define SGL_OFFSET_4    (0x0040 | I2OVERSION)
+#define SGL_OFFSET_5    (0x0050 | I2OVERSION)
+#define SGL_OFFSET_6    (0x0060 | I2OVERSION)
+#define SGL_OFFSET_7    (0x0070 | I2OVERSION)
+#define SGL_OFFSET_8    (0x0080 | I2OVERSION)
+#define SGL_OFFSET_9    (0x0090 | I2OVERSION)
+#define SGL_OFFSET_10   (0x00A0 | I2OVERSION)
+#define SGL_OFFSET_11   (0x00B0 | I2OVERSION)
+#define SGL_OFFSET_12   (0x00C0 | I2OVERSION)
+#define SGL_OFFSET(x)   (((x)<<4) | I2OVERSION)
+
+/* Transaction Reply Lists (TRL) Control Word structure */
+#define TRL_SINGLE_FIXED_LENGTH         0x00
+#define TRL_SINGLE_VARIABLE_LENGTH      0x40
+#define TRL_MULTIPLE_FIXED_LENGTH       0x80
+
+ /* msg header defines for MsgFlags */
+#define MSG_STATIC      0x0100
+#define MSG_64BIT_CNTXT 0x0200
+#define MSG_MULTI_TRANS 0x1000
+#define MSG_FAIL        0x2000
+#define MSG_FINAL       0x4000
+#define MSG_REPLY       0x8000
+
+ /* minimum size msg */
+#define THREE_WORD_MSG_SIZE     0x00030000
+#define FOUR_WORD_MSG_SIZE      0x00040000
+#define FIVE_WORD_MSG_SIZE      0x00050000
+#define SIX_WORD_MSG_SIZE       0x00060000
+#define SEVEN_WORD_MSG_SIZE     0x00070000
+#define EIGHT_WORD_MSG_SIZE     0x00080000
+#define NINE_WORD_MSG_SIZE      0x00090000
+#define TEN_WORD_MSG_SIZE       0x000A0000
+#define ELEVEN_WORD_MSG_SIZE    0x000B0000
+#define I2O_MESSAGE_SIZE(x)     ((x)<<16)
+
+/* special TID assignments */
+#define ADAPTER_TID             0
+#define HOST_TID                1
+
+/* outbound queue defines */
+#define I2O_MAX_OUTBOUND_MSG_FRAMES     128
+#define I2O_OUTBOUND_MSG_FRAME_SIZE     128     /* in 32-bit words */
+
+/* inbound queue definitions */
+#define I2O_MSG_INPOOL_MIN              32
+#define I2O_INBOUND_MSG_FRAME_SIZE      128     /* in 32-bit words */
+
+#define I2O_POST_WAIT_OK        0
+#define I2O_POST_WAIT_TIMEOUT   -ETIMEDOUT
+
+#define I2O_CONTEXT_LIST_MIN_LENGTH     15
+#define I2O_CONTEXT_LIST_USED           0x01
+#define I2O_CONTEXT_LIST_DELETED        0x02
+
+/* timeouts */
+#define I2O_TIMEOUT_INIT_OUTBOUND_QUEUE 15
+#define I2O_TIMEOUT_MESSAGE_GET         5
+#define I2O_TIMEOUT_RESET               30
+#define I2O_TIMEOUT_STATUS_GET          5
+#define I2O_TIMEOUT_LCT_GET             360
+#define I2O_TIMEOUT_SCSI_SCB_ABORT      240
+
+/* retries */
+#define I2O_HRT_GET_TRIES               3
+#define I2O_LCT_GET_TRIES               3
+
+/* defines for max_sectors and max_phys_segments */
+#define I2O_MAX_SECTORS                 1024
+#define I2O_MAX_SECTORS_LIMITED         256
+#define I2O_MAX_PHYS_SEGMENTS           MAX_PHYS_SEGMENTS
+
+/*
  *      Message structures
  */
 struct i2o_message {
@@ -58,6 +408,12 @@ struct i2o_message {
         u32 body[0];
 };
 
+/* MFA and I2O message used by mempool */
+struct i2o_msg_mfa {
+        u32 mfa;                /* MFA returned by the controller */
+        struct i2o_message msg; /* I2O message */
+};
+
 /*
  *      Each I2O device entity has one of these. There is one per device.
  */
@@ -130,6 +486,15 @@ struct i2o_dma {
 };
 
 /*
+ *      Contains slab cache and mempool information
+ */
+struct i2o_pool {
+        char *name;
+        kmem_cache_t *slab;
+        mempool_t *mempool;
+};
+
+/*
  *      Contains IO mapped address information
  */
 struct i2o_io {
@@ -174,8 +539,6 @@ struct i2o_controller {
         void __iomem *irq_status;       /* Interrupt status register address */
         void __iomem *irq_mask; /* Interrupt mask register address */
 
-        /* Dynamic LCT related data */
-
         struct i2o_dma status;  /* IOP status block */
 
         struct i2o_dma hrt;     /* HW Resource Table */
@@ -188,6 +551,8 @@ struct i2o_controller {
         struct i2o_io in_queue; /* inbound message queue Host->IOP */
         struct i2o_dma out_queue;       /* outbound message queue IOP->Host */
 
+        struct i2o_pool in_msg; /* mempool for inbound messages */
+
         unsigned int battery:1; /* Has a battery backup */
         unsigned int io_alloc:1;        /* An I/O resource was allocated */
         unsigned int mem_alloc:1;       /* A memory resource was allocated */
@@ -247,16 +612,13 @@ struct i2o_sys_tbl {
 extern struct list_head i2o_controllers;
 
 /* Message functions */
-static inline u32 i2o_msg_get(struct i2o_controller *,
-                              struct i2o_message __iomem **);
-extern u32 i2o_msg_get_wait(struct i2o_controller *,
-                            struct i2o_message __iomem **, int);
-static inline void i2o_msg_post(struct i2o_controller *, u32);
-static inline int i2o_msg_post_wait(struct i2o_controller *, u32,
-                                    unsigned long);
-extern int i2o_msg_post_wait_mem(struct i2o_controller *, u32, unsigned long,
-                                 struct i2o_dma *);
-extern void i2o_msg_nop(struct i2o_controller *, u32);
+static inline struct i2o_message *i2o_msg_get(struct i2o_controller *);
+extern struct i2o_message *i2o_msg_get_wait(struct i2o_controller *, int);
+static inline void i2o_msg_post(struct i2o_controller *, struct i2o_message *);
+static inline int i2o_msg_post_wait(struct i2o_controller *,
+                                    struct i2o_message *, unsigned long);
+extern int i2o_msg_post_wait_mem(struct i2o_controller *, struct i2o_message *,
+                                 unsigned long, struct i2o_dma *);
 static inline void i2o_flush_reply(struct i2o_controller *, u32);
 
 /* IOP functions */
@@ -384,10 +746,10 @@ static inline u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size)
 static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
                                             size_t size,
                                             enum dma_data_direction direction,
-                                            u32 __iomem ** sg_ptr)
+                                            u32 ** sg_ptr)
 {
         u32 sg_flags;
-        u32 __iomem *mptr = *sg_ptr;
+        u32 *mptr = *sg_ptr;
         dma_addr_t dma_addr;
 
         switch (direction) {
@@ -405,16 +767,16 @@ static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
         if (!dma_mapping_error(dma_addr)) {
 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
                 if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
-                        writel(0x7C020002, mptr++);
-                        writel(PAGE_SIZE, mptr++);
+                        *mptr++ = cpu_to_le32(0x7C020002);
+                        *mptr++ = cpu_to_le32(PAGE_SIZE);
                 }
 #endif
 
-                writel(sg_flags | size, mptr++);
-                writel(i2o_dma_low(dma_addr), mptr++);
+                *mptr++ = cpu_to_le32(sg_flags | size);
+                *mptr++ = cpu_to_le32(i2o_dma_low(dma_addr));
 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
                 if ((sizeof(dma_addr_t) > 4) && c->pae_support)
-                        writel(i2o_dma_high(dma_addr), mptr++);
+                        *mptr++ = cpu_to_le32(i2o_dma_high(dma_addr));
 #endif
                 *sg_ptr = mptr;
         }
@@ -439,10 +801,10 @@ static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
 static inline int i2o_dma_map_sg(struct i2o_controller *c,
                                  struct scatterlist *sg, int sg_count,
                                  enum dma_data_direction direction,
-                                 u32 __iomem ** sg_ptr)
+                                 u32 ** sg_ptr)
 {
         u32 sg_flags;
-        u32 __iomem *mptr = *sg_ptr;
+        u32 *mptr = *sg_ptr;
 
         switch (direction) {
         case DMA_TO_DEVICE:
@@ -461,19 +823,19 @@ static inline int i2o_dma_map_sg(struct i2o_controller *c,
 
 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
         if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
-                writel(0x7C020002, mptr++);
-                writel(PAGE_SIZE, mptr++);
+                *mptr++ = cpu_to_le32(0x7C020002);
+                *mptr++ = cpu_to_le32(PAGE_SIZE);
         }
 #endif
 
         while (sg_count-- > 0) {
                 if (!sg_count)
                         sg_flags |= 0xC0000000;
-                writel(sg_flags | sg_dma_len(sg), mptr++);
-                writel(i2o_dma_low(sg_dma_address(sg)), mptr++);
+                *mptr++ = cpu_to_le32(sg_flags | sg_dma_len(sg));
+                *mptr++ = cpu_to_le32(i2o_dma_low(sg_dma_address(sg)));
 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
                 if ((sizeof(dma_addr_t) > 4) && c->pae_support)
-                        writel(i2o_dma_high(sg_dma_address(sg)), mptr++);
+                        *mptr++ = cpu_to_le32(i2o_dma_high(sg_dma_address(sg)));
 #endif
                 sg++;
         }
@@ -563,6 +925,64 @@ static inline int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
         return 0;
 };
 
+/*
+ *      i2o_pool_alloc - Allocate an slab cache and mempool
+ *      @mempool: pointer to struct i2o_pool to write data into.
+ *      @name: name which is used to identify cache
+ *      @size: size of each object
+ *      @min_nr: minimum number of objects
+ *
+ *      First allocates a slab cache with name and size. Then allocates a
+ *      mempool which uses the slab cache for allocation and freeing.
+ *
+ *      Returns 0 on success or negative error code on failure.
+ */
+static inline int i2o_pool_alloc(struct i2o_pool *pool, const char *name,
+                                 size_t size, int min_nr)
+{
+        pool->name = kmalloc(strlen(name) + 1, GFP_KERNEL);
+        if (!pool->name)
+                goto exit;
+        strcpy(pool->name, name);
+
+        pool->slab =
+            kmem_cache_create(pool->name, size, 0, SLAB_HWCACHE_ALIGN, NULL,
+                              NULL);
+        if (!pool->slab)
+                goto free_name;
+
+        pool->mempool =
+            mempool_create(min_nr, mempool_alloc_slab, mempool_free_slab,
+                           pool->slab);
+        if (!pool->mempool)
+                goto free_slab;
+
+        return 0;
+
+      free_slab:
+        kmem_cache_destroy(pool->slab);
+
+      free_name:
+        kfree(pool->name);
+
+      exit:
+        return -ENOMEM;
+};
+
+/*
+ *      i2o_pool_free - Free slab cache and mempool again
+ *      @mempool: pointer to struct i2o_pool which should be freed
+ *
+ *      Note that you have to return all objects to the mempool again before
+ *      calling i2o_pool_free().
+ */
+static inline void i2o_pool_free(struct i2o_pool *pool)
+{
+        mempool_destroy(pool->mempool);
+        kmem_cache_destroy(pool->slab);
+        kfree(pool->name);
+};
+
 /* I2O driver (OSM) functions */
 extern int i2o_driver_register(struct i2o_driver *);
 extern void i2o_driver_unregister(struct i2o_driver *);
@@ -638,39 +1058,89 @@ extern int i2o_exec_lct_get(struct i2o_controller *);
 #define kobj_to_i2o_device(kobj) to_i2o_device(container_of(kobj, struct device, kobj))
 
 /**
+ *      i2o_out_to_virt - Turn an I2O message to a virtual address
+ *      @c: controller
+ *      @m: message engine value
+ *
+ *      Turn a receive message from an I2O controller bus address into
+ *      a Linux virtual address. The shared page frame is a linear block
+ *      so we simply have to shift the offset. This function does not
+ *      work for sender side messages as they are ioremap objects
+ *      provided by the I2O controller.
+ */
+static inline struct i2o_message *i2o_msg_out_to_virt(struct i2o_controller *c,
+                                                      u32 m)
+{
+        BUG_ON(m < c->out_queue.phys
+               || m >= c->out_queue.phys + c->out_queue.len);
+
+        return c->out_queue.virt + (m - c->out_queue.phys);
+};
+
+/**
+ *      i2o_msg_in_to_virt - Turn an I2O message to a virtual address
+ *      @c: controller
+ *      @m: message engine value
+ *
+ *      Turn a send message from an I2O controller bus address into
+ *      a Linux virtual address. The shared page frame is a linear block
+ *      so we simply have to shift the offset. This function does not
+ *      work for receive side messages as they are kmalloc objects
+ *      in a different pool.
+ */
+static inline struct i2o_message __iomem *i2o_msg_in_to_virt(struct
+                                                             i2o_controller *c,
+                                                             u32 m)
+{
+        return c->in_queue.virt + m;
+};
+
+/**
  *      i2o_msg_get - obtain an I2O message from the IOP
  *      @c: I2O controller
- *      @msg: pointer to a I2O message pointer
  *
- *      This function tries to get a message slot. If no message slot is
+ *      This function tries to get a message frame. If no message frame is
  *      available do not wait until one is availabe (see also i2o_msg_get_wait).
+ *      The returned pointer to the message frame is not in I/O memory, it is
+ *      allocated from a mempool. But because a MFA is allocated from the
+ *      controller too it is guaranteed that i2o_msg_post() will never fail.
  *
- *      On a success the message is returned and the pointer to the message is
- *      set in msg. The returned message is the physical page frame offset
- *      address from the read port (see the i2o spec). If no message is
- *      available returns I2O_QUEUE_EMPTY and msg is leaved untouched.
+ *      On a success a pointer to the message frame is returned. If the message
+ *      queue is empty -EBUSY is returned and if no memory is available -ENOMEM
+ *      is returned.
  */
-static inline u32 i2o_msg_get(struct i2o_controller *c,
-                              struct i2o_message __iomem ** msg)
+static inline struct i2o_message *i2o_msg_get(struct i2o_controller *c)
 {
-        u32 m = readl(c->in_port);
-
-        if (m != I2O_QUEUE_EMPTY)
-                *msg = c->in_queue.virt + m;
+        struct i2o_msg_mfa *mmsg = mempool_alloc(c->in_msg.mempool, GFP_ATOMIC);
+        if (!mmsg)
+                return ERR_PTR(-ENOMEM);
+
+        mmsg->mfa = readl(c->in_port);
+        if (mmsg->mfa == I2O_QUEUE_EMPTY) {
+                mempool_free(mmsg, c->in_msg.mempool);
+                return ERR_PTR(-EBUSY);
+        }
 
-        return m;
+        return &mmsg->msg;
 };
 
 /**
  *      i2o_msg_post - Post I2O message to I2O controller
  *      @c: I2O controller to which the message should be send
- *      @m: the message identifier
+ *      @msg: message returned by i2o_msg_get()
  *
- *      Post the message to the I2O controller.
+ *      Post the message to the I2O controller and return immediately.
  */
-static inline void i2o_msg_post(struct i2o_controller *c, u32 m)
+static inline void i2o_msg_post(struct i2o_controller *c,
+                                struct i2o_message *msg)
 {
-        writel(m, c->in_port);
+        struct i2o_msg_mfa *mmsg;
+
+        mmsg = container_of(msg, struct i2o_msg_mfa, msg);
+        memcpy_toio(i2o_msg_in_to_virt(c, mmsg->mfa), msg,
+                    (le32_to_cpu(msg->u.head[0]) >> 16) << 2);
+        writel(mmsg->mfa, c->in_port);
+        mempool_free(mmsg, c->in_msg.mempool);
 };
 
 /**
@@ -685,62 +1155,66 @@ static inline void i2o_msg_post(struct i2o_controller *c, u32 m)
  *
  *      Returns 0 on success or negative error code on failure.
  */
-static inline int i2o_msg_post_wait(struct i2o_controller *c, u32 m,
+static inline int i2o_msg_post_wait(struct i2o_controller *c,
+                                    struct i2o_message *msg,
                                     unsigned long timeout)
 {
-        return i2o_msg_post_wait_mem(c, m, timeout, NULL);
+        return i2o_msg_post_wait_mem(c, msg, timeout, NULL);
 };
 
 /**
- *      i2o_flush_reply - Flush reply from I2O controller
- *      @c: I2O controller
- *      @m: the message identifier
+ *      i2o_msg_nop_mfa - Returns a fetched MFA back to the controller
+ *      @c: I2O controller from which the MFA was fetched
+ *      @mfa: MFA which should be returned
  *
- *      The I2O controller must be informed that the reply message is not needed
- *      anymore. If you forget to flush the reply, the message frame can't be
- *      used by the controller anymore and is therefore lost.
+ *      This function must be used for preserved messages, because i2o_msg_nop()
+ *      also returns the allocated memory back to the msg_pool mempool.
  */
-static inline void i2o_flush_reply(struct i2o_controller *c, u32 m)
+static inline void i2o_msg_nop_mfa(struct i2o_controller *c, u32 mfa)
 {
-        writel(m, c->out_port);
+        struct i2o_message __iomem *msg;
+        u32 nop[3] = {
+                THREE_WORD_MSG_SIZE | SGL_OFFSET_0,
+                I2O_CMD_UTIL_NOP << 24 | HOST_TID << 12 | ADAPTER_TID,
+                0x00000000
+        };
+
+        msg = i2o_msg_in_to_virt(c, mfa);
+        memcpy_toio(msg, nop, sizeof(nop));
+        writel(mfa, c->in_port);
 };
 
 /**
- *      i2o_out_to_virt - Turn an I2O message to a virtual address
- *      @c: controller
- *      @m: message engine value
+ *      i2o_msg_nop - Returns a message which is not used
+ *      @c: I2O controller from which the message was created
+ *      @msg: message which should be returned
  *
- *      Turn a receive message from an I2O controller bus address into
- *      a Linux virtual address. The shared page frame is a linear block
- *      so we simply have to shift the offset. This function does not
- *      work for sender side messages as they are ioremap objects
- *      provided by the I2O controller.
+ *      If you fetch a message via i2o_msg_get, and can't use it, you must
+ *      return the message with this function. Otherwise the MFA is lost as well
+ *      as the allocated memory from the mempool.
  */
-static inline struct i2o_message *i2o_msg_out_to_virt(struct i2o_controller *c,
-                                                      u32 m)
+static inline void i2o_msg_nop(struct i2o_controller *c,
+                               struct i2o_message *msg)
 {
-        BUG_ON(m < c->out_queue.phys
-               || m >= c->out_queue.phys + c->out_queue.len);
+        struct i2o_msg_mfa *mmsg;
+        mmsg = container_of(msg, struct i2o_msg_mfa, msg);
 
-        return c->out_queue.virt + (m - c->out_queue.phys);
+        i2o_msg_nop_mfa(c, mmsg->mfa);
+        mempool_free(mmsg, c->in_msg.mempool);
 };
 
 /**
- *      i2o_msg_in_to_virt - Turn an I2O message to a virtual address
- *      @c: controller
- *      @m: message engine value
+ *      i2o_flush_reply - Flush reply from I2O controller
+ *      @c: I2O controller
+ *      @m: the message identifier
  *
- *      Turn a send message from an I2O controller bus address into
- *      a Linux virtual address. The shared page frame is a linear block
- *      so we simply have to shift the offset. This function does not
- *      work for receive side messages as they are kmalloc objects
- *      in a different pool.
+ *      The I2O controller must be informed that the reply message is not needed
+ *      anymore. If you forget to flush the reply, the message frame can't be
+ *      used by the controller anymore and is therefore lost.
  */
-static inline struct i2o_message __iomem *i2o_msg_in_to_virt(struct
-                                                             i2o_controller *c,
-                                                             u32 m)
+static inline void i2o_flush_reply(struct i2o_controller *c, u32 m)
 {
-        return c->in_queue.virt + m;
+        writel(m, c->out_port);
 };
 
 /*
@@ -779,350 +1253,5 @@ extern void i2o_dump_message(struct i2o_message *);
 extern void i2o_dump_hrt(struct i2o_controller *c);
 extern void i2o_debug_state(struct i2o_controller *c);
 
-/*
- *      Cache strategies
- */
-
-/*      The NULL strategy leaves everything up to the controller. This tends to be a
- *      pessimal but functional choice.
- */
-#define CACHE_NULL              0
-/*      Prefetch data when reading. We continually attempt to load the next 32 sectors
- *      into the controller cache.
- */
-#define CACHE_PREFETCH          1
-/*      Prefetch data when reading. We sometimes attempt to load the next 32 sectors
- *      into the controller cache. When an I/O is less <= 8K we assume its probably
- *      not sequential and don't prefetch (default)
- */
-#define CACHE_SMARTFETCH        2
-/*      Data is written to the cache and then out on to the disk. The I/O must be
- *      physically on the medium before the write is acknowledged (default without
- *      NVRAM)
- */
-#define CACHE_WRITETHROUGH      17
-/*      Data is written to the cache and then out on to the disk. The controller
- *      is permitted to write back the cache any way it wants. (default if battery
- *      backed NVRAM is present). It can be useful to set this for swap regardless of
- *      battery state.
- */
-#define CACHE_WRITEBACK         18
-/*      Optimise for under powered controllers, especially on RAID1 and RAID0. We
- *      write large I/O's directly to disk bypassing the cache to avoid the extra
- *      memory copy hits. Small writes are writeback cached
- */
-#define CACHE_SMARTBACK         19
-/*      Optimise for under powered controllers, especially on RAID1 and RAID0. We
- *      write large I/O's directly to disk bypassing the cache to avoid the extra
- *      memory copy hits. Small writes are writethrough cached. Suitable for devices
- *      lacking battery backup
- */
-#define CACHE_SMARTTHROUGH      20
-
-/*
- *      Ioctl structures
- */
-
-#define         BLKI2OGRSTRAT   _IOR('2', 1, int)
-#define         BLKI2OGWSTRAT   _IOR('2', 2, int)
-#define         BLKI2OSRSTRAT   _IOW('2', 3, int)
-#define         BLKI2OSWSTRAT   _IOW('2', 4, int)
-
-/*
- *      I2O Function codes
- */
-
-/*
- *      Executive Class
- */
-#define I2O_CMD_ADAPTER_ASSIGN          0xB3
-#define I2O_CMD_ADAPTER_READ            0xB2
-#define I2O_CMD_ADAPTER_RELEASE         0xB5
-#define I2O_CMD_BIOS_INFO_SET           0xA5
-#define I2O_CMD_BOOT_DEVICE_SET         0xA7
-#define I2O_CMD_CONFIG_VALIDATE         0xBB
-#define I2O_CMD_CONN_SETUP              0xCA
-#define I2O_CMD_DDM_DESTROY             0xB1
-#define I2O_CMD_DDM_ENABLE              0xD5
-#define I2O_CMD_DDM_QUIESCE             0xC7
-#define I2O_CMD_DDM_RESET               0xD9
-#define I2O_CMD_DDM_SUSPEND             0xAF
-#define I2O_CMD_DEVICE_ASSIGN           0xB7
-#define I2O_CMD_DEVICE_RELEASE          0xB9
-#define I2O_CMD_HRT_GET                 0xA8
-#define I2O_CMD_ADAPTER_CLEAR           0xBE
-#define I2O_CMD_ADAPTER_CONNECT         0xC9
-#define I2O_CMD_ADAPTER_RESET           0xBD
-#define I2O_CMD_LCT_NOTIFY              0xA2
-#define I2O_CMD_OUTBOUND_INIT           0xA1
-#define I2O_CMD_PATH_ENABLE             0xD3
-#define I2O_CMD_PATH_QUIESCE            0xC5
-#define I2O_CMD_PATH_RESET              0xD7
-#define I2O_CMD_STATIC_MF_CREATE        0xDD
-#define I2O_CMD_STATIC_MF_RELEASE       0xDF
-#define I2O_CMD_STATUS_GET              0xA0
-#define I2O_CMD_SW_DOWNLOAD             0xA9
-#define I2O_CMD_SW_UPLOAD               0xAB
-#define I2O_CMD_SW_REMOVE               0xAD
-#define I2O_CMD_SYS_ENABLE              0xD1
-#define I2O_CMD_SYS_MODIFY              0xC1
-#define I2O_CMD_SYS_QUIESCE             0xC3
-#define I2O_CMD_SYS_TAB_SET             0xA3
-
-/*
- * Utility Class
- */
-#define I2O_CMD_UTIL_NOP                0x00
-#define I2O_CMD_UTIL_ABORT              0x01
-#define I2O_CMD_UTIL_CLAIM              0x09
-#define I2O_CMD_UTIL_RELEASE            0x0B
-#define I2O_CMD_UTIL_PARAMS_GET         0x06
-#define I2O_CMD_UTIL_PARAMS_SET         0x05
-#define I2O_CMD_UTIL_EVT_REGISTER       0x13
-#define I2O_CMD_UTIL_EVT_ACK            0x14
-#define I2O_CMD_UTIL_CONFIG_DIALOG      0x10
-#define I2O_CMD_UTIL_DEVICE_RESERVE     0x0D
-#define I2O_CMD_UTIL_DEVICE_RELEASE     0x0F
-#define I2O_CMD_UTIL_LOCK               0x17
-#define I2O_CMD_UTIL_LOCK_RELEASE       0x19
-#define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15
-
-/*
- * SCSI Host Bus Adapter Class
- */
-#define I2O_CMD_SCSI_EXEC               0x81
-#define I2O_CMD_SCSI_ABORT              0x83
-#define I2O_CMD_SCSI_BUSRESET           0x27
-
-/*
- * Bus Adapter Class
- */
-#define I2O_CMD_BUS_ADAPTER_RESET       0x85
-#define I2O_CMD_BUS_RESET               0x87
-#define I2O_CMD_BUS_SCAN                0x89
-#define I2O_CMD_BUS_QUIESCE             0x8b
-
-/*
- * Random Block Storage Class
- */
-#define I2O_CMD_BLOCK_READ              0x30
-#define I2O_CMD_BLOCK_WRITE             0x31
-#define I2O_CMD_BLOCK_CFLUSH            0x37
-#define I2O_CMD_BLOCK_MLOCK             0x49
-#define I2O_CMD_BLOCK_MUNLOCK           0x4B
-#define I2O_CMD_BLOCK_MMOUNT            0x41
-#define I2O_CMD_BLOCK_MEJECT            0x43
-#define I2O_CMD_BLOCK_POWER             0x70
-
-#define I2O_CMD_PRIVATE                 0xFF
-
-/* Command status values  */
-
-#define I2O_CMD_IN_PROGRESS     0x01
-#define I2O_CMD_REJECTED        0x02
-#define I2O_CMD_FAILED          0x03
-#define I2O_CMD_COMPLETED       0x04
-
-/* I2O API function return values */
-
-#define I2O_RTN_NO_ERROR                        0
-#define I2O_RTN_NOT_INIT                        1
-#define I2O_RTN_FREE_Q_EMPTY                    2
-#define I2O_RTN_TCB_ERROR                       3
-#define I2O_RTN_TRANSACTION_ERROR               4
-#define I2O_RTN_ADAPTER_ALREADY_INIT            5
-#define I2O_RTN_MALLOC_ERROR                    6
-#define I2O_RTN_ADPTR_NOT_REGISTERED            7
-#define I2O_RTN_MSG_REPLY_TIMEOUT               8
-#define I2O_RTN_NO_STATUS                       9
-#define I2O_RTN_NO_FIRM_VER                     10
-#define I2O_RTN_NO_LINK_SPEED                   11
-
-/* Reply message status defines for all messages */
-
-#define I2O_REPLY_STATUS_SUCCESS                        0x00
-#define I2O_REPLY_STATUS_ABORT_DIRTY                    0x01
-#define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER         0x02
-#define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER         0x03
-#define I2O_REPLY_STATUS_ERROR_DIRTY                    0x04
-#define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER         0x05
-#define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER         0x06
-#define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY            0x08
-#define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09
-#define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A
-#define I2O_REPLY_STATUS_TRANSACTION_ERROR              0x0B
-#define I2O_REPLY_STATUS_PROGRESS_REPORT                0x80
-
-/* Status codes and Error Information for Parameter functions */
-
-#define I2O_PARAMS_STATUS_SUCCESS               0x00
-#define I2O_PARAMS_STATUS_BAD_KEY_ABORT         0x01
-#define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE      0x02
-#define I2O_PARAMS_STATUS_BUFFER_FULL           0x03
-#define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL      0x04
-#define I2O_PARAMS_STATUS_FIELD_UNREADABLE      0x05
-#define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE     0x06
-#define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS   0x07
-#define I2O_PARAMS_STATUS_INVALID_GROUP_ID      0x08
-#define I2O_PARAMS_STATUS_INVALID_OPERATION     0x09
-#define I2O_PARAMS_STATUS_NO_KEY_FIELD          0x0A
-#define I2O_PARAMS_STATUS_NO_SUCH_FIELD         0x0B
-#define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP     0x0C
-#define I2O_PARAMS_STATUS_OPERATION_ERROR       0x0D
-#define I2O_PARAMS_STATUS_SCALAR_ERROR          0x0E
-#define I2O_PARAMS_STATUS_TABLE_ERROR           0x0F
-#define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE      0x10
-
-/* DetailedStatusCode defines for Executive, DDM, Util and Transaction error
- * messages: Table 3-2 Detailed Status Codes.*/
-
-#define I2O_DSC_SUCCESS                        0x0000
-#define I2O_DSC_BAD_KEY                        0x0002
-#define I2O_DSC_TCL_ERROR                      0x0003
-#define I2O_DSC_REPLY_BUFFER_FULL              0x0004
-#define I2O_DSC_NO_SUCH_PAGE                   0x0005
-#define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT     0x0006
-#define I2O_DSC_INSUFFICIENT_RESOURCE_HARD     0x0007
-#define I2O_DSC_CHAIN_BUFFER_TOO_LARGE         0x0009
-#define I2O_DSC_UNSUPPORTED_FUNCTION           0x000A
-#define I2O_DSC_DEVICE_LOCKED                  0x000B
-#define I2O_DSC_DEVICE_RESET                   0x000C
-#define I2O_DSC_INAPPROPRIATE_FUNCTION         0x000D
-#define I2O_DSC_INVALID_INITIATOR_ADDRESS      0x000E
-#define I2O_DSC_INVALID_MESSAGE_FLAGS          0x000F
-#define I2O_DSC_INVALID_OFFSET                 0x0010
-#define I2O_DSC_INVALID_PARAMETER              0x0011
-#define I2O_DSC_INVALID_REQUEST                0x0012
-#define I2O_DSC_INVALID_TARGET_ADDRESS         0x0013
-#define I2O_DSC_MESSAGE_TOO_LARGE              0x0014
-#define I2O_DSC_MESSAGE_TOO_SMALL              0x0015
-#define I2O_DSC_MISSING_PARAMETER              0x0016
-#define I2O_DSC_TIMEOUT                        0x0017
-#define I2O_DSC_UNKNOWN_ERROR                  0x0018
-#define I2O_DSC_UNKNOWN_FUNCTION               0x0019
-#define I2O_DSC_UNSUPPORTED_VERSION            0x001A
-#define I2O_DSC_DEVICE_BUSY                    0x001B
-#define I2O_DSC_DEVICE_NOT_AVAILABLE           0x001C
-
-/* DetailedStatusCode defines for Block Storage Operation: Table 6-7 Detailed
-   Status Codes.*/
-
-#define I2O_BSA_DSC_SUCCESS               0x0000
-#define I2O_BSA_DSC_MEDIA_ERROR           0x0001
-#define I2O_BSA_DSC_ACCESS_ERROR          0x0002
-#define I2O_BSA_DSC_DEVICE_FAILURE        0x0003
-#define I2O_BSA_DSC_DEVICE_NOT_READY      0x0004
-#define I2O_BSA_DSC_MEDIA_NOT_PRESENT     0x0005
-#define I2O_BSA_DSC_MEDIA_LOCKED          0x0006
-#define I2O_BSA_DSC_MEDIA_FAILURE         0x0007
-#define I2O_BSA_DSC_PROTOCOL_FAILURE      0x0008
-#define I2O_BSA_DSC_BUS_FAILURE           0x0009
-#define I2O_BSA_DSC_ACCESS_VIOLATION      0x000A
-#define I2O_BSA_DSC_WRITE_PROTECTED       0x000B
-#define I2O_BSA_DSC_DEVICE_RESET          0x000C
-#define I2O_BSA_DSC_VOLUME_CHANGED        0x000D
-#define I2O_BSA_DSC_TIMEOUT               0x000E
-
-/* FailureStatusCodes, Table 3-3 Message Failure Codes */
-
-#define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED             0x81
-#define I2O_FSC_TRANSPORT_SERVICE_TERMINATED            0x82
-#define I2O_FSC_TRANSPORT_CONGESTION                    0x83
-#define I2O_FSC_TRANSPORT_FAILURE                       0x84
-#define I2O_FSC_TRANSPORT_STATE_ERROR                   0x85
-#define I2O_FSC_TRANSPORT_TIME_OUT                      0x86
-#define I2O_FSC_TRANSPORT_ROUTING_FAILURE               0x87
-#define I2O_FSC_TRANSPORT_INVALID_VERSION               0x88
-#define I2O_FSC_TRANSPORT_INVALID_OFFSET                0x89
-#define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS             0x8A
-#define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL               0x8B
-#define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE               0x8C
-#define I2O_FSC_TRANSPORT_INVALID_TARGET_ID             0x8D
-#define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID          0x8E
-#define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT     0x8F
-#define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE               0xFF
-
-/* Device Claim Types */
-#define I2O_CLAIM_PRIMARY                                       0x01000000
-#define I2O_CLAIM_MANAGEMENT                                    0x02000000
-#define I2O_CLAIM_AUTHORIZED                                    0x03000000
-#define I2O_CLAIM_SECONDARY                                     0x04000000
-
-/* Message header defines for VersionOffset */
-#define I2OVER15        0x0001
-#define I2OVER20        0x0002
-
-/* Default is 1.5 */
-#define I2OVERSION      I2OVER15
-
-#define SGL_OFFSET_0    I2OVERSION
-#define SGL_OFFSET_4    (0x0040 | I2OVERSION)
-#define SGL_OFFSET_5    (0x0050 | I2OVERSION)
-#define SGL_OFFSET_6    (0x0060 | I2OVERSION)
-#define SGL_OFFSET_7    (0x0070 | I2OVERSION)
-#define SGL_OFFSET_8    (0x0080 | I2OVERSION)
-#define SGL_OFFSET_9    (0x0090 | I2OVERSION)
-#define SGL_OFFSET_10   (0x00A0 | I2OVERSION)
-#define SGL_OFFSET_11   (0x00B0 | I2OVERSION)
-#define SGL_OFFSET_12   (0x00C0 | I2OVERSION)
-#define SGL_OFFSET(x)   (((x)<<4) | I2OVERSION)
-
-/* Transaction Reply Lists (TRL) Control Word structure */
-#define TRL_SINGLE_FIXED_LENGTH         0x00
-#define TRL_SINGLE_VARIABLE_LENGTH      0x40
-#define TRL_MULTIPLE_FIXED_LENGTH       0x80
-
- /* msg header defines for MsgFlags */
-#define MSG_STATIC      0x0100
-#define MSG_64BIT_CNTXT 0x0200
-#define MSG_MULTI_TRANS 0x1000
-#define MSG_FAIL        0x2000
-#define MSG_FINAL       0x4000
-#define MSG_REPLY       0x8000
-
- /* minimum size msg */
-#define THREE_WORD_MSG_SIZE     0x00030000
-#define FOUR_WORD_MSG_SIZE      0x00040000
-#define FIVE_WORD_MSG_SIZE      0x00050000
-#define SIX_WORD_MSG_SIZE       0x00060000
-#define SEVEN_WORD_MSG_SIZE     0x00070000
-#define EIGHT_WORD_MSG_SIZE     0x00080000
-#define NINE_WORD_MSG_SIZE      0x00090000
-#define TEN_WORD_MSG_SIZE       0x000A0000
-#define ELEVEN_WORD_MSG_SIZE    0x000B0000
-#define I2O_MESSAGE_SIZE(x)     ((x)<<16)
-
-/* special TID assignments */
-#define ADAPTER_TID             0
-#define HOST_TID                1
-
-/* outbound queue defines */
-#define I2O_MAX_OUTBOUND_MSG_FRAMES     128
-#define I2O_OUTBOUND_MSG_FRAME_SIZE     128     /* in 32-bit words */
-
-#define I2O_POST_WAIT_OK        0
-#define I2O_POST_WAIT_TIMEOUT   -ETIMEDOUT
-
-#define I2O_CONTEXT_LIST_MIN_LENGTH     15
-#define I2O_CONTEXT_LIST_USED           0x01
-#define I2O_CONTEXT_LIST_DELETED        0x02
-
-/* timeouts */
-#define I2O_TIMEOUT_INIT_OUTBOUND_QUEUE 15
-#define I2O_TIMEOUT_MESSAGE_GET         5
-#define I2O_TIMEOUT_RESET               30
-#define I2O_TIMEOUT_STATUS_GET          5
-#define I2O_TIMEOUT_LCT_GET             360
-#define I2O_TIMEOUT_SCSI_SCB_ABORT      240
-
-/* retries */
-#define I2O_HRT_GET_TRIES               3
-#define I2O_LCT_GET_TRIES               3
-
-/* defines for max_sectors and max_phys_segments */
-#define I2O_MAX_SECTORS                 1024
-#define I2O_MAX_SECTORS_LIMITED         256
-#define I2O_MAX_PHYS_SEGMENTS           MAX_PHYS_SEGMENTS
-
 #endif                          /* __KERNEL__ */
 #endif                          /* _I2O_H */