Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into for-davem

Conflicts:
	drivers/net/wireless/libertas/if_cs.c
	drivers/net/wireless/rtlwifi/pci.c
	net/bluetooth/l2cap_sock.c

4 files changed, 36 insertions, 8 deletions

diff --git a/include/linux/ath9k_platform.h b/include/linux/ath9k_platform.h
index 020387a114e3..60a7c49dcb49 100644
--- a/include/linux/ath9k_platform.h
+++ b/include/linux/ath9k_platform.h
@@ -28,6 +28,8 @@ struct ath9k_platform_data {
         int led_pin;
         u32 gpio_mask;
         u32 gpio_val;
+
+        bool is_clk_25mhz;
 };
 
 #endif /* _LINUX_ATH9K_PLATFORM_H */
diff --git a/include/linux/ssb/ssb_driver_chipcommon.h b/include/linux/ssb/ssb_driver_chipcommon.h
index 2cdf249b4e5f..a08d693d8324 100644
--- a/include/linux/ssb/ssb_driver_chipcommon.h
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
@@ -123,6 +123,8 @@
 #define SSB_CHIPCO_FLASHDATA            0x0048
 #define SSB_CHIPCO_BCAST_ADDR           0x0050
 #define SSB_CHIPCO_BCAST_DATA           0x0054
+#define SSB_CHIPCO_GPIOPULLUP           0x0058          /* Rev >= 20 only */
+#define SSB_CHIPCO_GPIOPULLDOWN         0x005C          /* Rev >= 20 only */
 #define SSB_CHIPCO_GPIOIN               0x0060
 #define SSB_CHIPCO_GPIOOUT              0x0064
 #define SSB_CHIPCO_GPIOOUTEN            0x0068
@@ -131,6 +133,9 @@
 #define SSB_CHIPCO_GPIOIRQ              0x0074
 #define SSB_CHIPCO_WATCHDOG             0x0080
 #define SSB_CHIPCO_GPIOTIMER            0x0088          /* LED powersave (corerev >= 16) */
+#define  SSB_CHIPCO_GPIOTIMER_OFFTIME   0x0000FFFF
+#define  SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT     0
+#define  SSB_CHIPCO_GPIOTIMER_ONTIME    0xFFFF0000
 #define  SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT      16
 #define SSB_CHIPCO_GPIOTOUTM            0x008C          /* LED powersave (corerev >= 16) */
 #define SSB_CHIPCO_CLOCK_N              0x0090
@@ -189,8 +194,10 @@
 #define  SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
 #define  SSB_CHIPCO_CLKCTLST_HAVEHTREQ  0x00000010 /* HT available request */
 #define  SSB_CHIPCO_CLKCTLST_HWCROFF    0x00000020 /* Force HW clock request off */
-#define  SSB_CHIPCO_CLKCTLST_HAVEHT     0x00010000 /* HT available */
-#define  SSB_CHIPCO_CLKCTLST_HAVEALP    0x00020000 /* APL available */
+#define  SSB_CHIPCO_CLKCTLST_HAVEALP    0x00010000 /* ALP available */
+#define  SSB_CHIPCO_CLKCTLST_HAVEHT     0x00020000 /* HT available */
+#define  SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT      0x00010000 /* 4328a0 has reversed bits */
+#define  SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP     0x00020000 /* 4328a0 has reversed bits */
 #define SSB_CHIPCO_HW_WORKAROUND        0x01E4 /* Hardware workaround (rev >= 20) */
 #define SSB_CHIPCO_UART0_DATA           0x0300
 #define SSB_CHIPCO_UART0_IMR            0x0304
diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h
index 402955ae48ce..efbf459d571c 100644
--- a/include/linux/ssb/ssb_regs.h
+++ b/include/linux/ssb/ssb_regs.h
@@ -97,7 +97,7 @@
 #define  SSB_INTVEC_ENET1       0x00000040 /* Enable interrupts for enet 1 */
 #define SSB_TMSLOW              0x0F98     /* SB Target State Low */
 #define  SSB_TMSLOW_RESET       0x00000001 /* Reset */
-#define  SSB_TMSLOW_REJECT_22   0x00000002 /* Reject (Backplane rev 2.2) */
+#define  SSB_TMSLOW_REJECT      0x00000002 /* Reject (Standard Backplane) */
 #define  SSB_TMSLOW_REJECT_23   0x00000004 /* Reject (Backplane rev 2.3) */
 #define  SSB_TMSLOW_CLOCK       0x00010000 /* Clock Enable */
 #define  SSB_TMSLOW_FGC         0x00020000 /* Force Gated Clocks On */
diff --git a/include/linux/wl12xx.h b/include/linux/wl12xx.h
index bebb8efea0a6..4b697395326e 100644
--- a/include/linux/wl12xx.h
+++ b/include/linux/wl12xx.h
@@ -24,12 +24,26 @@
 #ifndef _LINUX_WL12XX_H
 #define _LINUX_WL12XX_H
 
-/* The board reference clock values */
+/* Reference clock values */
 enum {
-        WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
-        WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
-        WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
-        WL12XX_REFCLOCK_54 = 3, /* 54 MHz */
+        WL12XX_REFCLOCK_19      = 0, /* 19.2 MHz */
+        WL12XX_REFCLOCK_26      = 1, /* 26 MHz */
+        WL12XX_REFCLOCK_38      = 2, /* 38.4 MHz */
+        WL12XX_REFCLOCK_52      = 3, /* 52 MHz */
+        WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
+        WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
+};
+
+/* TCXO clock values */
+enum {
+        WL12XX_TCXOCLOCK_19_2   = 0, /* 19.2MHz */
+        WL12XX_TCXOCLOCK_26     = 1, /* 26 MHz */
+        WL12XX_TCXOCLOCK_38_4   = 2, /* 38.4MHz */
+        WL12XX_TCXOCLOCK_52     = 3, /* 52 MHz */
+        WL12XX_TCXOCLOCK_16_368 = 4, /* 16.368 MHz */
+        WL12XX_TCXOCLOCK_32_736 = 5, /* 32.736 MHz */
+        WL12XX_TCXOCLOCK_16_8   = 6, /* 16.8 MHz */
+        WL12XX_TCXOCLOCK_33_6   = 7, /* 33.6 MHz */
 };
 
 struct wl12xx_platform_data {
@@ -38,8 +52,13 @@ struct wl12xx_platform_data {
         int irq;
         bool use_eeprom;
         int board_ref_clock;
+        int board_tcxo_clock;
+        unsigned long platform_quirks;
 };
 
+/* Platform does not support level trigger interrupts */
+#define WL12XX_PLATFORM_QUIRK_EDGE_IRQ  BIT(0)
+
 #ifdef CONFIG_WL12XX_PLATFORM_DATA
 
 int wl12xx_set_platform_data(const struct wl12xx_platform_data *data);