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authorVinod Koul <vinod.koul@linux.intel.com>2011-09-02 07:13:44 -0400
committerVinod Koul <vinod.koul@intel.com>2011-09-02 07:13:44 -0400
commit8516f52fa497b37eb3d5e58d34e61a41ae0a553a (patch)
treeb73175b134d36bea303d2f181ae89a448c2add81 /include/linux
parentc6a389f123b9f68d605bb7e0f9b32ec1e3e14132 (diff)
parent7b4b88e067d37cbbafd856121767f7e154294eb2 (diff)
Merge branch 'next' into v3.1-rc4
Fixed trivial conflicts in drivers/dma/amba-pl08x.c Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/amba/pl08x.h14
-rw-r--r--include/linux/dmaengine.h13
2 files changed, 23 insertions, 4 deletions
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h
index e6e28f37d8ec..a22662c93981 100644
--- a/include/linux/amba/pl08x.h
+++ b/include/linux/amba/pl08x.h
@@ -47,6 +47,9 @@ enum {
47 * @muxval: a number usually used to poke into some mux regiser to 47 * @muxval: a number usually used to poke into some mux regiser to
48 * mux in the signal to this channel 48 * mux in the signal to this channel
49 * @cctl_opt: default options for the channel control register 49 * @cctl_opt: default options for the channel control register
50 * @device_fc: Flow Controller Settings for ccfg register. Only valid for slave
51 * channels. Fill with 'true' if peripheral should be flow controller. Direction
52 * will be selected at Runtime.
50 * @addr: source/target address in physical memory for this DMA channel, 53 * @addr: source/target address in physical memory for this DMA channel,
51 * can be the address of a FIFO register for burst requests for example. 54 * can be the address of a FIFO register for burst requests for example.
52 * This can be left undefined if the PrimeCell API is used for configuring 55 * This can be left undefined if the PrimeCell API is used for configuring
@@ -65,6 +68,7 @@ struct pl08x_channel_data {
65 int max_signal; 68 int max_signal;
66 u32 muxval; 69 u32 muxval;
67 u32 cctl; 70 u32 cctl;
71 bool device_fc;
68 dma_addr_t addr; 72 dma_addr_t addr;
69 bool circular_buffer; 73 bool circular_buffer;
70 bool single; 74 bool single;
@@ -77,13 +81,11 @@ struct pl08x_channel_data {
77 * @addr: current address 81 * @addr: current address
78 * @maxwidth: the maximum width of a transfer on this bus 82 * @maxwidth: the maximum width of a transfer on this bus
79 * @buswidth: the width of this bus in bytes: 1, 2 or 4 83 * @buswidth: the width of this bus in bytes: 1, 2 or 4
80 * @fill_bytes: bytes required to fill to the next bus memory boundary
81 */ 84 */
82struct pl08x_bus_data { 85struct pl08x_bus_data {
83 dma_addr_t addr; 86 dma_addr_t addr;
84 u8 maxwidth; 87 u8 maxwidth;
85 u8 buswidth; 88 u8 buswidth;
86 size_t fill_bytes;
87}; 89};
88 90
89/** 91/**
@@ -105,8 +107,16 @@ struct pl08x_phy_chan {
105 107
106/** 108/**
107 * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor 109 * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
110 * @tx: async tx descriptor
111 * @node: node for txd list for channels
112 * @src_addr: src address of txd
113 * @dst_addr: dst address of txd
114 * @len: transfer len in bytes
115 * @direction: direction of transfer
108 * @llis_bus: DMA memory address (physical) start for the LLIs 116 * @llis_bus: DMA memory address (physical) start for the LLIs
109 * @llis_va: virtual memory address start for the LLIs 117 * @llis_va: virtual memory address start for the LLIs
118 * @cctl: control reg values for current txd
119 * @ccfg: config reg values for current txd
110 */ 120 */
111struct pl08x_txd { 121struct pl08x_txd {
112 struct dma_async_tx_descriptor tx; 122 struct dma_async_tx_descriptor tx;
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 8fbf40e0713c..ace51af4369f 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -24,8 +24,7 @@
24#include <linux/device.h> 24#include <linux/device.h>
25#include <linux/uio.h> 25#include <linux/uio.h>
26#include <linux/dma-direction.h> 26#include <linux/dma-direction.h>
27 27#include <linux/scatterlist.h>
28struct scatterlist;
29 28
30/** 29/**
31 * typedef dma_cookie_t - an opaque DMA cookie 30 * typedef dma_cookie_t - an opaque DMA cookie
@@ -519,6 +518,16 @@ static inline int dmaengine_slave_config(struct dma_chan *chan,
519 (unsigned long)config); 518 (unsigned long)config);
520} 519}
521 520
521static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
522 struct dma_chan *chan, void *buf, size_t len,
523 enum dma_data_direction dir, unsigned long flags)
524{
525 struct scatterlist sg;
526 sg_init_one(&sg, buf, len);
527
528 return chan->device->device_prep_slave_sg(chan, &sg, 1, dir, flags);
529}
530
522static inline int dmaengine_terminate_all(struct dma_chan *chan) 531static inline int dmaengine_terminate_all(struct dma_chan *chan)
523{ 532{
524 return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0); 533 return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);