diff options
author | Shaohua Li <shaohua.li@intel.com> | 2008-01-23 21:21:57 -0500 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2008-02-01 18:04:30 -0500 |
commit | 6c723d5bd89f03fc3ef627d50f89ade054d2ee3b (patch) | |
tree | 45fcf8a380b48ddf686456ff65a2234c23c05504 /include/linux | |
parent | 5c796ae7a7ebe56967ed9b9963d7c16d733635ff (diff) |
PCI: PCIE ASPM support
PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the Link to do likewise. This
capability allows hardware-autonomous, dynamic Link power reduction
beyond what is achievable by software-only controlled power management.
However, The device should be configured by software appropriately.
Enabling ASPM will save power, but will introduce device latency.
This patch adds ASPM support in Linux. It introduces a global policy for
ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control
it. The interface can be used as a boot option too. Currently we have
below setting:
-default, BIOS default setting
-powersave, highest power saving mode, enable all available ASPM
state
and clock power management
-performance, highest performance, disable ASPM and clock power
management
By default, the 'default' policy is used currently.
In my test, power difference between powersave mode and performance mode
is about 1.3w in a system with 3 PCIE links.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'include/linux')
-rw-r--r-- | include/linux/aspm.h | 44 | ||||
-rw-r--r-- | include/linux/pci.h | 5 | ||||
-rw-r--r-- | include/linux/pci_regs.h | 8 |
3 files changed, 57 insertions, 0 deletions
diff --git a/include/linux/aspm.h b/include/linux/aspm.h new file mode 100644 index 000000000000..f41a69895485 --- /dev/null +++ b/include/linux/aspm.h | |||
@@ -0,0 +1,44 @@ | |||
1 | /* | ||
2 | * aspm.h | ||
3 | * | ||
4 | * PCI Express ASPM defines and function prototypes | ||
5 | * | ||
6 | * Copyright (C) 2007 Intel Corp. | ||
7 | * Zhang Yanmin (yanmin.zhang@intel.com) | ||
8 | * Shaohua Li (shaohua.li@intel.com) | ||
9 | * | ||
10 | * For more information, please consult the following manuals (look at | ||
11 | * http://www.pcisig.com/ for how to get them): | ||
12 | * | ||
13 | * PCI Express Specification | ||
14 | */ | ||
15 | |||
16 | #ifndef LINUX_ASPM_H | ||
17 | #define LINUX_ASPM_H | ||
18 | |||
19 | #include <linux/pci.h> | ||
20 | |||
21 | #define PCIE_LINK_STATE_L0S 1 | ||
22 | #define PCIE_LINK_STATE_L1 2 | ||
23 | #define PCIE_LINK_STATE_CLKPM 4 | ||
24 | |||
25 | #ifdef CONFIG_PCIEASPM | ||
26 | extern void pcie_aspm_init_link_state(struct pci_dev *pdev); | ||
27 | extern void pcie_aspm_exit_link_state(struct pci_dev *pdev); | ||
28 | extern void pcie_aspm_pm_state_change(struct pci_dev *pdev); | ||
29 | extern void pci_disable_link_state(struct pci_dev *pdev, int state); | ||
30 | #else | ||
31 | #define pcie_aspm_init_link_state(pdev) do {} while (0) | ||
32 | #define pcie_aspm_exit_link_state(pdev) do {} while (0) | ||
33 | #define pcie_aspm_pm_state_change(pdev) do {} while (0) | ||
34 | #define pci_disable_link_state(pdev, state) do {} while (0) | ||
35 | #endif | ||
36 | |||
37 | #ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */ | ||
38 | extern void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev); | ||
39 | extern void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev); | ||
40 | #else | ||
41 | #define pcie_aspm_create_sysfs_dev_files(pdev) do {} while (0) | ||
42 | #define pcie_aspm_remove_sysfs_dev_files(pdev) do {} while (0) | ||
43 | #endif | ||
44 | #endif /* LINUX_ASPM_H */ | ||
diff --git a/include/linux/pci.h b/include/linux/pci.h index 13813b0592fc..163b45241729 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h | |||
@@ -128,6 +128,7 @@ struct pci_cap_saved_state { | |||
128 | u32 data[0]; | 128 | u32 data[0]; |
129 | }; | 129 | }; |
130 | 130 | ||
131 | struct pcie_link_state; | ||
131 | /* | 132 | /* |
132 | * The pci_dev structure is used to describe PCI devices. | 133 | * The pci_dev structure is used to describe PCI devices. |
133 | */ | 134 | */ |
@@ -163,6 +164,10 @@ struct pci_dev { | |||
163 | this is D0-D3, D0 being fully functional, | 164 | this is D0-D3, D0 being fully functional, |
164 | and D3 being off. */ | 165 | and D3 being off. */ |
165 | 166 | ||
167 | #ifdef CONFIG_PCIEASPM | ||
168 | struct pcie_link_state *link_state; /* ASPM link state. */ | ||
169 | #endif | ||
170 | |||
166 | pci_channel_state_t error_state; /* current connectivity state */ | 171 | pci_channel_state_t error_state; /* current connectivity state */ |
167 | struct device dev; /* Generic device interface */ | 172 | struct device dev; /* Generic device interface */ |
168 | 173 | ||
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index c1914a8b94a9..c0c1223c9194 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h | |||
@@ -395,9 +395,17 @@ | |||
395 | #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ | 395 | #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ |
396 | #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ | 396 | #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ |
397 | #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ | 397 | #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ |
398 | #define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */ | ||
399 | #define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */ | ||
400 | #define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */ | ||
401 | #define PCI_EXP_LNKCAP_CLKPM 0x40000 /* L1 Clock Power Management */ | ||
398 | #define PCI_EXP_LNKCTL 16 /* Link Control */ | 402 | #define PCI_EXP_LNKCTL 16 /* Link Control */ |
403 | #define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ | ||
404 | #define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ | ||
399 | #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */ | 405 | #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */ |
400 | #define PCI_EXP_LNKSTA 18 /* Link Status */ | 406 | #define PCI_EXP_LNKSTA 18 /* Link Status */ |
407 | #define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ | ||
408 | #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ | ||
401 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ | 409 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ |
402 | #define PCI_EXP_SLTCTL 24 /* Slot Control */ | 410 | #define PCI_EXP_SLTCTL 24 /* Slot Control */ |
403 | #define PCI_EXP_SLTSTA 26 /* Slot Status */ | 411 | #define PCI_EXP_SLTSTA 26 /* Slot Status */ |