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authorDave Airlie <airlied@redhat.com>2011-05-15 20:45:40 -0400
committerDave Airlie <airlied@redhat.com>2011-05-15 20:45:40 -0400
commit69f7876b2ab61e8114675d6092ad0b482e233612 (patch)
treea55aefd08d6c5f617d277a99e11b5a707e162585 /include/linux/v4l2-mediabus.h
parent0eacdba3a186e5d5b8a8bb421caacddc135e67e3 (diff)
parent645c62a5e95a5f9a8e0d0627446bbda4ee042024 (diff)
Merge remote branch 'keithp/drm-intel-next' of /ssd/git/drm-next into drm-core-next
* 'keithp/drm-intel-next' of /ssd/git/drm-next: (301 commits) drm/i915: split PCH clock gating init drm/i915: add Ivybridge clock gating init function drm/i915: Update the location of the ringbuffers' HWS_PGA registers for IVB. drm/i915: Add support for fence registers on Ivybridge. drm/i915: Use existing function instead of open-coding fence reg clear. drm/i915: split clock gating init into per-chipset functions drm/i915: set IBX pch type explicitly drm/i915: add Ivy Bridge PCI IDs and driver feature structs drm/i915: add PantherPoint PCH ID agp/intel: add Ivy Bridge support drm/i915: ring support for Ivy Bridge drm/i915: page flip support for Ivy Bridge drm/i915: interrupt & vblank support for Ivy Bridge drm/i915: treat Ivy Bridge watermarks like Sandy Bridge drm/i915: manual FDI training for Ivy Bridge drm/i915: add swizzle/tiling support for Ivy Bridge drm/i915: Ivy Bridge has split display and pipe control drm/i915: add IS_IVYBRIDGE macro for checks drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later drm/i915: split enable/disable vblank code into chipset specific functions ...
Diffstat (limited to 'include/linux/v4l2-mediabus.h')
-rw-r--r--include/linux/v4l2-mediabus.h7
1 files changed, 5 insertions, 2 deletions
diff --git a/include/linux/v4l2-mediabus.h b/include/linux/v4l2-mediabus.h
index 7054a7a8065e..de5c15921025 100644
--- a/include/linux/v4l2-mediabus.h
+++ b/include/linux/v4l2-mediabus.h
@@ -47,7 +47,7 @@ enum v4l2_mbus_pixelcode {
47 V4L2_MBUS_FMT_RGB565_2X8_BE = 0x1007, 47 V4L2_MBUS_FMT_RGB565_2X8_BE = 0x1007,
48 V4L2_MBUS_FMT_RGB565_2X8_LE = 0x1008, 48 V4L2_MBUS_FMT_RGB565_2X8_LE = 0x1008,
49 49
50 /* YUV (including grey) - next is 0x2013 */ 50 /* YUV (including grey) - next is 0x2014 */
51 V4L2_MBUS_FMT_Y8_1X8 = 0x2001, 51 V4L2_MBUS_FMT_Y8_1X8 = 0x2001,
52 V4L2_MBUS_FMT_UYVY8_1_5X8 = 0x2002, 52 V4L2_MBUS_FMT_UYVY8_1_5X8 = 0x2002,
53 V4L2_MBUS_FMT_VYUY8_1_5X8 = 0x2003, 53 V4L2_MBUS_FMT_VYUY8_1_5X8 = 0x2003,
@@ -60,6 +60,7 @@ enum v4l2_mbus_pixelcode {
60 V4L2_MBUS_FMT_Y10_1X10 = 0x200a, 60 V4L2_MBUS_FMT_Y10_1X10 = 0x200a,
61 V4L2_MBUS_FMT_YUYV10_2X10 = 0x200b, 61 V4L2_MBUS_FMT_YUYV10_2X10 = 0x200b,
62 V4L2_MBUS_FMT_YVYU10_2X10 = 0x200c, 62 V4L2_MBUS_FMT_YVYU10_2X10 = 0x200c,
63 V4L2_MBUS_FMT_Y12_1X12 = 0x2013,
63 V4L2_MBUS_FMT_UYVY8_1X16 = 0x200f, 64 V4L2_MBUS_FMT_UYVY8_1X16 = 0x200f,
64 V4L2_MBUS_FMT_VYUY8_1X16 = 0x2010, 65 V4L2_MBUS_FMT_VYUY8_1X16 = 0x2010,
65 V4L2_MBUS_FMT_YUYV8_1X16 = 0x2011, 66 V4L2_MBUS_FMT_YUYV8_1X16 = 0x2011,
@@ -67,9 +68,11 @@ enum v4l2_mbus_pixelcode {
67 V4L2_MBUS_FMT_YUYV10_1X20 = 0x200d, 68 V4L2_MBUS_FMT_YUYV10_1X20 = 0x200d,
68 V4L2_MBUS_FMT_YVYU10_1X20 = 0x200e, 69 V4L2_MBUS_FMT_YVYU10_1X20 = 0x200e,
69 70
70 /* Bayer - next is 0x3013 */ 71 /* Bayer - next is 0x3015 */
71 V4L2_MBUS_FMT_SBGGR8_1X8 = 0x3001, 72 V4L2_MBUS_FMT_SBGGR8_1X8 = 0x3001,
73 V4L2_MBUS_FMT_SGBRG8_1X8 = 0x3013,
72 V4L2_MBUS_FMT_SGRBG8_1X8 = 0x3002, 74 V4L2_MBUS_FMT_SGRBG8_1X8 = 0x3002,
75 V4L2_MBUS_FMT_SRGGB8_1X8 = 0x3014,
73 V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8 = 0x300b, 76 V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8 = 0x300b,
74 V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8 = 0x300c, 77 V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8 = 0x300c,
75 V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8 = 0x3009, 78 V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8 = 0x3009,