USB: EHCI: Add Intel Moorestown EHCI controller HOSTPCx extensions and support phy low power mode

The Intel Moorestown EHCI controller supports non-standard HOSTPCx register
extension. This register controls the LPM behaviour and controls the behaviour
of each USB port.

Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com>
Signed-off-by: Alek Du <alek.du@intel.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 13 insertions, 0 deletions

diff --git a/include/linux/usb/ehci_def.h b/include/linux/usb/ehci_def.h
index 5b88e36c9103..4c4b701ff265 100644
--- a/include/linux/usb/ehci_def.h
+++ b/include/linux/usb/ehci_def.h
@@ -132,6 +132,19 @@ struct ehci_regs {
 #define USBMODE_CM_HC   (3<<0)          /* host controller mode */
 #define USBMODE_CM_IDLE (0<<0)          /* idle state */
 
+/* Moorestown has some non-standard registers, partially due to the fact that
+ * its EHCI controller has both TT and LPM support. HOSTPCx are extentions to
+ * PORTSCx
+ */
+#define HOSTPC0         0x84            /* HOSTPC extension */
+#define HOSTPC_PHCD     (1<<22)         /* Phy clock disable */
+#define HOSTPC_PSPD     (3<<25)         /* Port speed detection */
+#define USBMODE_EX      0xc8            /* USB Device mode extension */
+#define USBMODE_EX_VBPS (1<<5)          /* VBus Power Select On */
+#define USBMODE_EX_HC   (3<<0)          /* host controller mode */
+#define TXFILLTUNING    0x24            /* TX FIFO Tuning register */
+#define TXFIFO_DEFAULT  (8<<16)         /* FIFO burst threshold 8 */
+
 /* Appendix C, Debug port ... intended for use with special "debug devices"
  * that can help if there's no serial console.  (nonstandard enumeration.)
  */