USB: EHCI: Support controllers with big endian capability regs

The two first HC capability registers (CAPLENGTH and HCIVERSION)
are defined as one 8-bit and one 16-bit register. Most HC
implementations have selected to treat these registers as part
of a 32-bit register, giving the same layout for both big and
small endian systems.

This patch adds a new quirk, big_endian_capbase, to support
controllers with big endian register interfaces that treat
HCIVERSION and CAPLENGTH as individual registers.

Signed-off-by: Jan Andersson <jan@gaisler.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

1 files changed, 7 insertions, 2 deletions

diff --git a/include/linux/usb/ehci_def.h b/include/linux/usb/ehci_def.h
index 78799432008e..7cc95ee3606b 100644
--- a/include/linux/usb/ehci_def.h
+++ b/include/linux/usb/ehci_def.h
@@ -25,10 +25,15 @@
 struct ehci_caps {
         /* these fields are specified as 8 and 16 bit registers,
          * but some hosts can't perform 8 or 16 bit PCI accesses.
+         * some hosts treat caplength and hciversion as parts of a 32-bit
+         * register, others treat them as two separate registers, this
+         * affects the memory map for big endian controllers.
          */
         u32             hc_capbase;
-#define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
-#define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
+#define HC_LENGTH(ehci, p)      (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
+                                (ehci_big_endian_capbase(ehci) ? 24 : 0)))
+#define HC_VERSION(ehci, p)     (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
+                                (ehci_big_endian_capbase(ehci) ? 0 : 16)))
         u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
 #define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */