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authorMichael Buesch <mb@bu3sch.de>2007-09-18 15:12:50 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-10-10 19:51:36 -0400
commit61e115a56d1aafd6e6a8a9fee8ac099a6128ac7b (patch)
treeadd97bf6a1207a4caea3a86cf13495ad3dc477de /include/linux/ssb
parent5ee3afba88f5a79d0bff07ddd87af45919259f91 (diff)
[SSB]: add Sonics Silicon Backplane bus support
SSB is an SoC bus used in a number of embedded devices. The most well-known of these devices is probably the Linksys WRT54G, but there are others as well. The bus is also used internally on the BCM43xx and BCM44xx devices from Broadcom. This patch also includes support for SSB ID tables in modules, so that SSB drivers can be loaded automatically. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/ssb')
-rw-r--r--include/linux/ssb/ssb.h424
-rw-r--r--include/linux/ssb/ssb_driver_chipcommon.h396
-rw-r--r--include/linux/ssb/ssb_driver_extif.h204
-rw-r--r--include/linux/ssb/ssb_driver_mips.h46
-rw-r--r--include/linux/ssb/ssb_driver_pci.h106
-rw-r--r--include/linux/ssb/ssb_regs.h292
6 files changed, 1468 insertions, 0 deletions
diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h
new file mode 100644
index 000000000000..2b5c312c4960
--- /dev/null
+++ b/include/linux/ssb/ssb.h
@@ -0,0 +1,424 @@
1#ifndef LINUX_SSB_H_
2#define LINUX_SSB_H_
3
4#include <linux/device.h>
5#include <linux/list.h>
6#include <linux/types.h>
7#include <linux/spinlock.h>
8#include <linux/pci.h>
9#include <linux/mod_devicetable.h>
10
11#include <linux/ssb/ssb_regs.h>
12
13
14struct pcmcia_device;
15struct ssb_bus;
16struct ssb_driver;
17
18
19struct ssb_sprom_r1 {
20 u16 pci_spid; /* Subsystem Product ID for PCI */
21 u16 pci_svid; /* Subsystem Vendor ID for PCI */
22 u16 pci_pid; /* Product ID for PCI */
23 u8 il0mac[6]; /* MAC address for 802.11b/g */
24 u8 et0mac[6]; /* MAC address for Ethernet */
25 u8 et1mac[6]; /* MAC address for 802.11a */
26 u8 et0phyaddr:5; /* MII address for enet0 */
27 u8 et1phyaddr:5; /* MII address for enet1 */
28 u8 et0mdcport:1; /* MDIO for enet0 */
29 u8 et1mdcport:1; /* MDIO for enet1 */
30 u8 board_rev; /* Board revision */
31 u8 country_code:4; /* Country Code */
32 u8 antenna_a:2; /* Antenna 0/1 available for A-PHY */
33 u8 antenna_bg:2; /* Antenna 0/1 available for B-PHY and G-PHY */
34 u16 pa0b0;
35 u16 pa0b1;
36 u16 pa0b2;
37 u16 pa1b0;
38 u16 pa1b1;
39 u16 pa1b2;
40 u8 gpio0; /* GPIO pin 0 */
41 u8 gpio1; /* GPIO pin 1 */
42 u8 gpio2; /* GPIO pin 2 */
43 u8 gpio3; /* GPIO pin 3 */
44 u16 maxpwr_a; /* A-PHY Power Amplifier Max Power (in dBm Q5.2) */
45 u16 maxpwr_bg; /* B/G-PHY Power Amplifier Max Power (in dBm Q5.2) */
46 u8 itssi_a; /* Idle TSSI Target for A-PHY */
47 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
48 u16 boardflags_lo; /* Boardflags (low 16 bits) */
49 u8 antenna_gain_a; /* A-PHY Antenna gain (in dBm Q5.2) */
50 u8 antenna_gain_bg; /* B/G-PHY Antenna gain (in dBm Q5.2) */
51 u8 oem[8]; /* OEM string (rev 1 only) */
52};
53
54struct ssb_sprom_r2 {
55 u16 boardflags_hi; /* Boardflags (high 16 bits) */
56 u8 maxpwr_a_lo; /* A-PHY Max Power Low */
57 u8 maxpwr_a_hi; /* A-PHY Max Power High */
58 u16 pa1lob0; /* A-PHY PA Low Settings */
59 u16 pa1lob1; /* A-PHY PA Low Settings */
60 u16 pa1lob2; /* A-PHY PA Low Settings */
61 u16 pa1hib0; /* A-PHY PA High Settings */
62 u16 pa1hib1; /* A-PHY PA High Settings */
63 u16 pa1hib2; /* A-PHY PA High Settings */
64 u8 ofdm_pwr_off; /* OFDM Power Offset from CCK Level */
65 u8 country_str[2]; /* Two char Country Code */
66};
67
68struct ssb_sprom_r3 {
69 u32 ofdmapo; /* A-PHY OFDM Mid Power Offset */
70 u32 ofdmalpo; /* A-PHY OFDM Low Power Offset */
71 u32 ofdmahpo; /* A-PHY OFDM High Power Offset */
72 u8 gpioldc_on_cnt; /* GPIO LED Powersave Duty Cycle ON count */
73 u8 gpioldc_off_cnt; /* GPIO LED Powersave Duty Cycle OFF count */
74 u8 cckpo_1M:4; /* CCK Power Offset for Rate 1M */
75 u8 cckpo_2M:4; /* CCK Power Offset for Rate 2M */
76 u8 cckpo_55M:4; /* CCK Power Offset for Rate 5.5M */
77 u8 cckpo_11M:4; /* CCK Power Offset for Rate 11M */
78 u32 ofdmgpo; /* G-PHY OFDM Power Offset */
79};
80
81struct ssb_sprom_r4 {
82 /* TODO */
83};
84
85struct ssb_sprom {
86 u8 revision;
87 u8 crc;
88 /* The valid r# fields are selected by the "revision".
89 * Revision 3 and lower inherit from lower revisions.
90 */
91 union {
92 struct {
93 struct ssb_sprom_r1 r1;
94 struct ssb_sprom_r2 r2;
95 struct ssb_sprom_r3 r3;
96 };
97 struct ssb_sprom_r4 r4;
98 };
99};
100
101/* Information about the PCB the circuitry is soldered on. */
102struct ssb_boardinfo {
103 u16 vendor;
104 u16 type;
105 u16 rev;
106};
107
108
109struct ssb_device;
110/* Lowlevel read/write operations on the device MMIO.
111 * Internal, don't use that outside of ssb. */
112struct ssb_bus_ops {
113 u16 (*read16)(struct ssb_device *dev, u16 offset);
114 u32 (*read32)(struct ssb_device *dev, u16 offset);
115 void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
116 void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
117};
118
119
120/* Core-ID values. */
121#define SSB_DEV_CHIPCOMMON 0x800
122#define SSB_DEV_ILINE20 0x801
123#define SSB_DEV_SDRAM 0x803
124#define SSB_DEV_PCI 0x804
125#define SSB_DEV_MIPS 0x805
126#define SSB_DEV_ETHERNET 0x806
127#define SSB_DEV_V90 0x807
128#define SSB_DEV_USB11_HOSTDEV 0x808
129#define SSB_DEV_ADSL 0x809
130#define SSB_DEV_ILINE100 0x80A
131#define SSB_DEV_IPSEC 0x80B
132#define SSB_DEV_PCMCIA 0x80D
133#define SSB_DEV_INTERNAL_MEM 0x80E
134#define SSB_DEV_MEMC_SDRAM 0x80F
135#define SSB_DEV_EXTIF 0x811
136#define SSB_DEV_80211 0x812
137#define SSB_DEV_MIPS_3302 0x816
138#define SSB_DEV_USB11_HOST 0x817
139#define SSB_DEV_USB11_DEV 0x818
140#define SSB_DEV_USB20_HOST 0x819
141#define SSB_DEV_USB20_DEV 0x81A
142#define SSB_DEV_SDIO_HOST 0x81B
143#define SSB_DEV_ROBOSWITCH 0x81C
144#define SSB_DEV_PARA_ATA 0x81D
145#define SSB_DEV_SATA_XORDMA 0x81E
146#define SSB_DEV_ETHERNET_GBIT 0x81F
147#define SSB_DEV_PCIE 0x820
148#define SSB_DEV_MIMO_PHY 0x821
149#define SSB_DEV_SRAM_CTRLR 0x822
150#define SSB_DEV_MINI_MACPHY 0x823
151#define SSB_DEV_ARM_1176 0x824
152#define SSB_DEV_ARM_7TDMI 0x825
153
154/* Vendor-ID values */
155#define SSB_VENDOR_BROADCOM 0x4243
156
157/* Some kernel subsystems poke with dev->drvdata, so we must use the
158 * following ugly workaround to get from struct device to struct ssb_device */
159struct __ssb_dev_wrapper {
160 struct device dev;
161 struct ssb_device *sdev;
162};
163
164struct ssb_device {
165 /* Having a copy of the ops pointer in each dev struct
166 * is an optimization. */
167 const struct ssb_bus_ops *ops;
168
169 struct device *dev;
170 struct ssb_bus *bus;
171 struct ssb_device_id id;
172
173 u8 core_index;
174 unsigned int irq;
175
176 /* Internal-only stuff follows. */
177 void *drvdata; /* Per-device data */
178 void *devtypedata; /* Per-devicetype (eg 802.11) data */
179};
180
181/* Go from struct device to struct ssb_device. */
182static inline
183struct ssb_device * dev_to_ssb_dev(struct device *dev)
184{
185 struct __ssb_dev_wrapper *wrap;
186 wrap = container_of(dev, struct __ssb_dev_wrapper, dev);
187 return wrap->sdev;
188}
189
190/* Device specific user data */
191static inline
192void ssb_set_drvdata(struct ssb_device *dev, void *data)
193{
194 dev->drvdata = data;
195}
196static inline
197void * ssb_get_drvdata(struct ssb_device *dev)
198{
199 return dev->drvdata;
200}
201
202/* Devicetype specific user data. This is per device-type (not per device) */
203void ssb_set_devtypedata(struct ssb_device *dev, void *data);
204static inline
205void * ssb_get_devtypedata(struct ssb_device *dev)
206{
207 return dev->devtypedata;
208}
209
210
211struct ssb_driver {
212 const char *name;
213 const struct ssb_device_id *id_table;
214
215 int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id);
216 void (*remove)(struct ssb_device *dev);
217 int (*suspend)(struct ssb_device *dev, pm_message_t state);
218 int (*resume)(struct ssb_device *dev);
219 void (*shutdown)(struct ssb_device *dev);
220
221 struct device_driver drv;
222};
223#define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
224
225extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
226static inline int ssb_driver_register(struct ssb_driver *drv)
227{
228 return __ssb_driver_register(drv, THIS_MODULE);
229}
230extern void ssb_driver_unregister(struct ssb_driver *drv);
231
232
233
234
235enum ssb_bustype {
236 SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */
237 SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */
238 SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */
239};
240
241/* board_vendor */
242#define SSB_BOARDVENDOR_BCM 0x14E4 /* Broadcom */
243#define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */
244#define SSB_BOARDVENDOR_HP 0x0E11 /* HP */
245/* board_type */
246#define SSB_BOARD_BCM94306MP 0x0418
247#define SSB_BOARD_BCM4309G 0x0421
248#define SSB_BOARD_BCM4306CB 0x0417
249#define SSB_BOARD_BCM4309MP 0x040C
250#define SSB_BOARD_MP4318 0x044A
251#define SSB_BOARD_BU4306 0x0416
252#define SSB_BOARD_BU4309 0x040A
253/* chip_package */
254#define SSB_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */
255#define SSB_CHIPPACK_BCM4712M 2 /* Medium 225pin 4712 */
256#define SSB_CHIPPACK_BCM4712L 0 /* Large 340pin 4712 */
257
258#include <linux/ssb/ssb_driver_chipcommon.h>
259#include <linux/ssb/ssb_driver_mips.h>
260#include <linux/ssb/ssb_driver_extif.h>
261#include <linux/ssb/ssb_driver_pci.h>
262
263struct ssb_bus {
264 /* The MMIO area. */
265 void __iomem *mmio;
266
267 const struct ssb_bus_ops *ops;
268
269 /* The core in the basic address register window. (PCI bus only) */
270 struct ssb_device *mapped_device;
271 /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
272 u8 mapped_pcmcia_seg;
273 /* Lock for core and segment switching. */
274 spinlock_t bar_lock;
275
276 /* The bus this backplane is running on. */
277 enum ssb_bustype bustype;
278 /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
279 struct pci_dev *host_pci;
280 /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
281 struct pcmcia_device *host_pcmcia;
282
283#ifdef CONFIG_SSB_PCIHOST
284 /* Mutex to protect the SPROM writing. */
285 struct mutex pci_sprom_mutex;
286#endif
287
288 /* ID information about the Chip. */
289 u16 chip_id;
290 u16 chip_rev;
291 u8 chip_package;
292
293 /* List of devices (cores) on the backplane. */
294 struct ssb_device devices[SSB_MAX_NR_CORES];
295 u8 nr_devices;
296
297 /* Reference count. Number of suspended devices. */
298 u8 suspend_cnt;
299
300 /* Software ID number for this bus. */
301 unsigned int busnumber;
302
303 /* The ChipCommon device (if available). */
304 struct ssb_chipcommon chipco;
305 /* The PCI-core device (if available). */
306 struct ssb_pcicore pcicore;
307 /* The MIPS-core device (if available). */
308 struct ssb_mipscore mipscore;
309 /* The EXTif-core device (if available). */
310 struct ssb_extif extif;
311
312 /* The following structure elements are not available in early
313 * SSB initialization. Though, they are available for regular
314 * registered drivers at any stage. So be careful when
315 * using them in the ssb core code. */
316
317 /* ID information about the PCB. */
318 struct ssb_boardinfo boardinfo;
319 /* Contents of the SPROM. */
320 struct ssb_sprom sprom;
321
322 /* Internal-only stuff follows. Do not touch. */
323 struct list_head list;
324#ifdef CONFIG_SSB_DEBUG
325 /* Is the bus already powered up? */
326 bool powered_up;
327 int power_warn_count;
328#endif /* DEBUG */
329};
330
331/* The initialization-invariants. */
332struct ssb_init_invariants {
333 struct ssb_boardinfo boardinfo;
334 struct ssb_sprom sprom;
335};
336/* Type of function to fetch the invariants. */
337typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
338 struct ssb_init_invariants *iv);
339
340/* Register a SSB system bus. get_invariants() is called after the
341 * basic system devices are initialized.
342 * The invariants are usually fetched from some NVRAM.
343 * Put the invariants into the struct pointed to by iv. */
344extern int ssb_bus_ssbbus_register(struct ssb_bus *bus,
345 unsigned long baseaddr,
346 ssb_invariants_func_t get_invariants);
347#ifdef CONFIG_SSB_PCIHOST
348extern int ssb_bus_pcibus_register(struct ssb_bus *bus,
349 struct pci_dev *host_pci);
350#endif /* CONFIG_SSB_PCIHOST */
351#ifdef CONFIG_SSB_PCMCIAHOST
352extern int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
353 struct pcmcia_device *pcmcia_dev,
354 unsigned long baseaddr);
355#endif /* CONFIG_SSB_PCMCIAHOST */
356
357extern void ssb_bus_unregister(struct ssb_bus *bus);
358
359extern u32 ssb_clockspeed(struct ssb_bus *bus);
360
361/* Is the device enabled in hardware? */
362int ssb_device_is_enabled(struct ssb_device *dev);
363/* Enable a device and pass device-specific SSB_TMSLOW flags.
364 * If no device-specific flags are available, use 0. */
365void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags);
366/* Disable a device in hardware and pass SSB_TMSLOW flags (if any). */
367void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags);
368
369
370/* Device MMIO register read/write functions. */
371static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
372{
373 return dev->ops->read16(dev, offset);
374}
375static inline u32 ssb_read32(struct ssb_device *dev, u16 offset)
376{
377 return dev->ops->read32(dev, offset);
378}
379static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
380{
381 dev->ops->write16(dev, offset, value);
382}
383static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
384{
385 dev->ops->write32(dev, offset, value);
386}
387
388
389/* Translation (routing) bits that need to be ORed to DMA
390 * addresses before they are given to a device. */
391extern u32 ssb_dma_translation(struct ssb_device *dev);
392#define SSB_DMA_TRANSLATION_MASK 0xC0000000
393#define SSB_DMA_TRANSLATION_SHIFT 30
394
395extern int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask);
396
397
398#ifdef CONFIG_SSB_PCIHOST
399/* PCI-host wrapper driver */
400extern int ssb_pcihost_register(struct pci_driver *driver);
401static inline void ssb_pcihost_unregister(struct pci_driver *driver)
402{
403 pci_unregister_driver(driver);
404}
405#endif /* CONFIG_SSB_PCIHOST */
406
407
408/* If a driver is shutdown or suspended, call this to signal
409 * that the bus may be completely powered down. SSB will decide,
410 * if it's really time to power down the bus, based on if there
411 * are other devices that want to run. */
412extern int ssb_bus_may_powerdown(struct ssb_bus *bus);
413/* Before initializing and enabling a device, call this to power-up the bus.
414 * If you want to allow use of dynamic-power-control, pass the flag.
415 * Otherwise static always-on powercontrol will be used. */
416extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
417
418
419/* Various helper functions */
420extern u32 ssb_admatch_base(u32 adm);
421extern u32 ssb_admatch_size(u32 adm);
422
423
424#endif /* LINUX_SSB_H_ */
diff --git a/include/linux/ssb/ssb_driver_chipcommon.h b/include/linux/ssb/ssb_driver_chipcommon.h
new file mode 100644
index 000000000000..4cb995494662
--- /dev/null
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
@@ -0,0 +1,396 @@
1#ifndef LINUX_SSB_CHIPCO_H_
2#define LINUX_SSB_CHIPCO_H_
3
4/* SonicsSiliconBackplane CHIPCOMMON core hardware definitions
5 *
6 * The chipcommon core provides chip identification, SB control,
7 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
8 * gpio interface, extbus, and support for serial and parallel flashes.
9 *
10 * Copyright 2005, Broadcom Corporation
11 * Copyright 2006, Michael Buesch <mb@bu3sch.de>
12 *
13 * Licensed under the GPL version 2. See COPYING for details.
14 */
15
16/** ChipCommon core registers. **/
17
18#define SSB_CHIPCO_CHIPID 0x0000
19#define SSB_CHIPCO_IDMASK 0x0000FFFF
20#define SSB_CHIPCO_REVMASK 0x000F0000
21#define SSB_CHIPCO_REVSHIFT 16
22#define SSB_CHIPCO_PACKMASK 0x00F00000
23#define SSB_CHIPCO_PACKSHIFT 20
24#define SSB_CHIPCO_NRCORESMASK 0x0F000000
25#define SSB_CHIPCO_NRCORESSHIFT 24
26#define SSB_CHIPCO_CAP 0x0004 /* Capabilities */
27#define SSB_CHIPCO_CAP_NRUART 0x00000003 /* # of UARTs */
28#define SSB_CHIPCO_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
29#define SSB_CHIPCO_CAP_UARTCLK 0x00000018 /* UART clock select */
30#define SSB_CHIPCO_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
31#define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
32#define SSB_CHIPCO_CAP_EXTBUS 0x000000C0 /* External buses present */
33#define SSB_CHIPCO_CAP_FLASHT 0x00000700 /* Flash Type */
34#define SSB_CHIPCO_FLASHT_NONE 0x00000000 /* No flash */
35#define SSB_CHIPCO_FLASHT_STSER 0x00000100 /* ST serial flash */
36#define SSB_CHIPCO_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
37#define SSB_CHIPCO_FLASHT_PARA 0x00000700 /* Parallel flash */
38#define SSB_CHIPCO_CAP_PLLT 0x00038000 /* PLL Type */
39#define SSB_PLLTYPE_NONE 0x00000000
40#define SSB_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */
41#define SSB_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */
42#define SSB_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */
43#define SSB_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */
44#define SSB_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */
45#define SSB_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */
46#define SSB_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */
47#define SSB_CHIPCO_CAP_PCTL 0x00040000 /* Power Control */
48#define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */
49#define SSB_CHIPCO_CAP_OTPS_SHIFT 19
50#define SSB_CHIPCO_CAP_OTPS_BASE 5
51#define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */
52#define SSB_CHIPCO_CAP_BROM 0x00800000 /* Internal boot ROM active */
53#define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
54#define SSB_CHIPCO_CORECTL 0x0008
55#define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
56#define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
57#define SSB_CHIPCO_BIST 0x000C
58#define SSB_CHIPCO_OTPS 0x0010 /* OTP status */
59#define SSB_CHIPCO_OTPS_PROGFAIL 0x80000000
60#define SSB_CHIPCO_OTPS_PROTECT 0x00000007
61#define SSB_CHIPCO_OTPS_HW_PROTECT 0x00000001
62#define SSB_CHIPCO_OTPS_SW_PROTECT 0x00000002
63#define SSB_CHIPCO_OTPS_CID_PROTECT 0x00000004
64#define SSB_CHIPCO_OTPC 0x0014 /* OTP control */
65#define SSB_CHIPCO_OTPC_RECWAIT 0xFF000000
66#define SSB_CHIPCO_OTPC_PROGWAIT 0x00FFFF00
67#define SSB_CHIPCO_OTPC_PRW_SHIFT 8
68#define SSB_CHIPCO_OTPC_MAXFAIL 0x00000038
69#define SSB_CHIPCO_OTPC_VSEL 0x00000006
70#define SSB_CHIPCO_OTPC_SELVL 0x00000001
71#define SSB_CHIPCO_OTPP 0x0018 /* OTP prog */
72#define SSB_CHIPCO_OTPP_COL 0x000000FF
73#define SSB_CHIPCO_OTPP_ROW 0x0000FF00
74#define SSB_CHIPCO_OTPP_ROW_SHIFT 8
75#define SSB_CHIPCO_OTPP_READERR 0x10000000
76#define SSB_CHIPCO_OTPP_VALUE 0x20000000
77#define SSB_CHIPCO_OTPP_READ 0x40000000
78#define SSB_CHIPCO_OTPP_START 0x80000000
79#define SSB_CHIPCO_OTPP_BUSY 0x80000000
80#define SSB_CHIPCO_IRQSTAT 0x0020
81#define SSB_CHIPCO_IRQMASK 0x0024
82#define SSB_CHIPCO_IRQ_GPIO 0x00000001 /* gpio intr */
83#define SSB_CHIPCO_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
84#define SSB_CHIPCO_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
85#define SSB_CHIPCO_CHIPCTL 0x0028 /* Rev >= 11 only */
86#define SSB_CHIPCO_CHIPSTAT 0x002C /* Rev >= 11 only */
87#define SSB_CHIPCO_JCMD 0x0030 /* Rev >= 10 only */
88#define SSB_CHIPCO_JCMD_START 0x80000000
89#define SSB_CHIPCO_JCMD_BUSY 0x80000000
90#define SSB_CHIPCO_JCMD_PAUSE 0x40000000
91#define SSB_CHIPCO_JCMD0_ACC_MASK 0x0000F000
92#define SSB_CHIPCO_JCMD0_ACC_IRDR 0x00000000
93#define SSB_CHIPCO_JCMD0_ACC_DR 0x00001000
94#define SSB_CHIPCO_JCMD0_ACC_IR 0x00002000
95#define SSB_CHIPCO_JCMD0_ACC_RESET 0x00003000
96#define SSB_CHIPCO_JCMD0_ACC_IRPDR 0x00004000
97#define SSB_CHIPCO_JCMD0_ACC_PDR 0x00005000
98#define SSB_CHIPCO_JCMD0_IRW_MASK 0x00000F00
99#define SSB_CHIPCO_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
100#define SSB_CHIPCO_JCMD_ACC_IRDR 0x00000000
101#define SSB_CHIPCO_JCMD_ACC_DR 0x00010000
102#define SSB_CHIPCO_JCMD_ACC_IR 0x00020000
103#define SSB_CHIPCO_JCMD_ACC_RESET 0x00030000
104#define SSB_CHIPCO_JCMD_ACC_IRPDR 0x00040000
105#define SSB_CHIPCO_JCMD_ACC_PDR 0x00050000
106#define SSB_CHIPCO_JCMD_IRW_MASK 0x00001F00
107#define SSB_CHIPCO_JCMD_IRW_SHIFT 8
108#define SSB_CHIPCO_JCMD_DRW_MASK 0x0000003F
109#define SSB_CHIPCO_JIR 0x0034 /* Rev >= 10 only */
110#define SSB_CHIPCO_JDR 0x0038 /* Rev >= 10 only */
111#define SSB_CHIPCO_JCTL 0x003C /* Rev >= 10 only */
112#define SSB_CHIPCO_JCTL_FORCE_CLK 4 /* Force clock */
113#define SSB_CHIPCO_JCTL_EXT_EN 2 /* Enable external targets */
114#define SSB_CHIPCO_JCTL_EN 1 /* Enable Jtag master */
115#define SSB_CHIPCO_FLASHCTL 0x0040
116#define SSB_CHIPCO_FLASHCTL_START 0x80000000
117#define SSB_CHIPCO_FLASHCTL_BUSY SSB_CHIPCO_FLASHCTL_START
118#define SSB_CHIPCO_FLASHADDR 0x0044
119#define SSB_CHIPCO_FLASHDATA 0x0048
120#define SSB_CHIPCO_BCAST_ADDR 0x0050
121#define SSB_CHIPCO_BCAST_DATA 0x0054
122#define SSB_CHIPCO_GPIOIN 0x0060
123#define SSB_CHIPCO_GPIOOUT 0x0064
124#define SSB_CHIPCO_GPIOOUTEN 0x0068
125#define SSB_CHIPCO_GPIOCTL 0x006C
126#define SSB_CHIPCO_GPIOPOL 0x0070
127#define SSB_CHIPCO_GPIOIRQ 0x0074
128#define SSB_CHIPCO_WATCHDOG 0x0080
129#define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
130#define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
131#define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
132#define SSB_CHIPCO_CLOCK_N 0x0090
133#define SSB_CHIPCO_CLOCK_SB 0x0094
134#define SSB_CHIPCO_CLOCK_PCI 0x0098
135#define SSB_CHIPCO_CLOCK_M2 0x009C
136#define SSB_CHIPCO_CLOCK_MIPS 0x00A0
137#define SSB_CHIPCO_CLKDIV 0x00A4 /* Rev >= 3 only */
138#define SSB_CHIPCO_CLKDIV_SFLASH 0x0F000000
139#define SSB_CHIPCO_CLKDIV_SFLASH_SHIFT 24
140#define SSB_CHIPCO_CLKDIV_OTP 0x000F0000
141#define SSB_CHIPCO_CLKDIV_OTP_SHIFT 16
142#define SSB_CHIPCO_CLKDIV_JTAG 0x00000F00
143#define SSB_CHIPCO_CLKDIV_JTAG_SHIFT 8
144#define SSB_CHIPCO_CLKDIV_UART 0x000000FF
145#define SSB_CHIPCO_PLLONDELAY 0x00B0 /* Rev >= 4 only */
146#define SSB_CHIPCO_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
147#define SSB_CHIPCO_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
148#define SSB_CHIPCO_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */
149#define SSB_CHIPCO_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */
150#define SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
151#define SSB_CHIPCO_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */
152#define SSB_CHIPCO_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
153#define SSB_CHIPCO_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
154#define SSB_CHIPCO_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
155#define SSB_CHIPCO_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
156#define SSB_CHIPCO_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
157#define SSB_CHIPCO_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
158#define SSB_CHIPCO_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
159#define SSB_CHIPCO_SLOWCLKCTL_CLKDIV_SHIFT 16
160#define SSB_CHIPCO_SYSCLKCTL 0x00C0 /* Rev >= 3 only */
161#define SSB_CHIPCO_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */
162#define SSB_CHIPCO_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */
163#define SSB_CHIPCO_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */
164#define SSB_CHIPCO_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */
165#define SSB_CHIPCO_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */
166#define SSB_CHIPCO_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
167#define SSB_CHIPCO_SYSCLKCTL_CLKDIV_SHIFT 16
168#define SSB_CHIPCO_CLKSTSTR 0x00C4 /* Rev >= 3 only */
169#define SSB_CHIPCO_PCMCIA_CFG 0x0100
170#define SSB_CHIPCO_PCMCIA_MEMWAIT 0x0104
171#define SSB_CHIPCO_PCMCIA_ATTRWAIT 0x0108
172#define SSB_CHIPCO_PCMCIA_IOWAIT 0x010C
173#define SSB_CHIPCO_IDE_CFG 0x0110
174#define SSB_CHIPCO_IDE_MEMWAIT 0x0114
175#define SSB_CHIPCO_IDE_ATTRWAIT 0x0118
176#define SSB_CHIPCO_IDE_IOWAIT 0x011C
177#define SSB_CHIPCO_PROG_CFG 0x0120
178#define SSB_CHIPCO_PROG_WAITCNT 0x0124
179#define SSB_CHIPCO_FLASH_CFG 0x0128
180#define SSB_CHIPCO_FLASH_WAITCNT 0x012C
181#define SSB_CHIPCO_UART0_DATA 0x0300
182#define SSB_CHIPCO_UART0_IMR 0x0304
183#define SSB_CHIPCO_UART0_FCR 0x0308
184#define SSB_CHIPCO_UART0_LCR 0x030C
185#define SSB_CHIPCO_UART0_MCR 0x0310
186#define SSB_CHIPCO_UART0_LSR 0x0314
187#define SSB_CHIPCO_UART0_MSR 0x0318
188#define SSB_CHIPCO_UART0_SCRATCH 0x031C
189#define SSB_CHIPCO_UART1_DATA 0x0400
190#define SSB_CHIPCO_UART1_IMR 0x0404
191#define SSB_CHIPCO_UART1_FCR 0x0408
192#define SSB_CHIPCO_UART1_LCR 0x040C
193#define SSB_CHIPCO_UART1_MCR 0x0410
194#define SSB_CHIPCO_UART1_LSR 0x0414
195#define SSB_CHIPCO_UART1_MSR 0x0418
196#define SSB_CHIPCO_UART1_SCRATCH 0x041C
197
198
199
200/** Clockcontrol masks and values **/
201
202/* SSB_CHIPCO_CLOCK_N */
203#define SSB_CHIPCO_CLK_N1 0x0000003F /* n1 control */
204#define SSB_CHIPCO_CLK_N2 0x00003F00 /* n2 control */
205#define SSB_CHIPCO_CLK_N2_SHIFT 8
206#define SSB_CHIPCO_CLK_PLLC 0x000F0000 /* pll control */
207#define SSB_CHIPCO_CLK_PLLC_SHIFT 16
208
209/* SSB_CHIPCO_CLOCK_SB/PCI/UART */
210#define SSB_CHIPCO_CLK_M1 0x0000003F /* m1 control */
211#define SSB_CHIPCO_CLK_M2 0x00003F00 /* m2 control */
212#define SSB_CHIPCO_CLK_M2_SHIFT 8
213#define SSB_CHIPCO_CLK_M3 0x003F0000 /* m3 control */
214#define SSB_CHIPCO_CLK_M3_SHIFT 16
215#define SSB_CHIPCO_CLK_MC 0x1F000000 /* mux control */
216#define SSB_CHIPCO_CLK_MC_SHIFT 24
217
218/* N3M Clock control magic field values */
219#define SSB_CHIPCO_CLK_F6_2 0x02 /* A factor of 2 in */
220#define SSB_CHIPCO_CLK_F6_3 0x03 /* 6-bit fields like */
221#define SSB_CHIPCO_CLK_F6_4 0x05 /* N1, M1 or M3 */
222#define SSB_CHIPCO_CLK_F6_5 0x09
223#define SSB_CHIPCO_CLK_F6_6 0x11
224#define SSB_CHIPCO_CLK_F6_7 0x21
225
226#define SSB_CHIPCO_CLK_F5_BIAS 5 /* 5-bit fields get this added */
227
228#define SSB_CHIPCO_CLK_MC_BYPASS 0x08
229#define SSB_CHIPCO_CLK_MC_M1 0x04
230#define SSB_CHIPCO_CLK_MC_M1M2 0x02
231#define SSB_CHIPCO_CLK_MC_M1M2M3 0x01
232#define SSB_CHIPCO_CLK_MC_M1M3 0x11
233
234/* Type 2 Clock control magic field values */
235#define SSB_CHIPCO_CLK_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
236#define SSB_CHIPCO_CLK_T2M2_BIAS 3 /* m2 bias */
237
238#define SSB_CHIPCO_CLK_T2MC_M1BYP 1
239#define SSB_CHIPCO_CLK_T2MC_M2BYP 2
240#define SSB_CHIPCO_CLK_T2MC_M3BYP 4
241
242/* Type 6 Clock control magic field values */
243#define SSB_CHIPCO_CLK_T6_MMASK 1 /* bits of interest in m */
244#define SSB_CHIPCO_CLK_T6_M0 120000000 /* sb clock for m = 0 */
245#define SSB_CHIPCO_CLK_T6_M1 100000000 /* sb clock for m = 1 */
246#define SSB_CHIPCO_CLK_SB2MIPS_T6(sb) (2 * (sb))
247
248/* Common clock base */
249#define SSB_CHIPCO_CLK_BASE1 24000000 /* Half the clock freq */
250#define SSB_CHIPCO_CLK_BASE2 12500000 /* Alternate crystal on some PLL's */
251
252/* Clock control values for 200Mhz in 5350 */
253#define SSB_CHIPCO_CLK_5350_N 0x0311
254#define SSB_CHIPCO_CLK_5350_M 0x04020009
255
256
257/** Bits in the config registers **/
258
259#define SSB_CHIPCO_CFG_EN 0x0001 /* Enable */
260#define SSB_CHIPCO_CFG_EXTM 0x000E /* Extif Mode */
261#define SSB_CHIPCO_CFG_EXTM_ASYNC 0x0002 /* Async/Parallel flash */
262#define SSB_CHIPCO_CFG_EXTM_SYNC 0x0004 /* Synchronous */
263#define SSB_CHIPCO_CFG_EXTM_PCMCIA 0x0008 /* PCMCIA */
264#define SSB_CHIPCO_CFG_EXTM_IDE 0x000A /* IDE */
265#define SSB_CHIPCO_CFG_DS16 0x0010 /* Data size, 0=8bit, 1=16bit */
266#define SSB_CHIPCO_CFG_CLKDIV 0x0060 /* Sync: Clock divisor */
267#define SSB_CHIPCO_CFG_CLKEN 0x0080 /* Sync: Clock enable */
268#define SSB_CHIPCO_CFG_BSTRO 0x0100 /* Sync: Size/Bytestrobe */
269
270
271/** Flash-specific control/status values */
272
273/* flashcontrol opcodes for ST flashes */
274#define SSB_CHIPCO_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
275#define SSB_CHIPCO_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
276#define SSB_CHIPCO_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
277#define SSB_CHIPCO_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
278#define SSB_CHIPCO_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
279#define SSB_CHIPCO_FLASHCTL_ST_PP 0x0302 /* Page Program */
280#define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
281#define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
282#define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
283#define SSB_CHIPCO_FLASHCTL_ST_RSIG 0x03AB /* Read Electronic Signature */
284
285/* Status register bits for ST flashes */
286#define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
287#define SSB_CHIPCO_FLASHSTA_ST_WEL 0x02 /* Write Enable Latch */
288#define SSB_CHIPCO_FLASHSTA_ST_BP 0x1C /* Block Protect */
289#define SSB_CHIPCO_FLASHSTA_ST_BP_SHIFT 2
290#define SSB_CHIPCO_FLASHSTA_ST_SRWD 0x80 /* Status Register Write Disable */
291
292/* flashcontrol opcodes for Atmel flashes */
293#define SSB_CHIPCO_FLASHCTL_AT_READ 0x07E8
294#define SSB_CHIPCO_FLASHCTL_AT_PAGE_READ 0x07D2
295#define SSB_CHIPCO_FLASHCTL_AT_BUF1_READ /* FIXME */
296#define SSB_CHIPCO_FLASHCTL_AT_BUF2_READ /* FIXME */
297#define SSB_CHIPCO_FLASHCTL_AT_STATUS 0x01D7
298#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE 0x0384
299#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRITE 0x0387
300#define SSB_CHIPCO_FLASHCTL_AT_BUF1_ERASE_PRGM 0x0283 /* Erase program */
301#define SSB_CHIPCO_FLASHCTL_AT_BUF2_ERASE_PRGM 0x0286 /* Erase program */
302#define SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM 0x0288
303#define SSB_CHIPCO_FLASHCTL_AT_BUF2_PROGRAM 0x0289
304#define SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE 0x0281
305#define SSB_CHIPCO_FLASHCTL_AT_BLOCK_ERASE 0x0250
306#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRER_PRGM 0x0382 /* Write erase program */
307#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRER_PRGM 0x0385 /* Write erase program */
308#define SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD 0x0253
309#define SSB_CHIPCO_FLASHCTL_AT_BUF2_LOAD 0x0255
310#define SSB_CHIPCO_FLASHCTL_AT_BUF1_COMPARE 0x0260
311#define SSB_CHIPCO_FLASHCTL_AT_BUF2_COMPARE 0x0261
312#define SSB_CHIPCO_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
313#define SSB_CHIPCO_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
314
315/* Status register bits for Atmel flashes */
316#define SSB_CHIPCO_FLASHSTA_AT_READY 0x80
317#define SSB_CHIPCO_FLASHSTA_AT_MISMATCH 0x40
318#define SSB_CHIPCO_FLASHSTA_AT_ID 0x38
319#define SSB_CHIPCO_FLASHSTA_AT_ID_SHIFT 3
320
321
322/** OTP **/
323
324/* OTP regions */
325#define SSB_CHIPCO_OTP_HW_REGION SSB_CHIPCO_OTPS_HW_PROTECT
326#define SSB_CHIPCO_OTP_SW_REGION SSB_CHIPCO_OTPS_SW_PROTECT
327#define SSB_CHIPCO_OTP_CID_REGION SSB_CHIPCO_OTPS_CID_PROTECT
328
329/* OTP regions (Byte offsets from otp size) */
330#define SSB_CHIPCO_OTP_SWLIM_OFF (-8)
331#define SSB_CHIPCO_OTP_CIDBASE_OFF 0
332#define SSB_CHIPCO_OTP_CIDLIM_OFF 8
333
334/* Predefined OTP words (Word offset from otp size) */
335#define SSB_CHIPCO_OTP_BOUNDARY_OFF (-4)
336#define SSB_CHIPCO_OTP_HWSIGN_OFF (-3)
337#define SSB_CHIPCO_OTP_SWSIGN_OFF (-2)
338#define SSB_CHIPCO_OTP_CIDSIGN_OFF (-1)
339
340#define SSB_CHIPCO_OTP_CID_OFF 0
341#define SSB_CHIPCO_OTP_PKG_OFF 1
342#define SSB_CHIPCO_OTP_FID_OFF 2
343#define SSB_CHIPCO_OTP_RSV_OFF 3
344#define SSB_CHIPCO_OTP_LIM_OFF 4
345
346#define SSB_CHIPCO_OTP_SIGNATURE 0x578A
347#define SSB_CHIPCO_OTP_MAGIC 0x4E56
348
349
350struct ssb_device;
351struct ssb_serial_port;
352
353struct ssb_chipcommon {
354 struct ssb_device *dev;
355 u32 capabilities;
356 /* Fast Powerup Delay constant */
357 u16 fast_pwrup_delay;
358};
359
360extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
361
362#include <linux/pm.h>
363extern void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state);
364extern void ssb_chipco_resume(struct ssb_chipcommon *cc);
365
366extern void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
367 u32 *plltype, u32 *n, u32 *m);
368extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
369 u32 *plltype, u32 *n, u32 *m);
370extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
371 unsigned long ns_per_cycle);
372
373enum ssb_clkmode {
374 SSB_CLKMODE_SLOW,
375 SSB_CLKMODE_FAST,
376 SSB_CLKMODE_DYNAMIC,
377};
378
379extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
380 enum ssb_clkmode mode);
381
382extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
383 u32 ticks);
384
385u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask);
386
387void ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value);
388
389void ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value);
390
391#ifdef CONFIG_SSB_SERIAL
392extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
393 struct ssb_serial_port *ports);
394#endif /* CONFIG_SSB_SERIAL */
395
396#endif /* LINUX_SSB_CHIPCO_H_ */
diff --git a/include/linux/ssb/ssb_driver_extif.h b/include/linux/ssb/ssb_driver_extif.h
new file mode 100644
index 000000000000..a9164357b5ae
--- /dev/null
+++ b/include/linux/ssb/ssb_driver_extif.h
@@ -0,0 +1,204 @@
1/*
2 * Hardware-specific External Interface I/O core definitions
3 * for the BCM47xx family of SiliconBackplane-based chips.
4 *
5 * The External Interface core supports a total of three external chip selects
6 * supporting external interfaces. One of the external chip selects is
7 * used for Flash, one is used for PCMCIA, and the other may be
8 * programmed to support either a synchronous interface or an
9 * asynchronous interface. The asynchronous interface can be used to
10 * support external devices such as UARTs and the BCM2019 Bluetooth
11 * baseband processor.
12 * The external interface core also contains 2 on-chip 16550 UARTs, clock
13 * frequency control, a watchdog interrupt timer, and a GPIO interface.
14 *
15 * Copyright 2005, Broadcom Corporation
16 * Copyright 2006, Michael Buesch
17 *
18 * Licensed under the GPL version 2. See COPYING for details.
19 */
20#ifndef LINUX_SSB_EXTIFCORE_H_
21#define LINUX_SSB_EXTIFCORE_H_
22
23/* external interface address space */
24#define SSB_EXTIF_PCMCIA_MEMBASE(x) (x)
25#define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
26#define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
27#define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
28#define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
29
30#define SSB_EXTIF_NR_GPIOOUT 5
31/* GPIO NOTE:
32 * The multiple instances of output and output enable registers
33 * are present to allow driver software for multiple cores to control
34 * gpio outputs without needing to share a single register pair.
35 * Use the following helper macro to get a register offset value.
36 */
37#define SSB_EXTIF_GPIO_OUT(index) ({ \
38 BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT); \
39 SSB_EXTIF_GPIO_OUT_BASE + ((index) * 8); \
40 })
41#define SSB_EXTIF_GPIO_OUTEN(index) ({ \
42 BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT); \
43 SSB_EXTIF_GPIO_OUTEN_BASE + ((index) * 8); \
44 })
45
46/** EXTIF core registers **/
47
48#define SSB_EXTIF_CTL 0x0000
49#define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */
50#define SSB_EXTIF_EXTSTAT 0x0004
51#define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */
52#define SSB_EXTIF_EXTSTAT_EIRQPIN (1 << 1) /* External interrupt pin (ro) */
53#define SSB_EXTIF_EXTSTAT_GPIOIRQPIN (1 << 2) /* GPIO interrupt pin (ro) */
54#define SSB_EXTIF_PCMCIA_CFG 0x0010
55#define SSB_EXTIF_PCMCIA_MEMWAIT 0x0014
56#define SSB_EXTIF_PCMCIA_ATTRWAIT 0x0018
57#define SSB_EXTIF_PCMCIA_IOWAIT 0x001C
58#define SSB_EXTIF_PROG_CFG 0x0020
59#define SSB_EXTIF_PROG_WAITCNT 0x0024
60#define SSB_EXTIF_FLASH_CFG 0x0028
61#define SSB_EXTIF_FLASH_WAITCNT 0x002C
62#define SSB_EXTIF_WATCHDOG 0x0040
63#define SSB_EXTIF_CLOCK_N 0x0044
64#define SSB_EXTIF_CLOCK_SB 0x0048
65#define SSB_EXTIF_CLOCK_PCI 0x004C
66#define SSB_EXTIF_CLOCK_MII 0x0050
67#define SSB_EXTIF_GPIO_IN 0x0060
68#define SSB_EXTIF_GPIO_OUT_BASE 0x0064
69#define SSB_EXTIF_GPIO_OUTEN_BASE 0x0068
70#define SSB_EXTIF_EJTAG_OUTEN 0x0090
71#define SSB_EXTIF_GPIO_INTPOL 0x0094
72#define SSB_EXTIF_GPIO_INTMASK 0x0098
73#define SSB_EXTIF_UART_DATA 0x0300
74#define SSB_EXTIF_UART_TIMER 0x0310
75#define SSB_EXTIF_UART_FCR 0x0320
76#define SSB_EXTIF_UART_LCR 0x0330
77#define SSB_EXTIF_UART_MCR 0x0340
78#define SSB_EXTIF_UART_LSR 0x0350
79#define SSB_EXTIF_UART_MSR 0x0360
80#define SSB_EXTIF_UART_SCRATCH 0x0370
81
82
83
84
85/* pcmcia/prog/flash_config */
86#define SSB_EXTCFG_EN (1 << 0) /* enable */
87#define SSB_EXTCFG_MODE 0xE /* mode */
88#define SSB_EXTCFG_MODE_SHIFT 1
89#define SSB_EXTCFG_MODE_FLASH 0x0 /* flash/asynchronous mode */
90#define SSB_EXTCFG_MODE_SYNC 0x2 /* synchronous mode */
91#define SSB_EXTCFG_MODE_PCMCIA 0x4 /* pcmcia mode */
92#define SSB_EXTCFG_DS16 (1 << 4) /* destsize: 0=8bit, 1=16bit */
93#define SSB_EXTCFG_BSWAP (1 << 5) /* byteswap */
94#define SSB_EXTCFG_CLKDIV 0xC0 /* clock divider */
95#define SSB_EXTCFG_CLKDIV_SHIFT 6
96#define SSB_EXTCFG_CLKDIV_2 0x0 /* backplane/2 */
97#define SSB_EXTCFG_CLKDIV_3 0x40 /* backplane/3 */
98#define SSB_EXTCFG_CLKDIV_4 0x80 /* backplane/4 */
99#define SSB_EXTCFG_CLKEN (1 << 8) /* clock enable */
100#define SSB_EXTCFG_STROBE (1 << 9) /* size/bytestrobe (synch only) */
101
102/* pcmcia_memwait */
103#define SSB_PCMCIA_MEMW_0 0x0000003F /* waitcount0 */
104#define SSB_PCMCIA_MEMW_1 0x00001F00 /* waitcount1 */
105#define SSB_PCMCIA_MEMW_1_SHIFT 8
106#define SSB_PCMCIA_MEMW_2 0x001F0000 /* waitcount2 */
107#define SSB_PCMCIA_MEMW_2_SHIFT 16
108#define SSB_PCMCIA_MEMW_3 0x1F000000 /* waitcount3 */
109#define SSB_PCMCIA_MEMW_3_SHIFT 24
110
111/* pcmcia_attrwait */
112#define SSB_PCMCIA_ATTW_0 0x0000003F /* waitcount0 */
113#define SSB_PCMCIA_ATTW_1 0x00001F00 /* waitcount1 */
114#define SSB_PCMCIA_ATTW_1_SHIFT 8
115#define SSB_PCMCIA_ATTW_2 0x001F0000 /* waitcount2 */
116#define SSB_PCMCIA_ATTW_2_SHIFT 16
117#define SSB_PCMCIA_ATTW_3 0x1F000000 /* waitcount3 */
118#define SSB_PCMCIA_ATTW_3_SHIFT 24
119
120/* pcmcia_iowait */
121#define SSB_PCMCIA_IOW_0 0x0000003F /* waitcount0 */
122#define SSB_PCMCIA_IOW_1 0x00001F00 /* waitcount1 */
123#define SSB_PCMCIA_IOW_1_SHIFT 8
124#define SSB_PCMCIA_IOW_2 0x001F0000 /* waitcount2 */
125#define SSB_PCMCIA_IOW_2_SHIFT 16
126#define SSB_PCMCIA_IOW_3 0x1F000000 /* waitcount3 */
127#define SSB_PCMCIA_IOW_3_SHIFT 24
128
129/* prog_waitcount */
130#define SSB_PROG_WCNT_0 0x0000001F /* waitcount0 */
131#define SSB_PROG_WCNT_1 0x00001F00 /* waitcount1 */
132#define SSB_PROG_WCNT_1_SHIFT 8
133#define SSB_PROG_WCNT_2 0x001F0000 /* waitcount2 */
134#define SSB_PROG_WCNT_2_SHIFT 16
135#define SSB_PROG_WCNT_3 0x1F000000 /* waitcount3 */
136#define SSB_PROG_WCNT_3_SHIFT 24
137
138#define SSB_PROG_W0 0x0000000C
139#define SSB_PROG_W1 0x00000A00
140#define SSB_PROG_W2 0x00020000
141#define SSB_PROG_W3 0x01000000
142
143/* flash_waitcount */
144#define SSB_FLASH_WCNT_0 0x0000001F /* waitcount0 */
145#define SSB_FLASH_WCNT_1 0x00001F00 /* waitcount1 */
146#define SSB_FLASH_WCNT_1_SHIFT 8
147#define SSB_FLASH_WCNT_2 0x001F0000 /* waitcount2 */
148#define SSB_FLASH_WCNT_2_SHIFT 16
149#define SSB_FLASH_WCNT_3 0x1F000000 /* waitcount3 */
150#define SSB_FLASH_WCNT_3_SHIFT 24
151
152/* watchdog */
153#define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
154
155
156
157#ifdef CONFIG_SSB_DRIVER_EXTIF
158
159struct ssb_extif {
160 struct ssb_device *dev;
161};
162
163static inline bool ssb_extif_available(struct ssb_extif *extif)
164{
165 return (extif->dev != NULL);
166}
167
168extern void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
169 u32 *plltype, u32 *n, u32 *m);
170
171extern void ssb_extif_timing_init(struct ssb_extif *extif,
172 unsigned long ns);
173
174u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
175
176void ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value);
177
178void ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value);
179
180#ifdef CONFIG_SSB_SERIAL
181extern int ssb_extif_serial_init(struct ssb_extif *extif,
182 struct ssb_serial_port *ports);
183#endif /* CONFIG_SSB_SERIAL */
184
185
186#else /* CONFIG_SSB_DRIVER_EXTIF */
187/* extif disabled */
188
189struct ssb_extif {
190};
191
192static inline bool ssb_extif_available(struct ssb_extif *extif)
193{
194 return 0;
195}
196
197static inline
198void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
199 u32 *plltype, u32 *n, u32 *m)
200{
201}
202
203#endif /* CONFIG_SSB_DRIVER_EXTIF */
204#endif /* LINUX_SSB_EXTIFCORE_H_ */
diff --git a/include/linux/ssb/ssb_driver_mips.h b/include/linux/ssb/ssb_driver_mips.h
new file mode 100644
index 000000000000..5f44e9740cd2
--- /dev/null
+++ b/include/linux/ssb/ssb_driver_mips.h
@@ -0,0 +1,46 @@
1#ifndef LINUX_SSB_MIPSCORE_H_
2#define LINUX_SSB_MIPSCORE_H_
3
4#ifdef CONFIG_SSB_DRIVER_MIPS
5
6struct ssb_device;
7
8struct ssb_serial_port {
9 void *regs;
10 unsigned long clockspeed;
11 unsigned int irq;
12 unsigned int baud_base;
13 unsigned int reg_shift;
14};
15
16
17struct ssb_mipscore {
18 struct ssb_device *dev;
19
20 int nr_serial_ports;
21 struct ssb_serial_port serial_ports[4];
22
23 u8 flash_buswidth;
24 u32 flash_window;
25 u32 flash_window_size;
26};
27
28extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
29extern u32 ssb_cpu_clock(struct ssb_mipscore *mcore);
30
31extern unsigned int ssb_mips_irq(struct ssb_device *dev);
32
33
34#else /* CONFIG_SSB_DRIVER_MIPS */
35
36struct ssb_mipscore {
37};
38
39static inline
40void ssb_mipscore_init(struct ssb_mipscore *mcore)
41{
42}
43
44#endif /* CONFIG_SSB_DRIVER_MIPS */
45
46#endif /* LINUX_SSB_MIPSCORE_H_ */
diff --git a/include/linux/ssb/ssb_driver_pci.h b/include/linux/ssb/ssb_driver_pci.h
new file mode 100644
index 000000000000..9cfffb7b1a27
--- /dev/null
+++ b/include/linux/ssb/ssb_driver_pci.h
@@ -0,0 +1,106 @@
1#ifndef LINUX_SSB_PCICORE_H_
2#define LINUX_SSB_PCICORE_H_
3
4#ifdef CONFIG_SSB_DRIVER_PCICORE
5
6/* PCI core registers. */
7#define SSB_PCICORE_CTL 0x0000 /* PCI Control */
8#define SSB_PCICORE_CTL_RST_OE 0x00000001 /* PCI_RESET Output Enable */
9#define SSB_PCICORE_CTL_RST 0x00000002 /* PCI_RESET driven out to pin */
10#define SSB_PCICORE_CTL_CLK_OE 0x00000004 /* Clock gate Output Enable */
11#define SSB_PCICORE_CTL_CLK 0x00000008 /* Gate for clock driven out to pin */
12#define SSB_PCICORE_ARBCTL 0x0010 /* PCI Arbiter Control */
13#define SSB_PCICORE_ARBCTL_INTERN 0x00000001 /* Use internal arbiter */
14#define SSB_PCICORE_ARBCTL_EXTERN 0x00000002 /* Use external arbiter */
15#define SSB_PCICORE_ARBCTL_PARKID 0x00000006 /* Mask, selects which agent is parked on an idle bus */
16#define SSB_PCICORE_ARBCTL_PARKID_LAST 0x00000000 /* Last requestor */
17#define SSB_PCICORE_ARBCTL_PARKID_4710 0x00000002 /* 4710 */
18#define SSB_PCICORE_ARBCTL_PARKID_EXT0 0x00000004 /* External requestor 0 */
19#define SSB_PCICORE_ARBCTL_PARKID_EXT1 0x00000006 /* External requestor 1 */
20#define SSB_PCICORE_ISTAT 0x0020 /* Interrupt status */
21#define SSB_PCICORE_ISTAT_INTA 0x00000001 /* PCI INTA# */
22#define SSB_PCICORE_ISTAT_INTB 0x00000002 /* PCI INTB# */
23#define SSB_PCICORE_ISTAT_SERR 0x00000004 /* PCI SERR# (write to clear) */
24#define SSB_PCICORE_ISTAT_PERR 0x00000008 /* PCI PERR# (write to clear) */
25#define SSB_PCICORE_ISTAT_PME 0x00000010 /* PCI PME# */
26#define SSB_PCICORE_IMASK 0x0024 /* Interrupt mask */
27#define SSB_PCICORE_IMASK_INTA 0x00000001 /* PCI INTA# */
28#define SSB_PCICORE_IMASK_INTB 0x00000002 /* PCI INTB# */
29#define SSB_PCICORE_IMASK_SERR 0x00000004 /* PCI SERR# */
30#define SSB_PCICORE_IMASK_PERR 0x00000008 /* PCI PERR# */
31#define SSB_PCICORE_IMASK_PME 0x00000010 /* PCI PME# */
32#define SSB_PCICORE_MBOX 0x0028 /* Backplane to PCI Mailbox */
33#define SSB_PCICORE_MBOX_F0_0 0x00000100 /* PCI function 0, INT 0 */
34#define SSB_PCICORE_MBOX_F0_1 0x00000200 /* PCI function 0, INT 1 */
35#define SSB_PCICORE_MBOX_F1_0 0x00000400 /* PCI function 1, INT 0 */
36#define SSB_PCICORE_MBOX_F1_1 0x00000800 /* PCI function 1, INT 1 */
37#define SSB_PCICORE_MBOX_F2_0 0x00001000 /* PCI function 2, INT 0 */
38#define SSB_PCICORE_MBOX_F2_1 0x00002000 /* PCI function 2, INT 1 */
39#define SSB_PCICORE_MBOX_F3_0 0x00004000 /* PCI function 3, INT 0 */
40#define SSB_PCICORE_MBOX_F3_1 0x00008000 /* PCI function 3, INT 1 */
41#define SSB_PCICORE_BCAST_ADDR 0x0050 /* Backplane Broadcast Address */
42#define SSB_PCICORE_BCAST_ADDR_MASK 0x000000FF
43#define SSB_PCICORE_BCAST_DATA 0x0054 /* Backplane Broadcast Data */
44#define SSB_PCICORE_GPIO_IN 0x0060 /* rev >= 2 only */
45#define SSB_PCICORE_GPIO_OUT 0x0064 /* rev >= 2 only */
46#define SSB_PCICORE_GPIO_ENABLE 0x0068 /* rev >= 2 only */
47#define SSB_PCICORE_GPIO_CTL 0x006C /* rev >= 2 only */
48#define SSB_PCICORE_SBTOPCI0 0x0100 /* Backplane to PCI translation 0 (sbtopci0) */
49#define SSB_PCICORE_SBTOPCI0_MASK 0xFC000000
50#define SSB_PCICORE_SBTOPCI1 0x0104 /* Backplane to PCI translation 1 (sbtopci1) */
51#define SSB_PCICORE_SBTOPCI1_MASK 0xFC000000
52#define SSB_PCICORE_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
53#define SSB_PCICORE_SBTOPCI2_MASK 0xC0000000
54
55/* SBtoPCIx */
56#define SSB_PCICORE_SBTOPCI_MEM 0x00000000
57#define SSB_PCICORE_SBTOPCI_IO 0x00000001
58#define SSB_PCICORE_SBTOPCI_CFG0 0x00000002
59#define SSB_PCICORE_SBTOPCI_CFG1 0x00000003
60#define SSB_PCICORE_SBTOPCI_PREF 0x00000004 /* Prefetch enable */
61#define SSB_PCICORE_SBTOPCI_BURST 0x00000008 /* Burst enable */
62#define SSB_PCICORE_SBTOPCI_MRM 0x00000020 /* Memory Read Multiple */
63#define SSB_PCICORE_SBTOPCI_RC 0x00000030 /* Read Command mask (rev >= 11) */
64#define SSB_PCICORE_SBTOPCI_RC_READ 0x00000000 /* Memory read */
65#define SSB_PCICORE_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
66#define SSB_PCICORE_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
67
68
69/* PCIcore specific boardflags */
70#define SSB_PCICORE_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
71
72
73struct ssb_pcicore {
74 struct ssb_device *dev;
75 u8 setup_done:1;
76 u8 hostmode:1;
77 u8 cardbusmode:1;
78};
79
80extern void ssb_pcicore_init(struct ssb_pcicore *pc);
81
82/* Enable IRQ routing for a specific device */
83extern int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
84 struct ssb_device *dev);
85
86
87#else /* CONFIG_SSB_DRIVER_PCICORE */
88
89
90struct ssb_pcicore {
91};
92
93static inline
94void ssb_pcicore_init(struct ssb_pcicore *pc)
95{
96}
97
98static inline
99int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
100 struct ssb_device *dev)
101{
102 return 0;
103}
104
105#endif /* CONFIG_SSB_DRIVER_PCICORE */
106#endif /* LINUX_SSB_PCICORE_H_ */
diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h
new file mode 100644
index 000000000000..47c7c71a5acf
--- /dev/null
+++ b/include/linux/ssb/ssb_regs.h
@@ -0,0 +1,292 @@
1#ifndef LINUX_SSB_REGS_H_
2#define LINUX_SSB_REGS_H_
3
4
5/* SiliconBackplane Address Map.
6 * All regions may not exist on all chips.
7 */
8#define SSB_SDRAM_BASE 0x00000000U /* Physical SDRAM */
9#define SSB_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
10#define SSB_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
11#define SSB_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
12#define SSB_ENUM_BASE 0x18000000U /* Enumeration space base */
13#define SSB_ENUM_LIMIT 0x18010000U /* Enumeration space limit */
14
15#define SSB_FLASH2 0x1c000000U /* Flash Region 2 (region 1 shadowed here) */
16#define SSB_FLASH2_SZ 0x02000000U /* Size of Flash Region 2 */
17
18#define SSB_EXTIF_BASE 0x1f000000U /* External Interface region base address */
19#define SSB_FLASH1 0x1fc00000U /* Flash Region 1 */
20#define SSB_FLASH1_SZ 0x00400000U /* Size of Flash Region 1 */
21
22#define SSB_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
23#define SSB_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
24#define SSB_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
25#define SSB_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
26#define SSB_EUART (SSB_EXTIF_BASE + 0x00800000)
27#define SSB_LED (SSB_EXTIF_BASE + 0x00900000)
28
29
30/* Enumeration space constants */
31#define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */
32#define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
33
34
35/* mips address */
36#define SSB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
37
38
39/* SSB PCI config space registers. */
40#define SSB_PMCSR 0x44
41#define SSB_PE 0x100
42#define SSB_BAR0_WIN 0x80 /* Backplane address space 0 */
43#define SSB_BAR1_WIN 0x84 /* Backplane address space 1 */
44#define SSB_SPROMCTL 0x88 /* SPROM control */
45#define SSB_SPROMCTL_WE 0x10 /* SPROM write enable */
46#define SSB_BAR1_CONTROL 0x8c /* Address space 1 burst control */
47#define SSB_PCI_IRQS 0x90 /* PCI interrupts */
48#define SSB_PCI_IRQMASK 0x94 /* PCI IRQ control and mask (pcirev >= 6 only) */
49#define SSB_BACKPLANE_IRQS 0x98 /* Backplane Interrupts */
50#define SSB_GPIO_IN 0xB0 /* GPIO Input (pcirev >= 3 only) */
51#define SSB_GPIO_OUT 0xB4 /* GPIO Output (pcirev >= 3 only) */
52#define SSB_GPIO_OUT_ENABLE 0xB8 /* GPIO Output Enable/Disable (pcirev >= 3 only) */
53#define SSB_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
54#define SSB_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
55#define SSB_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
56#define SSB_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
57
58
59#define SSB_BAR0_MAX_RETRIES 50
60
61/* Silicon backplane configuration register definitions */
62#define SSB_IPSFLAG 0x0F08
63#define SSB_IPSFLAG_IRQ1 0x0000003F /* which sbflags get routed to mips interrupt 1 */
64#define SSB_IPSFLAG_IRQ1_SHIFT 0
65#define SSB_IPSFLAG_IRQ2 0x00003F00 /* which sbflags get routed to mips interrupt 2 */
66#define SSB_IPSFLAG_IRQ2_SHIFT 8
67#define SSB_IPSFLAG_IRQ3 0x003F0000 /* which sbflags get routed to mips interrupt 3 */
68#define SSB_IPSFLAG_IRQ3_SHIFT 16
69#define SSB_IPSFLAG_IRQ4 0x3F000000 /* which sbflags get routed to mips interrupt 4 */
70#define SSB_IPSFLAG_IRQ4_SHIFT 24
71#define SSB_TPSFLAG 0x0F18
72#define SSB_TPSFLAG_BPFLAG 0x0000003F /* Backplane flag # */
73#define SSB_TPSFLAG_ALWAYSIRQ 0x00000040 /* IRQ is always sent on the Backplane */
74#define SSB_TMERRLOGA 0x0F48
75#define SSB_TMERRLOG 0x0F50
76#define SSB_ADMATCH3 0x0F60
77#define SSB_ADMATCH2 0x0F68
78#define SSB_ADMATCH1 0x0F70
79#define SSB_IMSTATE 0x0F90 /* SB Initiator Agent State */
80#define SSB_IMSTATE_PC 0x0000000f /* Pipe Count */
81#define SSB_IMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */
82#define SSB_IMSTATE_AP_BOTH 0x00000000 /* Use both timeslices and token */
83#define SSB_IMSTATE_AP_TS 0x00000010 /* Use timeslices only */
84#define SSB_IMSTATE_AP_TK 0x00000020 /* Use token only */
85#define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
86#define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
87#define SSB_IMSTATE_TO 0x00040000 /* Timeout */
88#define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
89#define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
90#define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
91#define SSB_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */
92#define SSB_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */
93#define SSB_INTVEC_USB 0x00000010 /* Enable interrupts for usb */
94#define SSB_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */
95#define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
96#define SSB_TMSLOW 0x0F98 /* SB Target State Low */
97#define SSB_TMSLOW_RESET 0x00000001 /* Reset */
98#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
99#define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
100#define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
101#define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
102#define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */
103#define SSB_TMSLOW_BE 0x80000000 /* BIST Enable */
104#define SSB_TMSHIGH 0x0F9C /* SB Target State High */
105#define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
106#define SSB_TMSHIGH_INT 0x00000002 /* Interrupt */
107#define SSB_TMSHIGH_BUSY 0x00000004 /* Busy */
108#define SSB_TMSHIGH_TO 0x00000020 /* Timeout. Backplane rev >= 2.3 only */
109#define SSB_TMSHIGH_COREFL 0x1FFF0000 /* Core specific flags */
110#define SSB_TMSHIGH_COREFL_SHIFT 16
111#define SSB_TMSHIGH_DMA64 0x10000000 /* 64bit DMA supported */
112#define SSB_TMSHIGH_GCR 0x20000000 /* Gated Clock Request */
113#define SSB_TMSHIGH_BISTF 0x40000000 /* BIST Failed */
114#define SSB_TMSHIGH_BISTD 0x80000000 /* BIST Done */
115#define SSB_BWA0 0x0FA0
116#define SSB_IMCFGLO 0x0FA8
117#define SSB_IMCFGLO_SERTO 0x00000007 /* Service timeout */
118#define SSB_IMCFGLO_REQTO 0x00000070 /* Request timeout */
119#define SSB_IMCFGLO_REQTO_SHIFT 4
120#define SSB_IMCFGLO_CONNID 0x00FF0000 /* Connection ID */
121#define SSB_IMCFGLO_CONNID_SHIFT 16
122#define SSB_IMCFGHI 0x0FAC
123#define SSB_ADMATCH0 0x0FB0
124#define SSB_TMCFGLO 0x0FB8
125#define SSB_TMCFGHI 0x0FBC
126#define SSB_BCONFIG 0x0FC0
127#define SSB_BSTATE 0x0FC8
128#define SSB_ACTCFG 0x0FD8
129#define SSB_FLAGST 0x0FE8
130#define SSB_IDLOW 0x0FF8
131#define SSB_IDLOW_CFGSP 0x00000003 /* Config Space */
132#define SSB_IDLOW_ADDRNGE 0x00000038 /* Address Ranges supported */
133#define SSB_IDLOW_ADDRNGE_SHIFT 3
134#define SSB_IDLOW_SYNC 0x00000040
135#define SSB_IDLOW_INITIATOR 0x00000080
136#define SSB_IDLOW_MIBL 0x00000F00 /* Minimum Backplane latency */
137#define SSB_IDLOW_MIBL_SHIFT 8
138#define SSB_IDLOW_MABL 0x0000F000 /* Maximum Backplane latency */
139#define SSB_IDLOW_MABL_SHIFT 12
140#define SSB_IDLOW_TIF 0x00010000 /* This Initiator is first */
141#define SSB_IDLOW_CCW 0x000C0000 /* Cycle counter width */
142#define SSB_IDLOW_CCW_SHIFT 18
143#define SSB_IDLOW_TPT 0x00F00000 /* Target ports */
144#define SSB_IDLOW_TPT_SHIFT 20
145#define SSB_IDLOW_INITP 0x0F000000 /* Initiator ports */
146#define SSB_IDLOW_INITP_SHIFT 24
147#define SSB_IDLOW_SSBREV 0xF0000000 /* Sonics Backplane Revision code */
148#define SSB_IDLOW_SSBREV_22 0x00000000 /* <= 2.2 */
149#define SSB_IDLOW_SSBREV_23 0x10000000 /* 2.3 */
150#define SSB_IDHIGH 0x0FFC /* SB Identification High */
151#define SSB_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */
152#define SSB_IDHIGH_CC 0x00008FF0 /* Core Code */
153#define SSB_IDHIGH_CC_SHIFT 4
154#define SSB_IDHIGH_RCHI 0x00007000 /* Revision Code (high part) */
155#define SSB_IDHIGH_RCHI_SHIFT 8 /* yes, shift 8 is right */
156#define SSB_IDHIGH_VC 0xFFFF0000 /* Vendor Code */
157#define SSB_IDHIGH_VC_SHIFT 16
158
159/* SPROM shadow area. If not otherwise noted, fields are
160 * two bytes wide. Note that the SPROM can _only_ be read
161 * in two-byte quantinies.
162 */
163#define SSB_SPROMSIZE_WORDS 64
164#define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
165#define SSB_SPROM_BASE 0x1000
166#define SSB_SPROM_REVISION 0x107E
167#define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
168#define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
169#define SSB_SPROM_REVISION_CRC_SHIFT 8
170/* SPROM Revision 1 */
171#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
172#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
173#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
174#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
175#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
176#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
177#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
178#define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
179#define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
180#define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
181#define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
182#define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
183#define SSB_SPROM1_BINF 0x105C /* Board info */
184#define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
185#define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
186#define SSB_SPROM1_BINF_CCODE_SHIFT 8
187#define SSB_SPROM1_BINF_ANTA 0x3000 /* Available A-PHY antennas */
188#define SSB_SPROM1_BINF_ANTA_SHIFT 12
189#define SSB_SPROM1_BINF_ANTBG 0xC000 /* Available B-PHY antennas */
190#define SSB_SPROM1_BINF_ANTBG_SHIFT 14
191#define SSB_SPROM1_PA0B0 0x105E
192#define SSB_SPROM1_PA0B1 0x1060
193#define SSB_SPROM1_PA0B2 0x1062
194#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
195#define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
196#define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
197#define SSB_SPROM1_GPIOA_P1_SHIFT 8
198#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
199#define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
200#define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
201#define SSB_SPROM1_GPIOB_P3_SHIFT 8
202#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
203#define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
204#define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
205#define SSB_SPROM1_MAXPWR_A_SHIFT 8
206#define SSB_SPROM1_PA1B0 0x106A
207#define SSB_SPROM1_PA1B1 0x106C
208#define SSB_SPROM1_PA1B2 0x106E
209#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
210#define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
211#define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
212#define SSB_SPROM1_ITSSI_A_SHIFT 8
213#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
214#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
215#define SSB_SPROM1_AGAIN_A 0x00FF /* A-PHY */
216#define SSB_SPROM1_AGAIN_BG 0xFF00 /* B-PHY and G-PHY */
217#define SSB_SPROM1_AGAIN_BG_SHIFT 8
218#define SSB_SPROM1_OEM 0x1076 /* 8 bytes OEM string (rev 1 only) */
219/* SPROM Revision 2 (inherits from rev 1) */
220#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
221#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
222#define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
223#define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
224#define SSB_SPROM2_MAXP_A_LO_SHIFT 8
225#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
226#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
227#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
228#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
229#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
230#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
231#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
232#define SSB_SPROM2_OPO_VALUE 0x00FF
233#define SSB_SPROM2_OPO_UNUSED 0xFF00
234#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
235/* SPROM Revision 3 (inherits from rev 2) */
236#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
237#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
238#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
239#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
240#define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
241#define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
242#define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
243#define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
244#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
245#define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
246#define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
247#define SSB_SPROM3_CCKPO_2M_SHIFT 4
248#define SSB_SPROM3_CCKPO_55M 0x0F00 /* 5.5M Rate PO */
249#define SSB_SPROM3_CCKPO_55M_SHIFT 8
250#define SSB_SPROM3_CCKPO_11M 0xF000 /* 11M Rate PO */
251#define SSB_SPROM3_CCKPO_11M_SHIFT 12
252#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
253
254/* Values for SSB_SPROM1_BINF_CCODE */
255enum {
256 SSB_SPROM1CCODE_WORLD = 0,
257 SSB_SPROM1CCODE_THAILAND,
258 SSB_SPROM1CCODE_ISRAEL,
259 SSB_SPROM1CCODE_JORDAN,
260 SSB_SPROM1CCODE_CHINA,
261 SSB_SPROM1CCODE_JAPAN,
262 SSB_SPROM1CCODE_USA_CANADA_ANZ,
263 SSB_SPROM1CCODE_EUROPE,
264 SSB_SPROM1CCODE_USA_LOW,
265 SSB_SPROM1CCODE_JAPAN_HIGH,
266 SSB_SPROM1CCODE_ALL,
267 SSB_SPROM1CCODE_NONE,
268};
269
270/* Address-Match values and masks (SSB_ADMATCHxxx) */
271#define SSB_ADM_TYPE 0x00000003 /* Address type */
272#define SSB_ADM_TYPE0 0
273#define SSB_ADM_TYPE1 1
274#define SSB_ADM_TYPE2 2
275#define SSB_ADM_AD64 0x00000004
276#define SSB_ADM_SZ0 0x000000F8 /* Type0 size */
277#define SSB_ADM_SZ0_SHIFT 3
278#define SSB_ADM_SZ1 0x000001F8 /* Type1 size */
279#define SSB_ADM_SZ1_SHIFT 3
280#define SSB_ADM_SZ2 0x000001F8 /* Type2 size */
281#define SSB_ADM_SZ2_SHIFT 3
282#define SSB_ADM_EN 0x00000400 /* Enable */
283#define SSB_ADM_NEG 0x00000800 /* Negative decode */
284#define SSB_ADM_BASE0 0xFFFFFF00 /* Type0 base address */
285#define SSB_ADM_BASE0_SHIFT 8
286#define SSB_ADM_BASE1 0xFFFFF000 /* Type1 base address for the core */
287#define SSB_ADM_BASE1_SHIFT 12
288#define SSB_ADM_BASE2 0xFFFF0000 /* Type2 base address for the core */
289#define SSB_ADM_BASE2_SHIFT 16
290
291
292#endif /* LINUX_SSB_REGS_H_ */
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