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authorLarry Finger <Larry.Finger@lwfinger.net>2007-11-09 17:56:25 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:04:41 -0500
commitc272ef4403c271799a7f09a4ab7a236c86643843 (patch)
tree8f2baf9c11159044b42233cea56aa5a62dcd7500 /include/linux/ssb
parentac82fab44f6b981e3f6b53784e2f23838f4908e1 (diff)
ssb: Convert to use of the new SPROM structure
In disagreement with the SPROM specs, revision 3 devices appear to have moved the MAC address. Change ssb to handle the revision 4 SPROM, which is a different size. This change in size is handled by adding a new variable to the ssb_sprom struct and using it whenever possible. For those routines that do not have access to this structure, a 'u16 size' argument is added. The new PCI_ID for the BCM4328 is also added. Testing of the Revision 4 SPROM, which is used on the BCM4328, was done by Michael Gerdau <mgerdau@tiscali.de>. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'include/linux/ssb')
-rw-r--r--include/linux/ssb/ssb.h1
-rw-r--r--include/linux/ssb/ssb_regs.h38
2 files changed, 28 insertions, 11 deletions
diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h
index cdd8a2fd4a69..745de2aac85f 100644
--- a/include/linux/ssb/ssb.h
+++ b/include/linux/ssb/ssb.h
@@ -308,6 +308,7 @@ struct ssb_bus {
308 /* ID information about the Chip. */ 308 /* ID information about the Chip. */
309 u16 chip_id; 309 u16 chip_id;
310 u16 chip_rev; 310 u16 chip_rev;
311 u16 sprom_size; /* number of words in sprom */
311 u8 chip_package; 312 u8 chip_package;
312 313
313 /* List of devices (cores) on the backplane. */ 314 /* List of devices (cores) on the backplane. */
diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h
index bcebcffd448b..96bba69b1271 100644
--- a/include/linux/ssb/ssb_regs.h
+++ b/include/linux/ssb/ssb_regs.h
@@ -147,6 +147,10 @@
147#define SSB_IDLOW_SSBREV 0xF0000000 /* Sonics Backplane Revision code */ 147#define SSB_IDLOW_SSBREV 0xF0000000 /* Sonics Backplane Revision code */
148#define SSB_IDLOW_SSBREV_22 0x00000000 /* <= 2.2 */ 148#define SSB_IDLOW_SSBREV_22 0x00000000 /* <= 2.2 */
149#define SSB_IDLOW_SSBREV_23 0x10000000 /* 2.3 */ 149#define SSB_IDLOW_SSBREV_23 0x10000000 /* 2.3 */
150#define SSB_IDLOW_SSBREV_24 0x40000000 /* ?? Found in BCM4328 */
151#define SSB_IDLOW_SSBREV_25 0x50000000 /* ?? Not Found yet */
152#define SSB_IDLOW_SSBREV_26 0x60000000 /* ?? Found in some BCM4311/2 */
153#define SSB_IDLOW_SSBREV_27 0x70000000 /* ?? Found in some BCM4311/2 */
150#define SSB_IDHIGH 0x0FFC /* SB Identification High */ 154#define SSB_IDHIGH 0x0FFC /* SB Identification High */
151#define SSB_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */ 155#define SSB_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */
152#define SSB_IDHIGH_CC 0x00008FF0 /* Core Code */ 156#define SSB_IDHIGH_CC 0x00008FF0 /* Core Code */
@@ -162,6 +166,10 @@
162 */ 166 */
163#define SSB_SPROMSIZE_WORDS 64 167#define SSB_SPROMSIZE_WORDS 64
164#define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16)) 168#define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
169#define SSB_SPROMSIZE_WORDS_R123 64
170#define SSB_SPROMSIZE_WORDS_R4 220
171#define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
172#define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
165#define SSB_SPROM_BASE 0x1000 173#define SSB_SPROM_BASE 0x1000
166#define SSB_SPROM_REVISION 0x107E 174#define SSB_SPROM_REVISION 0x107E
167#define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */ 175#define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
@@ -232,7 +240,10 @@
232#define SSB_SPROM2_OPO_VALUE 0x00FF 240#define SSB_SPROM2_OPO_VALUE 0x00FF
233#define SSB_SPROM2_OPO_UNUSED 0xFF00 241#define SSB_SPROM2_OPO_UNUSED 0xFF00
234#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */ 242#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
235/* SPROM Revision 3 (inherits from rev 2) */ 243/* SPROM Revision 3 (inherits most data from rev 2) */
244#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
245#define SSB_SPROM3_ET0MAC 0x1050 /* 6 bytes MAC address for Ethernet ?? */
246#define SSB_SPROM3_ET1MAC 0x1050 /* 6 bytes MAC address for 802.11a ?? */
236#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */ 247#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
237#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */ 248#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
238#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */ 249#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
@@ -250,8 +261,10 @@
250#define SSB_SPROM3_CCKPO_11M 0xF000 /* 11M Rate PO */ 261#define SSB_SPROM3_CCKPO_11M 0xF000 /* 11M Rate PO */
251#define SSB_SPROM3_CCKPO_11M_SHIFT 12 262#define SSB_SPROM3_CCKPO_11M_SHIFT 12
252#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */ 263#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
253/* SPROM Revision 4 */ 264/* SPROM Revision 4 entries with ?? in comment are unknown */
254#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for b/g */ 265#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for b/g */
266#define SSB_SPROM4_ET0MAC 0x1018 /* 6 bytes MAC address for Ethernet ?? */
267#define SSB_SPROM4_ET1MAC 0x1018 /* 6 bytes MAC address for 802.11a ?? */
255#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings */ 268#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings */
256#define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ 269#define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
257#define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ 270#define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
@@ -263,19 +276,22 @@
263#define SSB_SPROM4_ANT_BG 0x105C /* B/G Antennas */ 276#define SSB_SPROM4_ANT_BG 0x105C /* B/G Antennas */
264#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */ 277#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
265#define SSB_SPROM4_AGAIN 0x105E /* Antenna Gain (in dBm Q5.2) */ 278#define SSB_SPROM4_AGAIN 0x105E /* Antenna Gain (in dBm Q5.2) */
279#define SSB_SPROM4_AGAIN_0 0x00FF /* Antenna 0 */
280#define SSB_SPROM4_AGAIN_1 0xFF00 /* Antenna 1 */
281#define SSB_SPROM4_AGAIN_1_SHIFT 8
266#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */ 282#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
267#define SSB_SPROM4_MAXP_A 0x1000 /* Max Power A */ 283#define SSB_SPROM4_MAXP_A 0x1000 /* Max Power A ?? */
268#define SSB_SPROM4_MAXP_A_HI 0x00FF /* Mask for Hi */ 284#define SSB_SPROM4_MAXP_A_HI 0x00FF /* Mask for Hi */
269#define SSB_SPROM4_MAXP_A_LO 0xFF00 /* Mask for Lo */ 285#define SSB_SPROM4_MAXP_A_LO 0xFF00 /* Mask for Lo */
270#define SSB_SPROM4_MAXP_A_LO_SHIFT 16 /* Shift for Lo */ 286#define SSB_SPROM4_MAXP_A_LO_SHIFT 16 /* Shift for Lo */
271#define SSB_SPROM4_PA1LOB0 0x1000 287#define SSB_SPROM4_PA1LOB0 0x1000 /* ?? */
272#define SSB_SPROM4_PA1LOB1 0x1000 288#define SSB_SPROM4_PA1LOB1 0x1000 /* ?? */
273#define SSB_SPROM4_PA1LOB2 0x1000 289#define SSB_SPROM4_PA1LOB2 0x1000 /* ?? */
274#define SSB_SPROM4_PA1HIB0 0x1000 290#define SSB_SPROM4_PA1HIB0 0x1000 /* ?? */
275#define SSB_SPROM4_PA1HIB1 0x1000 291#define SSB_SPROM4_PA1HIB1 0x1000 /* ?? */
276#define SSB_SPROM4_PA1HIB2 0x1000 292#define SSB_SPROM4_PA1HIB2 0x1000 /* ?? */
277#define SSB_SPROM4_OPO 0x1000 293#define SSB_SPROM4_OPO 0x1000 /* ?? */
278#define SSB_SPROM4_OPO_VALUE 0x0000 294#define SSB_SPROM4_OPO_VALUE 0x0000 /* ?? */
279#define SSB_SPROM4_GPIOLDC 0x105A /* LED Powersave Duty Cycle */ 295#define SSB_SPROM4_GPIOLDC 0x105A /* LED Powersave Duty Cycle */
280#define SSB_SPROM4_GPIOLDC_OFF 0x0000FF00 /* Off Count */ 296#define SSB_SPROM4_GPIOLDC_OFF 0x0000FF00 /* Off Count */
281#define SSB_SPROM4_GPIOLDC_OFF_SHIFT 8 297#define SSB_SPROM4_GPIOLDC_OFF_SHIFT 8