aboutsummaryrefslogtreecommitdiffstats
path: root/include/linux/ssb
diff options
context:
space:
mode:
authorRafał Miłecki <zajec5@gmail.com>2010-03-31 16:54:18 -0400
committerJohn W. Linville <linville@tuxdriver.com>2010-04-26 13:51:08 -0400
commit0a182fd88f8180b342f753f04c7d5507b5891c96 (patch)
tree056f2ec8a8f0600175fce41468edfd7d0b69cef3 /include/linux/ssb
parentea2db495f92ad2cf3301623e60cb95b4062bc484 (diff)
ssb: Use relative offsets for SPROM
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'include/linux/ssb')
-rw-r--r--include/linux/ssb/ssb_regs.h196
1 files changed, 98 insertions, 98 deletions
diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h
index b8be23ce1915..8990e30c657a 100644
--- a/include/linux/ssb/ssb_regs.h
+++ b/include/linux/ssb/ssb_regs.h
@@ -172,25 +172,25 @@
172#define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16)) 172#define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
173#define SSB_SPROM_BASE1 0x1000 173#define SSB_SPROM_BASE1 0x1000
174#define SSB_SPROM_BASE31 0x0800 174#define SSB_SPROM_BASE31 0x0800
175#define SSB_SPROM_REVISION 0x107E 175#define SSB_SPROM_REVISION 0x007E
176#define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */ 176#define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
177#define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */ 177#define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
178#define SSB_SPROM_REVISION_CRC_SHIFT 8 178#define SSB_SPROM_REVISION_CRC_SHIFT 8
179 179
180/* SPROM Revision 1 */ 180/* SPROM Revision 1 */
181#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */ 181#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
182#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */ 182#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
183#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */ 183#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
184#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */ 184#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
185#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */ 185#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
186#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */ 186#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
187#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */ 187#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
188#define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ 188#define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
189#define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ 189#define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
190#define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5 190#define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
191#define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ 191#define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
192#define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ 192#define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
193#define SSB_SPROM1_BINF 0x105C /* Board info */ 193#define SSB_SPROM1_BINF 0x005C /* Board info */
194#define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */ 194#define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
195#define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */ 195#define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
196#define SSB_SPROM1_BINF_CCODE_SHIFT 8 196#define SSB_SPROM1_BINF_CCODE_SHIFT 8
@@ -198,63 +198,63 @@
198#define SSB_SPROM1_BINF_ANTBG_SHIFT 12 198#define SSB_SPROM1_BINF_ANTBG_SHIFT 12
199#define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */ 199#define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
200#define SSB_SPROM1_BINF_ANTA_SHIFT 14 200#define SSB_SPROM1_BINF_ANTA_SHIFT 14
201#define SSB_SPROM1_PA0B0 0x105E 201#define SSB_SPROM1_PA0B0 0x005E
202#define SSB_SPROM1_PA0B1 0x1060 202#define SSB_SPROM1_PA0B1 0x0060
203#define SSB_SPROM1_PA0B2 0x1062 203#define SSB_SPROM1_PA0B2 0x0062
204#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */ 204#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
205#define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */ 205#define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
206#define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */ 206#define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
207#define SSB_SPROM1_GPIOA_P1_SHIFT 8 207#define SSB_SPROM1_GPIOA_P1_SHIFT 8
208#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */ 208#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
209#define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */ 209#define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
210#define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */ 210#define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
211#define SSB_SPROM1_GPIOB_P3_SHIFT 8 211#define SSB_SPROM1_GPIOB_P3_SHIFT 8
212#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */ 212#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
213#define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */ 213#define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
214#define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */ 214#define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
215#define SSB_SPROM1_MAXPWR_A_SHIFT 8 215#define SSB_SPROM1_MAXPWR_A_SHIFT 8
216#define SSB_SPROM1_PA1B0 0x106A 216#define SSB_SPROM1_PA1B0 0x006A
217#define SSB_SPROM1_PA1B1 0x106C 217#define SSB_SPROM1_PA1B1 0x006C
218#define SSB_SPROM1_PA1B2 0x106E 218#define SSB_SPROM1_PA1B2 0x006E
219#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */ 219#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
220#define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/ 220#define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
221#define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */ 221#define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
222#define SSB_SPROM1_ITSSI_A_SHIFT 8 222#define SSB_SPROM1_ITSSI_A_SHIFT 8
223#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */ 223#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
224#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */ 224#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
225#define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */ 225#define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
226#define SSB_SPROM1_AGAIN_BG_SHIFT 0 226#define SSB_SPROM1_AGAIN_BG_SHIFT 0
227#define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */ 227#define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
228#define SSB_SPROM1_AGAIN_A_SHIFT 8 228#define SSB_SPROM1_AGAIN_A_SHIFT 8
229 229
230/* SPROM Revision 2 (inherits from rev 1) */ 230/* SPROM Revision 2 (inherits from rev 1) */
231#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */ 231#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
232#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */ 232#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
233#define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */ 233#define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
234#define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */ 234#define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
235#define SSB_SPROM2_MAXP_A_LO_SHIFT 8 235#define SSB_SPROM2_MAXP_A_LO_SHIFT 8
236#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */ 236#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
237#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */ 237#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
238#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */ 238#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
239#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */ 239#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
240#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */ 240#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
241#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */ 241#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
242#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */ 242#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
243#define SSB_SPROM2_OPO_VALUE 0x00FF 243#define SSB_SPROM2_OPO_VALUE 0x00FF
244#define SSB_SPROM2_OPO_UNUSED 0xFF00 244#define SSB_SPROM2_OPO_UNUSED 0xFF00
245#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */ 245#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
246 246
247/* SPROM Revision 3 (inherits most data from rev 2) */ 247/* SPROM Revision 3 (inherits most data from rev 2) */
248#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */ 248#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
249#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */ 249#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
250#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */ 250#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
251#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */ 251#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
252#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */ 252#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
253#define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */ 253#define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
254#define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8 254#define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
255#define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */ 255#define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
256#define SSB_SPROM3_GPIOLDC_ON_SHIFT 16 256#define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
257#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */ 257#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
258#define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */ 258#define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
259#define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */ 259#define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
260#define SSB_SPROM3_CCKPO_2M_SHIFT 4 260#define SSB_SPROM3_CCKPO_2M_SHIFT 4
@@ -265,100 +265,100 @@
265#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */ 265#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
266 266
267/* SPROM Revision 4 */ 267/* SPROM Revision 4 */
268#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */ 268#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
269#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */ 269#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
270#define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ 270#define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
271#define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ 271#define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
272#define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 272#define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
273#define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ 273#define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
274#define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ 274#define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
275#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */ 275#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
276#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */ 276#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
277#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ 277#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
278#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 278#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
279#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ 279#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
280#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 280#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
281#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */ 281#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
282#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */ 282#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
283#define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */ 283#define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
284#define SSB_SPROM4_AGAIN0_SHIFT 0 284#define SSB_SPROM4_AGAIN0_SHIFT 0
285#define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */ 285#define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
286#define SSB_SPROM4_AGAIN1_SHIFT 8 286#define SSB_SPROM4_AGAIN1_SHIFT 8
287#define SSB_SPROM4_AGAIN23 0x1060 287#define SSB_SPROM4_AGAIN23 0x0060
288#define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */ 288#define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
289#define SSB_SPROM4_AGAIN2_SHIFT 0 289#define SSB_SPROM4_AGAIN2_SHIFT 0
290#define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */ 290#define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
291#define SSB_SPROM4_AGAIN3_SHIFT 8 291#define SSB_SPROM4_AGAIN3_SHIFT 8
292#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */ 292#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
293#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */ 293#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
294#define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */ 294#define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
295#define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ 295#define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
296#define SSB_SPROM4_ITSSI_BG_SHIFT 8 296#define SSB_SPROM4_ITSSI_BG_SHIFT 8
297#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */ 297#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
298#define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */ 298#define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
299#define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */ 299#define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
300#define SSB_SPROM4_ITSSI_A_SHIFT 8 300#define SSB_SPROM4_ITSSI_A_SHIFT 8
301#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */ 301#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
302#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */ 302#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
303#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */ 303#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
304#define SSB_SPROM4_GPIOA_P1_SHIFT 8 304#define SSB_SPROM4_GPIOA_P1_SHIFT 8
305#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */ 305#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
306#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */ 306#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
307#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */ 307#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
308#define SSB_SPROM4_GPIOB_P3_SHIFT 8 308#define SSB_SPROM4_GPIOB_P3_SHIFT 8
309#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */ 309#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
310#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */ 310#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
311#define SSB_SPROM4_PA0B2 0x1086 311#define SSB_SPROM4_PA0B2 0x0086
312#define SSB_SPROM4_PA1B0 0x108E 312#define SSB_SPROM4_PA1B0 0x008E
313#define SSB_SPROM4_PA1B1 0x1090 313#define SSB_SPROM4_PA1B1 0x0090
314#define SSB_SPROM4_PA1B2 0x1092 314#define SSB_SPROM4_PA1B2 0x0092
315 315
316/* SPROM Revision 5 (inherits most data from rev 4) */ 316/* SPROM Revision 5 (inherits most data from rev 4) */
317#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */ 317#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
318#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */ 318#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
319#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */ 319#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
320#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */ 320#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
321#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */ 321#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
322#define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */ 322#define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
323#define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */ 323#define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
324#define SSB_SPROM5_GPIOA_P1_SHIFT 8 324#define SSB_SPROM5_GPIOA_P1_SHIFT 8
325#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */ 325#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
326#define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */ 326#define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
327#define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */ 327#define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
328#define SSB_SPROM5_GPIOB_P3_SHIFT 8 328#define SSB_SPROM5_GPIOB_P3_SHIFT 8
329 329
330/* SPROM Revision 8 */ 330/* SPROM Revision 8 */
331#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */ 331#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
332#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */ 332#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
333#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */ 333#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
334#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */ 334#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
335#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */ 335#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
336#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */ 336#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
337#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */ 337#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
338#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/ 338#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
339#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ 339#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
340#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8 340#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
341#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ 341#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
342#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0 342#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
343#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */ 343#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
344#define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */ 344#define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
345#define SSB_SPROM8_AGAIN0_SHIFT 0 345#define SSB_SPROM8_AGAIN0_SHIFT 0
346#define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */ 346#define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
347#define SSB_SPROM8_AGAIN1_SHIFT 8 347#define SSB_SPROM8_AGAIN1_SHIFT 8
348#define SSB_SPROM8_AGAIN23 0x10A0 348#define SSB_SPROM8_AGAIN23 0x00A0
349#define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */ 349#define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
350#define SSB_SPROM8_AGAIN2_SHIFT 0 350#define SSB_SPROM8_AGAIN2_SHIFT 0
351#define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */ 351#define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
352#define SSB_SPROM8_AGAIN3_SHIFT 8 352#define SSB_SPROM8_AGAIN3_SHIFT 8
353#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */ 353#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
354#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */ 354#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
355#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */ 355#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
356#define SSB_SPROM8_GPIOA_P1_SHIFT 8 356#define SSB_SPROM8_GPIOA_P1_SHIFT 8
357#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */ 357#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
358#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */ 358#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
359#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */ 359#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
360#define SSB_SPROM8_GPIOB_P3_SHIFT 8 360#define SSB_SPROM8_GPIOB_P3_SHIFT 8
361#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */ 361#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
362#define SSB_SPROM8_RSSISMF2G 0x000F 362#define SSB_SPROM8_RSSISMF2G 0x000F
363#define SSB_SPROM8_RSSISMC2G 0x00F0 363#define SSB_SPROM8_RSSISMC2G 0x00F0
364#define SSB_SPROM8_RSSISMC2G_SHIFT 4 364#define SSB_SPROM8_RSSISMC2G_SHIFT 4
@@ -366,7 +366,7 @@
366#define SSB_SPROM8_RSSISAV2G_SHIFT 8 366#define SSB_SPROM8_RSSISAV2G_SHIFT 8
367#define SSB_SPROM8_BXA2G 0x1800 367#define SSB_SPROM8_BXA2G 0x1800
368#define SSB_SPROM8_BXA2G_SHIFT 11 368#define SSB_SPROM8_BXA2G_SHIFT 11
369#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */ 369#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
370#define SSB_SPROM8_RSSISMF5G 0x000F 370#define SSB_SPROM8_RSSISMF5G 0x000F
371#define SSB_SPROM8_RSSISMC5G 0x00F0 371#define SSB_SPROM8_RSSISMC5G 0x00F0
372#define SSB_SPROM8_RSSISMC5G_SHIFT 4 372#define SSB_SPROM8_RSSISMC5G_SHIFT 4
@@ -374,47 +374,47 @@
374#define SSB_SPROM8_RSSISAV5G_SHIFT 8 374#define SSB_SPROM8_RSSISAV5G_SHIFT 8
375#define SSB_SPROM8_BXA5G 0x1800 375#define SSB_SPROM8_BXA5G 0x1800
376#define SSB_SPROM8_BXA5G_SHIFT 11 376#define SSB_SPROM8_BXA5G_SHIFT 11
377#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */ 377#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
378#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */ 378#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
379#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */ 379#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
380#define SSB_SPROM8_TRI5G_SHIFT 8 380#define SSB_SPROM8_TRI5G_SHIFT 8
381#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */ 381#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
382#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */ 382#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
383#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */ 383#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
384#define SSB_SPROM8_TRI5GH_SHIFT 8 384#define SSB_SPROM8_TRI5GH_SHIFT 8
385#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */ 385#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
386#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */ 386#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
387#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */ 387#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
388#define SSB_SPROM8_RXPO5G_SHIFT 8 388#define SSB_SPROM8_RXPO5G_SHIFT 8
389#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */ 389#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
390#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */ 390#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
391#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ 391#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
392#define SSB_SPROM8_ITSSI_BG_SHIFT 8 392#define SSB_SPROM8_ITSSI_BG_SHIFT 8
393#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */ 393#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
394#define SSB_SPROM8_PA0B1 0x10C4 394#define SSB_SPROM8_PA0B1 0x00C4
395#define SSB_SPROM8_PA0B2 0x10C6 395#define SSB_SPROM8_PA0B2 0x00C6
396#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */ 396#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
397#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */ 397#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
398#define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */ 398#define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
399#define SSB_SPROM8_ITSSI_A_SHIFT 8 399#define SSB_SPROM8_ITSSI_A_SHIFT 8
400#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */ 400#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
401#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */ 401#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
402#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */ 402#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
403#define SSB_SPROM8_MAXP_AL_SHIFT 8 403#define SSB_SPROM8_MAXP_AL_SHIFT 8
404#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */ 404#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
405#define SSB_SPROM8_PA1B1 0x10CE 405#define SSB_SPROM8_PA1B1 0x00CE
406#define SSB_SPROM8_PA1B2 0x10D0 406#define SSB_SPROM8_PA1B2 0x00D0
407#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */ 407#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
408#define SSB_SPROM8_PA1LOB1 0x10D4 408#define SSB_SPROM8_PA1LOB1 0x00D4
409#define SSB_SPROM8_PA1LOB2 0x10D6 409#define SSB_SPROM8_PA1LOB2 0x00D6
410#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */ 410#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
411#define SSB_SPROM8_PA1HIB1 0x10DA 411#define SSB_SPROM8_PA1HIB1 0x00DA
412#define SSB_SPROM8_PA1HIB2 0x10DC 412#define SSB_SPROM8_PA1HIB2 0x00DC
413#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */ 413#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
414#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */ 414#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
415#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */ 415#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
416#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */ 416#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
417#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */ 417#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
418 418
419/* Values for SSB_SPROM1_BINF_CCODE */ 419/* Values for SSB_SPROM1_BINF_CCODE */
420enum { 420enum {