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authorDavid Woodhouse <dwmw2@infradead.org>2006-05-24 04:22:21 -0400
committerDavid Woodhouse <dwmw2@infradead.org>2006-05-24 04:22:21 -0400
commit66643de455c27973ac31ad6de9f859d399916842 (patch)
tree7ebed7f051879007d4b11d6aaa9e65a1bcb0b08f /include/linux/spi/spi.h
parent2c23d62abb820e19c54012520f08a198c2233a85 (diff)
parent387e2b0439026aa738a9edca15a57e5c0bcb4dfc (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts: include/asm-powerpc/unistd.h include/asm-sparc/unistd.h include/asm-sparc64/unistd.h Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Diffstat (limited to 'include/linux/spi/spi.h')
-rw-r--r--include/linux/spi/spi.h45
1 files changed, 28 insertions, 17 deletions
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index b05f1463a267..e928c0dcc297 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -31,18 +31,23 @@ extern struct bus_type spi_bus_type;
31 * @master: SPI controller used with the device. 31 * @master: SPI controller used with the device.
32 * @max_speed_hz: Maximum clock rate to be used with this chip 32 * @max_speed_hz: Maximum clock rate to be used with this chip
33 * (on this board); may be changed by the device's driver. 33 * (on this board); may be changed by the device's driver.
34 * The spi_transfer.speed_hz can override this for each transfer.
34 * @chip-select: Chipselect, distinguishing chips handled by "master". 35 * @chip-select: Chipselect, distinguishing chips handled by "master".
35 * @mode: The spi mode defines how data is clocked out and in. 36 * @mode: The spi mode defines how data is clocked out and in.
36 * This may be changed by the device's driver. 37 * This may be changed by the device's driver.
38 * The "active low" default for chipselect mode can be overridden,
39 * as can the "MSB first" default for each word in a transfer.
37 * @bits_per_word: Data transfers involve one or more words; word sizes 40 * @bits_per_word: Data transfers involve one or more words; word sizes
38 * like eight or 12 bits are common. In-memory wordsizes are 41 * like eight or 12 bits are common. In-memory wordsizes are
39 * powers of two bytes (e.g. 20 bit samples use 32 bits). 42 * powers of two bytes (e.g. 20 bit samples use 32 bits).
40 * This may be changed by the device's driver. 43 * This may be changed by the device's driver, or left at the
44 * default (0) indicating protocol words are eight bit bytes.
45 * The spi_transfer.bits_per_word can override this for each transfer.
41 * @irq: Negative, or the number passed to request_irq() to receive 46 * @irq: Negative, or the number passed to request_irq() to receive
42 * interrupts from this device. 47 * interrupts from this device.
43 * @controller_state: Controller's runtime state 48 * @controller_state: Controller's runtime state
44 * @controller_data: Board-specific definitions for controller, such as 49 * @controller_data: Board-specific definitions for controller, such as
45 * FIFO initialization parameters; from board_info.controller_data 50 * FIFO initialization parameters; from board_info.controller_data
46 * 51 *
47 * An spi_device is used to interchange data between an SPI slave 52 * An spi_device is used to interchange data between an SPI slave
48 * (usually a discrete chip) and CPU memory. 53 * (usually a discrete chip) and CPU memory.
@@ -65,6 +70,7 @@ struct spi_device {
65#define SPI_MODE_2 (SPI_CPOL|0) 70#define SPI_MODE_2 (SPI_CPOL|0)
66#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) 71#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
67#define SPI_CS_HIGH 0x04 /* chipselect active high? */ 72#define SPI_CS_HIGH 0x04 /* chipselect active high? */
73#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
68 u8 bits_per_word; 74 u8 bits_per_word;
69 int irq; 75 int irq;
70 void *controller_state; 76 void *controller_state;
@@ -73,7 +79,6 @@ struct spi_device {
73 79
74 // likely need more hooks for more protocol options affecting how 80 // likely need more hooks for more protocol options affecting how
75 // the controller talks to each chip, like: 81 // the controller talks to each chip, like:
76 // - bit order (default is wordwise msb-first)
77 // - memory packing (12 bit samples into low bits, others zeroed) 82 // - memory packing (12 bit samples into low bits, others zeroed)
78 // - priority 83 // - priority
79 // - drop chipselect after each word 84 // - drop chipselect after each word
@@ -143,13 +148,13 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
143 * struct spi_master - interface to SPI master controller 148 * struct spi_master - interface to SPI master controller
144 * @cdev: class interface to this driver 149 * @cdev: class interface to this driver
145 * @bus_num: board-specific (and often SOC-specific) identifier for a 150 * @bus_num: board-specific (and often SOC-specific) identifier for a
146 * given SPI controller. 151 * given SPI controller.
147 * @num_chipselect: chipselects are used to distinguish individual 152 * @num_chipselect: chipselects are used to distinguish individual
148 * SPI slaves, and are numbered from zero to num_chipselects. 153 * SPI slaves, and are numbered from zero to num_chipselects.
149 * each slave has a chipselect signal, but it's common that not 154 * each slave has a chipselect signal, but it's common that not
150 * every chipselect is connected to a slave. 155 * every chipselect is connected to a slave.
151 * @setup: updates the device mode and clocking records used by a 156 * @setup: updates the device mode and clocking records used by a
152 * device's SPI controller; protocol code may call this. 157 * device's SPI controller; protocol code may call this.
153 * @transfer: adds a message to the controller's transfer queue. 158 * @transfer: adds a message to the controller's transfer queue.
154 * @cleanup: frees controller-specific state 159 * @cleanup: frees controller-specific state
155 * 160 *
@@ -167,13 +172,13 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
167struct spi_master { 172struct spi_master {
168 struct class_device cdev; 173 struct class_device cdev;
169 174
170 /* other than zero (== assign one dynamically), bus_num is fully 175 /* other than negative (== assign one dynamically), bus_num is fully
171 * board-specific. usually that simplifies to being SOC-specific. 176 * board-specific. usually that simplifies to being SOC-specific.
172 * example: one SOC has three SPI controllers, numbered 1..3, 177 * example: one SOC has three SPI controllers, numbered 0..2,
173 * and one board's schematics might show it using SPI-2. software 178 * and one board's schematics might show it using SPI-2. software
174 * would normally use bus_num=2 for that controller. 179 * would normally use bus_num=2 for that controller.
175 */ 180 */
176 u16 bus_num; 181 s16 bus_num;
177 182
178 /* chipselects will be integral to many controllers; some others 183 /* chipselects will be integral to many controllers; some others
179 * might use board-specific GPIOs. 184 * might use board-specific GPIOs.
@@ -268,10 +273,14 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
268 * @tx_dma: DMA address of tx_buf, if spi_message.is_dma_mapped 273 * @tx_dma: DMA address of tx_buf, if spi_message.is_dma_mapped
269 * @rx_dma: DMA address of rx_buf, if spi_message.is_dma_mapped 274 * @rx_dma: DMA address of rx_buf, if spi_message.is_dma_mapped
270 * @len: size of rx and tx buffers (in bytes) 275 * @len: size of rx and tx buffers (in bytes)
276 * @speed_hz: Select a speed other then the device default for this
277 * transfer. If 0 the default (from spi_device) is used.
278 * @bits_per_word: select a bits_per_word other then the device default
279 * for this transfer. If 0 the default (from spi_device) is used.
271 * @cs_change: affects chipselect after this transfer completes 280 * @cs_change: affects chipselect after this transfer completes
272 * @delay_usecs: microseconds to delay after this transfer before 281 * @delay_usecs: microseconds to delay after this transfer before
273 * (optionally) changing the chipselect status, then starting 282 * (optionally) changing the chipselect status, then starting
274 * the next transfer or completing this spi_message. 283 * the next transfer or completing this spi_message.
275 * @transfer_list: transfers are sequenced through spi_message.transfers 284 * @transfer_list: transfers are sequenced through spi_message.transfers
276 * 285 *
277 * SPI transfers always write the same number of bytes as they read. 286 * SPI transfers always write the same number of bytes as they read.
@@ -322,7 +331,9 @@ struct spi_transfer {
322 dma_addr_t rx_dma; 331 dma_addr_t rx_dma;
323 332
324 unsigned cs_change:1; 333 unsigned cs_change:1;
334 u8 bits_per_word;
325 u16 delay_usecs; 335 u16 delay_usecs;
336 u32 speed_hz;
326 337
327 struct list_head transfer_list; 338 struct list_head transfer_list;
328}; 339};
@@ -356,7 +367,7 @@ struct spi_transfer {
356 * and its transfers, ignore them until its completion callback. 367 * and its transfers, ignore them until its completion callback.
357 */ 368 */
358struct spi_message { 369struct spi_message {
359 struct list_head transfers; 370 struct list_head transfers;
360 371
361 struct spi_device *spi; 372 struct spi_device *spi;
362 373
@@ -374,7 +385,7 @@ struct spi_message {
374 */ 385 */
375 386
376 /* completion is reported through a callback */ 387 /* completion is reported through a callback */
377 void (*complete)(void *context); 388 void (*complete)(void *context);
378 void *context; 389 void *context;
379 unsigned actual_length; 390 unsigned actual_length;
380 int status; 391 int status;