diff options
author | Sebastian Andrzej Siewior <bigeasy@linutronix.de> | 2010-11-24 04:17:14 -0500 |
---|---|---|
committer | Sebastian Andrzej Siewior <bigeasy@linutronix.de> | 2010-12-01 07:48:30 -0500 |
commit | d6ea3df0d470fb9260db93883f97764cf9f0e562 (patch) | |
tree | 277838ea93d6dc0c7d2a05be757dfa1b8bedb619 /include/linux/spi/pxa2xx_spi.h | |
parent | 8348c259dd6a6019a8fa01b0a3443409480f7b9d (diff) |
spi/pxa2xx: Add CE4100 support
Sodaville's SPI controller is very much the same as in PXA25x. The
difference:
- The RX/TX FIFO is only 4 words deep instead of 16
- No DMA support
- The SPI controller offers a CS functionality
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Diffstat (limited to 'include/linux/spi/pxa2xx_spi.h')
-rw-r--r-- | include/linux/spi/pxa2xx_spi.h | 105 |
1 files changed, 104 insertions, 1 deletions
diff --git a/include/linux/spi/pxa2xx_spi.h b/include/linux/spi/pxa2xx_spi.h index 471ed6889113..d3e1075f7b60 100644 --- a/include/linux/spi/pxa2xx_spi.h +++ b/include/linux/spi/pxa2xx_spi.h | |||
@@ -19,7 +19,6 @@ | |||
19 | #define __linux_pxa2xx_spi_h | 19 | #define __linux_pxa2xx_spi_h |
20 | 20 | ||
21 | #include <linux/pxa2xx_ssp.h> | 21 | #include <linux/pxa2xx_ssp.h> |
22 | #include <mach/dma.h> | ||
23 | 22 | ||
24 | #define PXA2XX_CS_ASSERT (0x01) | 23 | #define PXA2XX_CS_ASSERT (0x01) |
25 | #define PXA2XX_CS_DEASSERT (0x02) | 24 | #define PXA2XX_CS_DEASSERT (0x02) |
@@ -44,6 +43,110 @@ struct pxa2xx_spi_chip { | |||
44 | void (*cs_control)(u32 command); | 43 | void (*cs_control)(u32 command); |
45 | }; | 44 | }; |
46 | 45 | ||
46 | #ifdef CONFIG_ARCH_PXA | ||
47 | |||
48 | #include <linux/clk.h> | ||
49 | #include <mach/dma.h> | ||
50 | |||
47 | extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info); | 51 | extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info); |
48 | 52 | ||
53 | #else | ||
54 | /* | ||
55 | * This is the implemtation for CE4100 on x86. ARM defines them in mach/ or | ||
56 | * plat/ include path. | ||
57 | * The CE4100 does not provide DMA support. This bits are here to let the driver | ||
58 | * compile and will never be used. Maybe we get DMA support at a later point in | ||
59 | * time. | ||
60 | */ | ||
61 | |||
62 | #define DCSR(n) (n) | ||
63 | #define DSADR(n) (n) | ||
64 | #define DTADR(n) (n) | ||
65 | #define DCMD(n) (n) | ||
66 | #define DRCMR(n) (n) | ||
67 | |||
68 | #define DCSR_RUN (1 << 31) /* Run Bit */ | ||
69 | #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch */ | ||
70 | #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable */ | ||
71 | #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ | ||
72 | #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ | ||
73 | #define DCSR_ENDINTR (1 << 2) /* End Interrupt */ | ||
74 | #define DCSR_STARTINTR (1 << 1) /* Start Interrupt */ | ||
75 | #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt */ | ||
76 | |||
77 | #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable */ | ||
78 | #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ | ||
79 | #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ | ||
80 | #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ | ||
81 | #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ | ||
82 | #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ | ||
83 | #define DCSR_EORINTR (1 << 9) /* The end of Receive */ | ||
84 | |||
85 | #define DRCMR_MAPVLD (1 << 7) /* Map Valid */ | ||
86 | #define DRCMR_CHLNUM 0x1f /* mask for Channel Number */ | ||
87 | |||
88 | #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor */ | ||
89 | #define DDADR_STOP (1 << 0) /* Stop */ | ||
90 | |||
91 | #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ | ||
92 | #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ | ||
93 | #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ | ||
94 | #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ | ||
95 | #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ | ||
96 | #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ | ||
97 | #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ | ||
98 | #define DCMD_BURST8 (1 << 16) /* 8 byte burst */ | ||
99 | #define DCMD_BURST16 (2 << 16) /* 16 byte burst */ | ||
100 | #define DCMD_BURST32 (3 << 16) /* 32 byte burst */ | ||
101 | #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ | ||
102 | #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ | ||
103 | #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ | ||
104 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | ||
105 | |||
106 | /* | ||
107 | * Descriptor structure for PXA's DMA engine | ||
108 | * Note: this structure must always be aligned to a 16-byte boundary. | ||
109 | */ | ||
110 | |||
111 | typedef enum { | ||
112 | DMA_PRIO_HIGH = 0, | ||
113 | DMA_PRIO_MEDIUM = 1, | ||
114 | DMA_PRIO_LOW = 2 | ||
115 | } pxa_dma_prio; | ||
116 | |||
117 | /* | ||
118 | * DMA registration | ||
119 | */ | ||
120 | |||
121 | static inline int pxa_request_dma(char *name, | ||
122 | pxa_dma_prio prio, | ||
123 | void (*irq_handler)(int, void *), | ||
124 | void *data) | ||
125 | { | ||
126 | return -ENODEV; | ||
127 | } | ||
128 | |||
129 | static inline void pxa_free_dma(int dma_ch) | ||
130 | { | ||
131 | } | ||
132 | |||
133 | /* | ||
134 | * The CE4100 does not have the clk framework implemented and SPI clock can | ||
135 | * not be switched on/off or the divider changed. | ||
136 | */ | ||
137 | static inline void clk_disable(struct clk *clk) | ||
138 | { | ||
139 | } | ||
140 | |||
141 | static inline int clk_enable(struct clk *clk) | ||
142 | { | ||
143 | return 0; | ||
144 | } | ||
145 | |||
146 | static inline unsigned long clk_get_rate(struct clk *clk) | ||
147 | { | ||
148 | return 3686400; | ||
149 | } | ||
150 | |||
151 | #endif | ||
49 | #endif | 152 | #endif |