Merge branch 'master' of /home/davem/src/GIT/linux-2.6/

1 files changed, 75 insertions, 5 deletions

diff --git a/include/linux/rio_regs.h b/include/linux/rio_regs.h
index 326540f9b54e..aedee0489fb4 100644
--- a/include/linux/rio_regs.h
+++ b/include/linux/rio_regs.h
@@ -39,6 +39,8 @@
 #define  RIO_PEF_INB_MBOX2              0x00200000      /* [II] Mailbox 2 */
 #define  RIO_PEF_INB_MBOX3              0x00100000      /* [II] Mailbox 3 */
 #define  RIO_PEF_INB_DOORBELL           0x00080000      /* [II] Doorbells */
+#define  RIO_PEF_EXT_RT                 0x00000200      /* [III, 1.3] Extended route table support */
+#define  RIO_PEF_STD_RT                 0x00000100      /* [III, 1.3] Standard route table support */
 #define  RIO_PEF_CTLS                   0x00000010      /* [III] CTLS */
 #define  RIO_PEF_EXT_FEATURES           0x00000008      /* [I] EFT_PTR valid */
 #define  RIO_PEF_ADDR_66                0x00000004      /* [I] 66 bits */
@@ -91,7 +93,10 @@
 #define  RIO_OPS_ATOMIC_CLR             0x00000010      /* [I] Atomic clr op */
 #define  RIO_OPS_PORT_WRITE             0x00000004      /* [I] Port-write op */
 
-                                        /* 0x20-0x3c *//* Reserved */
+                                        /* 0x20-0x30 *//* Reserved */
+
+#define RIO_SWITCH_RT_LIMIT     0x34    /* [III, 1.3] Switch Route Table Destination ID Limit CAR */
+#define  RIO_RT_MAX_DESTID              0x0000ffff
 
 #define RIO_MBOX_CSR            0x40    /* [II] Mailbox CSR */
 #define  RIO_MBOX0_AVAIL                0x80000000      /* [II] Mbox 0 avail */
@@ -153,7 +158,11 @@
 #define RIO_HOST_DID_LOCK_CSR   0x68    /* [III] Host Base Device ID Lock CSR */
 #define RIO_COMPONENT_TAG_CSR   0x6c    /* [III] Component Tag CSR */
 
-                                        /* 0x70-0xf8 *//* Reserved */
+#define RIO_STD_RTE_CONF_DESTID_SEL_CSR 0x70
+#define RIO_STD_RTE_CONF_PORT_SEL_CSR   0x74
+#define RIO_STD_RTE_DEFAULT_PORT        0x78
+
+                                        /* 0x7c-0xf8 *//* Reserved */
                                         /* 0x100-0xfff8 *//* [I] Extended Features Space */
                                         /* 0x10000-0xfffff8 *//* [I] Implementation-defined Space */
 
@@ -183,9 +192,14 @@
 #define RIO_EFB_PAR_EP_ID       0x0001  /* [IV] LP/LVDS EP Devices */
 #define RIO_EFB_PAR_EP_REC_ID   0x0002  /* [IV] LP/LVDS EP Recovery Devices */
 #define RIO_EFB_PAR_EP_FREE_ID  0x0003  /* [IV] LP/LVDS EP Free Devices */
+#define RIO_EFB_SER_EP_ID_V13P  0x0001  /* [VI] LP/Serial EP Devices, RapidIO Spec ver 1.3 and above */
+#define RIO_EFB_SER_EP_REC_ID_V13P      0x0002  /* [VI] LP/Serial EP Recovery Devices, RapidIO Spec ver 1.3 and above */
+#define RIO_EFB_SER_EP_FREE_ID_V13P     0x0003  /* [VI] LP/Serial EP Free Devices, RapidIO Spec ver 1.3 and above */
 #define RIO_EFB_SER_EP_ID       0x0004  /* [VI] LP/Serial EP Devices */
 #define RIO_EFB_SER_EP_REC_ID   0x0005  /* [VI] LP/Serial EP Recovery Devices */
 #define RIO_EFB_SER_EP_FREE_ID  0x0006  /* [VI] LP/Serial EP Free Devices */
+#define RIO_EFB_SER_EP_FREC_ID  0x0009  /* [VI] LP/Serial EP Free Recovery Devices */
+#define RIO_EFB_ERR_MGMNT       0x0007  /* [VIII] Error Management Extensions */
 
 /*
  * Physical 8/16 LP-LVDS
@@ -201,15 +215,71 @@
 #define RIO_PORT_MNT_HEADER             0x0000
 #define RIO_PORT_REQ_CTL_CSR            0x0020
 #define RIO_PORT_RSP_CTL_CSR            0x0024  /* 0x0001/0x0002 */
+#define RIO_PORT_LINKTO_CTL_CSR         0x0020  /* Serial */
+#define RIO_PORT_RSPTO_CTL_CSR          0x0024  /* Serial */
 #define RIO_PORT_GEN_CTL_CSR            0x003c
 #define  RIO_PORT_GEN_HOST              0x80000000
 #define  RIO_PORT_GEN_MASTER            0x40000000
 #define  RIO_PORT_GEN_DISCOVERED        0x20000000
 #define RIO_PORT_N_MNT_REQ_CSR(x)       (0x0040 + x*0x20)       /* 0x0002 */
 #define RIO_PORT_N_MNT_RSP_CSR(x)       (0x0044 + x*0x20)       /* 0x0002 */
+#define  RIO_PORT_N_MNT_RSP_RVAL        0x80000000 /* Response Valid */
+#define  RIO_PORT_N_MNT_RSP_ASTAT       0x000003e0 /* ackID Status */
+#define  RIO_PORT_N_MNT_RSP_LSTAT       0x0000001f /* Link Status */
 #define RIO_PORT_N_ACK_STS_CSR(x)       (0x0048 + x*0x20)       /* 0x0002 */
-#define RIO_PORT_N_ERR_STS_CSR(x)       (0x58 + x*0x20)
-#define PORT_N_ERR_STS_PORT_OK  0x00000002
-#define RIO_PORT_N_CTL_CSR(x)           (0x5c + x*0x20)
+#define  RIO_PORT_N_ACK_CLEAR           0x80000000
+#define  RIO_PORT_N_ACK_INBOUND         0x1f000000
+#define  RIO_PORT_N_ACK_OUTSTAND        0x00001f00
+#define  RIO_PORT_N_ACK_OUTBOUND        0x0000001f
+#define RIO_PORT_N_ERR_STS_CSR(x)       (0x0058 + x*0x20)
+#define  RIO_PORT_N_ERR_STS_PW_OUT_ES   0x00010000 /* Output Error-stopped */
+#define  RIO_PORT_N_ERR_STS_PW_INP_ES   0x00000100 /* Input Error-stopped */
+#define  RIO_PORT_N_ERR_STS_PW_PEND     0x00000010 /* Port-Write Pending */
+#define  RIO_PORT_N_ERR_STS_PORT_ERR    0x00000004
+#define  RIO_PORT_N_ERR_STS_PORT_OK     0x00000002
+#define  RIO_PORT_N_ERR_STS_PORT_UNINIT 0x00000001
+#define  RIO_PORT_N_ERR_STS_CLR_MASK    0x07120204
+#define RIO_PORT_N_CTL_CSR(x)           (0x005c + x*0x20)
+#define  RIO_PORT_N_CTL_PWIDTH          0xc0000000
+#define  RIO_PORT_N_CTL_PWIDTH_1        0x00000000
+#define  RIO_PORT_N_CTL_PWIDTH_4        0x40000000
+#define  RIO_PORT_N_CTL_P_TYP_SER       0x00000001
+#define  RIO_PORT_N_CTL_LOCKOUT         0x00000002
+#define  RIO_PORT_N_CTL_EN_RX_SER       0x00200000
+#define  RIO_PORT_N_CTL_EN_TX_SER       0x00400000
+#define  RIO_PORT_N_CTL_EN_RX_PAR       0x08000000
+#define  RIO_PORT_N_CTL_EN_TX_PAR       0x40000000
+
+/*
+ * Error Management Extensions (RapidIO 1.3+, Part 8)
+ *
+ * Extended Features Block ID=0x0007
+ */
+
+/* General EM Registers (Common for all Ports) */
+
+#define RIO_EM_EFB_HEADER       0x000   /* Error Management Extensions Block Header */
+#define RIO_EM_LTL_ERR_DETECT   0x008   /* Logical/Transport Layer Error Detect CSR */
+#define RIO_EM_LTL_ERR_EN       0x00c   /* Logical/Transport Layer Error Enable CSR */
+#define RIO_EM_LTL_HIADDR_CAP   0x010   /* Logical/Transport Layer High Address Capture CSR */
+#define RIO_EM_LTL_ADDR_CAP     0x014   /* Logical/Transport Layer Address Capture CSR */
+#define RIO_EM_LTL_DEVID_CAP    0x018   /* Logical/Transport Layer Device ID Capture CSR */
+#define RIO_EM_LTL_CTRL_CAP     0x01c   /* Logical/Transport Layer Control Capture CSR */
+#define RIO_EM_PW_TGT_DEVID     0x028   /* Port-write Target deviceID CSR */
+#define RIO_EM_PKT_TTL          0x02c   /* Packet Time-to-live CSR */
+
+/* Per-Port EM Registers */
+
+#define RIO_EM_PN_ERR_DETECT(x) (0x040 + x*0x40) /* Port N Error Detect CSR */
+#define  REM_PED_IMPL_SPEC              0x80000000
+#define  REM_PED_LINK_TO                0x00000001
+#define RIO_EM_PN_ERRRATE_EN(x) (0x044 + x*0x40) /* Port N Error Rate Enable CSR */
+#define RIO_EM_PN_ATTRIB_CAP(x) (0x048 + x*0x40) /* Port N Attributes Capture CSR */
+#define RIO_EM_PN_PKT_CAP_0(x)  (0x04c + x*0x40) /* Port N Packet/Control Symbol Capture 0 CSR */
+#define RIO_EM_PN_PKT_CAP_1(x)  (0x050 + x*0x40) /* Port N Packet Capture 1 CSR */
+#define RIO_EM_PN_PKT_CAP_2(x)  (0x054 + x*0x40) /* Port N Packet Capture 2 CSR */
+#define RIO_EM_PN_PKT_CAP_3(x)  (0x058 + x*0x40) /* Port N Packet Capture 3 CSR */
+#define RIO_EM_PN_ERRRATE(x)    (0x068 + x*0x40) /* Port N Error Rate CSR */
+#define RIO_EM_PN_ERRRATE_TR(x) (0x06c + x*0x40) /* Port N Error Rate Threshold CSR */
 
 #endif                          /* LINUX_RIO_REGS_H */