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authorMark Brown <broonie@opensource.wolfsonmicro.com>2011-10-28 17:50:49 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2011-11-08 06:29:48 -0500
commitf8beab2bb611d735767871e0e1a12dc6a0def7b1 (patch)
treea30103e40ae9d4473025edad6a2b3a28e3133fb5 /include/linux/regmap.h
parent1ea6b8f48918282bdca0b32a34095504ee65bab5 (diff)
regmap: Add a reusable irq_chip for regmap based interrupt controllers
There seem to be lots of regmap-using devices with very similar interrupt controllers with a small bank of interrupt registers and mask registers with an interrupt per bit. This won't cover everything but it's a good start. Each chip supplies a base for the status registers, a base for the mask registers, an optional base for writing acknowledgements (which may be the same as the status registers) and an array of bits within each of these register banks which indicate the interrupt. There is an assumption that the bit for each interrupt will be the same in each of the register bank. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'include/linux/regmap.h')
-rw-r--r--include/linux/regmap.h47
1 files changed, 47 insertions, 0 deletions
diff --git a/include/linux/regmap.h b/include/linux/regmap.h
index 690276a642cf..bd54cecdfdf8 100644
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -144,4 +144,51 @@ int regcache_sync(struct regmap *map);
144void regcache_cache_only(struct regmap *map, bool enable); 144void regcache_cache_only(struct regmap *map, bool enable);
145void regcache_cache_bypass(struct regmap *map, bool enable); 145void regcache_cache_bypass(struct regmap *map, bool enable);
146 146
147/**
148 * Description of an IRQ for the generic regmap irq_chip.
149 *
150 * @reg_offset: Offset of the status/mask register within the bank
151 * @mask: Mask used to flag/control the register.
152 */
153struct regmap_irq {
154 unsigned int reg_offset;
155 unsigned int mask;
156};
157
158/**
159 * Description of a generic regmap irq_chip. This is not intended to
160 * handle every possible interrupt controller, but it should handle a
161 * substantial proportion of those that are found in the wild.
162 *
163 * @name: Descriptive name for IRQ controller.
164 *
165 * @status_base: Base status register address.
166 * @mask_base: Base mask register address.
167 * @ack_base: Base ack address. If zero then the chip is clear on read.
168 *
169 * @num_regs: Number of registers in each control bank.
170 * @irqs: Descriptors for individual IRQs. Interrupt numbers are
171 * assigned based on the index in the array of the interrupt.
172 * @num_irqs: Number of descriptors.
173 */
174struct regmap_irq_chip {
175 const char *name;
176
177 unsigned int status_base;
178 unsigned int mask_base;
179 unsigned int ack_base;
180
181 int num_regs;
182
183 const struct regmap_irq *irqs;
184 int num_irqs;
185};
186
187struct regmap_irq_chip_data;
188
189int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
190 int irq_base, struct regmap_irq_chip *chip,
191 struct regmap_irq_chip_data **data);
192void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *data);
193
147#endif 194#endif