spi: spi-pxa2xx: SPI support for Intel Quark X1000

There are two SPI controllers exported by PCI subsystem for Intel Quark X1000.
The SPI memory mapped I/O registers supported by Quark are different from
the current implementation, and Quark only supports the registers of 'SSCR0',
'SSCR1', 'SSSR', 'SSDR', and 'DDS_RATE'. This patch is to enable the SPI for
Intel Quark X1000.

This piece of work is derived from Dan O'Donovan's initial work for Intel Quark
X1000 SPI enabling.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Weike Chen <alvin.chen@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

1 files changed, 20 insertions, 0 deletions

diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h
index f2b405116166..77aed9ea1d26 100644
--- a/include/linux/pxa2xx_ssp.h
+++ b/include/linux/pxa2xx_ssp.h
@@ -108,6 +108,25 @@
 #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
 #endif
 
+/* QUARK_X1000 SSCR0 bit definition */
+#define QUARK_X1000_SSCR0_DSS   (0x1F)          /* Data Size Select (mask) */
+#define QUARK_X1000_SSCR0_DataSize(x)  ((x) - 1)        /* Data Size Select [4..32] */
+#define QUARK_X1000_SSCR0_FRF   (0x3 << 5)      /* FRame Format (mask) */
+#define QUARK_X1000_SSCR0_Motorola      (0x0 << 5)      /* Motorola's Serial Peripheral Interface (SPI) */
+
+#define RX_THRESH_QUARK_X1000_DFLT      1
+#define TX_THRESH_QUARK_X1000_DFLT      16
+
+#define QUARK_X1000_SSSR_TFL_MASK       (0x1F << 8)     /* Transmit FIFO Level mask */
+#define QUARK_X1000_SSSR_RFL_MASK       (0x1F << 13)    /* Receive FIFO Level mask */
+
+#define QUARK_X1000_SSCR1_TFT   (0x1F << 6)     /* Transmit FIFO Threshold (mask) */
+#define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6)   /* level [1..32] */
+#define QUARK_X1000_SSCR1_RFT   (0x1F << 11)    /* Receive FIFO Threshold (mask) */
+#define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11)  /* level [1..32] */
+#define QUARK_X1000_SSCR1_STRF       (1 << 17)          /* Select FIFO or EFWR */
+#define QUARK_X1000_SSCR1_EFWR  (1 << 16)               /* Enable FIFO Write/Read */
+
 /* extra bits in PXA255, PXA26x and PXA27x SSP ports */
 #define SSCR0_TISSP             (1 << 4)        /* TI Sync Serial Protocol */
 #define SSCR0_PSP               (3 << 4)        /* PSP - Programmable Serial Protocol */
@@ -175,6 +194,7 @@ enum pxa_ssp_type {
         PXA910_SSP,
         CE4100_SSP,
         LPSS_SSP,
+        QUARK_X1000_SSP,
 };
 
 struct ssp_device {