perf_counter: Implement generalized cache event types

Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.

This is a 3-dimensional space:

       { L1-D, L1-I, L2, ITLB, DTLB, BPU } x
       { load, store, prefetch } x
       { accesses, misses }

User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)

Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.

Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.

( x86 is supported for now, with the Nehalem event table filled in,
  and with Core2 and Atom having placeholder tables. )

Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

1 files changed, 34 insertions, 0 deletions

diff --git a/include/linux/perf_counter.h b/include/linux/perf_counter.h
index f794c69b34c9..3586df840f69 100644
--- a/include/linux/perf_counter.h
+++ b/include/linux/perf_counter.h
@@ -28,6 +28,7 @@ enum perf_event_types {
         PERF_TYPE_HARDWARE              = 0,
         PERF_TYPE_SOFTWARE              = 1,
         PERF_TYPE_TRACEPOINT            = 2,
+        PERF_TYPE_HW_CACHE              = 3,
 
         /*
          * available TYPE space, raw is the max value.
@@ -56,6 +57,39 @@ enum attr_ids {
 };
 
 /*
+ * Generalized hardware cache counters:
+ *
+ *       { L1-D, L1-I, L2, LLC, ITLB, DTLB, BPU } x
+ *       { read, write, prefetch } x
+ *       { accesses, misses }
+ */
+enum hw_cache_id {
+        PERF_COUNT_HW_CACHE_L1D,
+        PERF_COUNT_HW_CACHE_L1I,
+        PERF_COUNT_HW_CACHE_L2,
+        PERF_COUNT_HW_CACHE_DTLB,
+        PERF_COUNT_HW_CACHE_ITLB,
+        PERF_COUNT_HW_CACHE_BPU,
+
+        PERF_COUNT_HW_CACHE_MAX,
+};
+
+enum hw_cache_op_id {
+        PERF_COUNT_HW_CACHE_OP_READ,
+        PERF_COUNT_HW_CACHE_OP_WRITE,
+        PERF_COUNT_HW_CACHE_OP_PREFETCH,
+
+        PERF_COUNT_HW_CACHE_OP_MAX,
+};
+
+enum hw_cache_op_result_id {
+        PERF_COUNT_HW_CACHE_RESULT_ACCESS,
+        PERF_COUNT_HW_CACHE_RESULT_MISS,
+
+        PERF_COUNT_HW_CACHE_RESULT_MAX,
+};
+
+/*
  * Special "software" counters provided by the kernel, even if the hardware
  * does not support performance counters. These counters measure various
  * physical and sw events of the kernel (and allow the profiling of them as