Merge commit 'v2.6.28-rc2' into x86/pci-ioapic-boot-irq-quirks

1 files changed, 17 insertions, 0 deletions

diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 19958b929905..e5effd47ed74 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -374,8 +374,10 @@
 #define  PCI_EXP_DEVCAP_ATN_BUT 0x1000  /* Attention Button Present */
 #define  PCI_EXP_DEVCAP_ATN_IND 0x2000  /* Attention Indicator Present */
 #define  PCI_EXP_DEVCAP_PWR_IND 0x4000  /* Power Indicator Present */
+#define  PCI_EXP_DEVCAP_RBER    0x8000  /* Role-Based Error Reporting */
 #define  PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
 #define  PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
+#define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
 #define PCI_EXP_DEVCTL          8       /* Device Control */
 #define  PCI_EXP_DEVCTL_CERE    0x0001  /* Correctable Error Reporting En. */
 #define  PCI_EXP_DEVCTL_NFERE   0x0002  /* Non-Fatal Error Reporting Enable */
@@ -388,6 +390,7 @@
 #define  PCI_EXP_DEVCTL_AUX_PME 0x0400  /* Auxiliary Power PM Enable */
 #define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
 #define  PCI_EXP_DEVCTL_READRQ  0x7000  /* Max_Read_Request_Size */
+#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
 #define PCI_EXP_DEVSTA          10      /* Device Status */
 #define  PCI_EXP_DEVSTA_CED     0x01    /* Correctable Error Detected */
 #define  PCI_EXP_DEVSTA_NFED    0x02    /* Non-Fatal Error Detected */
@@ -418,6 +421,10 @@
 #define  PCI_EXP_RTCTL_CRSSVE   0x10    /* CRS Software Visibility Enable */
 #define PCI_EXP_RTCAP           30      /* Root Capabilities */
 #define PCI_EXP_RTSTA           32      /* Root Status */
+#define PCI_EXP_DEVCAP2         36      /* Device Capabilities 2 */
+#define  PCI_EXP_DEVCAP2_ARI    0x20    /* Alternative Routing-ID */
+#define PCI_EXP_DEVCTL2         40      /* Device Control 2 */
+#define  PCI_EXP_DEVCTL2_ARI    0x20    /* Alternative Routing-ID */
 
 /* Extended Capabilities (PCI-X 2.0 and Express) */
 #define PCI_EXT_CAP_ID(header)          (header & 0x0000ffff)
@@ -428,6 +435,7 @@
 #define PCI_EXT_CAP_ID_VC       2
 #define PCI_EXT_CAP_ID_DSN      3
 #define PCI_EXT_CAP_ID_PWR      4
+#define PCI_EXT_CAP_ID_ARI      14
 
 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS    4       /* Uncorrectable Error Status */
@@ -535,5 +543,14 @@
 #define HT_CAPTYPE_GEN3         0xD0    /* Generation 3 hypertransport configuration */
 #define HT_CAPTYPE_PM           0xE0    /* Hypertransport powermanagement configuration */
 
+/* Alternative Routing-ID Interpretation */
+#define PCI_ARI_CAP             0x04    /* ARI Capability Register */
+#define  PCI_ARI_CAP_MFVC       0x0001  /* MFVC Function Groups Capability */
+#define  PCI_ARI_CAP_ACS        0x0002  /* ACS Function Groups Capability */
+#define  PCI_ARI_CAP_NFN(x)     (((x) >> 8) & 0xff) /* Next Function Number */
+#define PCI_ARI_CTRL            0x06    /* ARI Control Register */
+#define  PCI_ARI_CTRL_MFVC      0x0001  /* MFVC Function Groups Enable */
+#define  PCI_ARI_CTRL_ACS       0x0002  /* ACS Function Groups Enable */
+#define  PCI_ARI_CTRL_FG(x)     (((x) >> 4) & 7) /* Function Group */
 
 #endif /* LINUX_PCI_REGS_H */