Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6

* master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6: (37 commits)
  PCI: merge almost all of pci_32.h and pci_64.h together
  PCI: X86: Introduce and enable PCI domain support
  PCI: Add 'nodomains' boot option, and pci_domains_supported global
  PCI: modify PCI bridge control ISA flag for clarity
  PCI: use _CRS for PCI resource allocation
  PCI: avoid P2P prefetch window for expansion ROMs
  PCI: skip ISA ioresource alignment on some systems
  PCI: remove transparent bridge sizing
  pci: write file size to inode on proc bus file write
  pci: use size stored in proc_dir_entry for proc bus files
  pci: implement "pci=noaer"
  PCI: fix IDE legacy mode resources
  MSI: Use correct data offset for 32-bit MSI in read_msi_msg()
  PCI: Fix incorrect argument order to list_add_tail() in PCI dynamic ID code
  PCI: i386: Compaq EVO N800c needs PCI bus renumbering
  PCI: Remove no longer correct documentation regarding MSI vector assignment
  PCI: re-enable onboard sound on "MSI K8T Neo2-FIR"
  PCI: quirk_vt82c586_acpi: Omit reading PCI revision ID
  PCI: quirk amd_8131_mmrbc: Omit reading pci revision ID
  cpqphp: Use PCI_CLASS_REVISION instead of PCI_REVISION_ID for read
  ...

1 files changed, 6 insertions, 2 deletions

diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 423d592c55d5..c1914a8b94a9 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -147,7 +147,7 @@
 #define PCI_BRIDGE_CONTROL      0x3e
 #define  PCI_BRIDGE_CTL_PARITY  0x01    /* Enable parity detection on secondary interface */
 #define  PCI_BRIDGE_CTL_SERR    0x02    /* The same for SERR forwarding */
-#define  PCI_BRIDGE_CTL_NO_ISA  0x04    /* Disable bridging of ISA ports */
+#define  PCI_BRIDGE_CTL_ISA     0x04    /* Enable ISA mode */
 #define  PCI_BRIDGE_CTL_VGA     0x08    /* Forward VGA addresses */
 #define  PCI_BRIDGE_CTL_MASTER_ABORT    0x20  /* Report master aborts */
 #define  PCI_BRIDGE_CTL_BUS_RESET       0x40    /* Secondary bus reset */
@@ -202,8 +202,12 @@
 #define  PCI_CAP_ID_CHSWP       0x06    /* CompactPCI HotSwap */
 #define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
 #define  PCI_CAP_ID_HT          0x08    /* HyperTransport */
-#define  PCI_CAP_ID_VNDR        0x09    /* Vendor specific capability */
+#define  PCI_CAP_ID_VNDR        0x09    /* Vendor specific */
+#define  PCI_CAP_ID_DBG         0x0A    /* Debug port */
+#define  PCI_CAP_ID_CCRC        0x0B    /* CompactPCI Central Resource Control */
 #define  PCI_CAP_ID_SHPC        0x0C    /* PCI Standard Hot-Plug Controller */
+#define  PCI_CAP_ID_SSVID       0x0D    /* Bridge subsystem vendor/device ID */
+#define  PCI_CAP_ID_AGP3        0x0E    /* AGP Target PCI-PCI bridge */
 #define  PCI_CAP_ID_EXP         0x10    /* PCI Express */
 #define  PCI_CAP_ID_MSIX        0x11    /* MSI-X */
 #define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */