diff options
author | Greg Kroah-Hartman <gregkh@suse.de> | 2008-02-02 14:32:01 -0500 |
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committer | Greg Kroah-Hartman <gregkh@suse.de> | 2008-02-02 14:32:01 -0500 |
commit | cc3a1378b4dd45d3e78dd4aeb10641b06a87d614 (patch) | |
tree | 4eb9dc8f7cefc44926f886c467992e769b873c69 /include/linux/pci_regs.h | |
parent | ae9458d6a0956aa21cb49e1251e35a8d4dacbe6e (diff) |
Revert "PCI: PCIE ASPM support"
This reverts commit 6c723d5bd89f03fc3ef627d50f89ade054d2ee3b.
It caused build errors on non-x86 platforms, config file confusion, and
even some boot errors on some x86-64 boxes. All around, not quite ready
for prime-time :(
Cc: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'include/linux/pci_regs.h')
-rw-r--r-- | include/linux/pci_regs.h | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index c0c1223c9194..c1914a8b94a9 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h | |||
@@ -395,17 +395,9 @@ | |||
395 | #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ | 395 | #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ |
396 | #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ | 396 | #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ |
397 | #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ | 397 | #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ |
398 | #define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */ | ||
399 | #define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */ | ||
400 | #define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */ | ||
401 | #define PCI_EXP_LNKCAP_CLKPM 0x40000 /* L1 Clock Power Management */ | ||
402 | #define PCI_EXP_LNKCTL 16 /* Link Control */ | 398 | #define PCI_EXP_LNKCTL 16 /* Link Control */ |
403 | #define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ | ||
404 | #define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ | ||
405 | #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */ | 399 | #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */ |
406 | #define PCI_EXP_LNKSTA 18 /* Link Status */ | 400 | #define PCI_EXP_LNKSTA 18 /* Link Status */ |
407 | #define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ | ||
408 | #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ | ||
409 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ | 401 | #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ |
410 | #define PCI_EXP_SLTCTL 24 /* Slot Control */ | 402 | #define PCI_EXP_SLTCTL 24 /* Slot Control */ |
411 | #define PCI_EXP_SLTSTA 26 /* Slot Status */ | 403 | #define PCI_EXP_SLTSTA 26 /* Slot Status */ |