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authorAlex Williamson <alex.williamson@redhat.com>2011-11-11 12:07:36 -0500
committerJesse Barnes <jbarnes@virtuousgeek.org>2011-12-05 13:22:15 -0500
commit91f57d5e1be3db1e079c8696f1eab214f1c7922d (patch)
tree58d4a2a2fa41185c0fe64f8ac7395215fd27d2a1 /include/linux/pci_regs.h
parent60fe823837d10673500ff685c01eb2f896fe5849 (diff)
PCI: More PRI/PASID cleanup
More consistency cleanups. Drop the _OFF, separate and indent CTRL/CAP/STATUS bit definitions. This helped find the previous mis-use of bit 0 in the PASID capability register. Reviewed-by: Joerg Roedel <joerg.roedel@amd.com> Tested-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'include/linux/pci_regs.h')
-rw-r--r--include/linux/pci_regs.h30
1 files changed, 16 insertions, 14 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 090d3a9f5b26..28fe380cb19d 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -666,22 +666,24 @@
666#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */ 666#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */
667 667
668/* Page Request Interface */ 668/* Page Request Interface */
669#define PCI_PRI_CONTROL_OFF 0x04 /* Offset of control register */ 669#define PCI_PRI_CTRL 0x04 /* PRI control register */
670#define PCI_PRI_STATUS_OFF 0x06 /* Offset of status register */ 670#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */
671#define PCI_PRI_ENABLE 0x0001 /* Enable mask */ 671#define PCI_PRI_CTRL_RESET 0x02 /* Reset */
672#define PCI_PRI_RESET 0x0002 /* Reset bit mask */ 672#define PCI_PRI_STATUS 0x06 /* PRI status register */
673#define PCI_PRI_STATUS_RF 0x0001 /* Request Failure */ 673#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */
674#define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */ 674#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */
675#define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */ 675#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */
676#define PCI_PRI_MAX_REQ_OFF 0x08 /* Cap offset for max reqs supported */ 676#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
677#define PCI_PRI_ALLOC_REQ_OFF 0x0c /* Cap offset for max reqs allowed */ 677#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
678 678
679/* PASID capability */ 679/* PASID capability */
680#define PCI_PASID_CAP_OFF 0x04 /* PASID feature register */ 680#define PCI_PASID_CAP 0x04 /* PASID feature register */
681#define PCI_PASID_CONTROL_OFF 0x06 /* PASID control register */ 681#define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */
682#define PCI_PASID_ENABLE 0x01 /* Enable/Supported bit */ 682#define PCI_PASID_CAP_PRIV 0x04 /* Priviledge Mode Supported */
683#define PCI_PASID_EXEC 0x02 /* Exec permissions Enable/Supported */ 683#define PCI_PASID_CTRL 0x06 /* PASID control register */
684#define PCI_PASID_PRIV 0x04 /* Priviledge Mode Enable/Support */ 684#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */
685#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */
686#define PCI_PASID_CTRL_PRIV 0x04 /* Priviledge Mode Enable */
685 687
686/* Single Root I/O Virtualization */ 688/* Single Root I/O Virtualization */
687#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 689#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */