diff options
| author | Lucas De Marchi <lucas.demarchi@profusion.mobi> | 2011-03-30 21:57:33 -0400 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@profusion.mobi> | 2011-03-31 10:26:23 -0400 |
| commit | 25985edcedea6396277003854657b5f3cb31a628 (patch) | |
| tree | f026e810210a2ee7290caeb737c23cb6472b7c38 /include/linux/pci_regs.h | |
| parent | 6aba74f2791287ec407e0f92487a725a25908067 (diff) | |
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'include/linux/pci_regs.h')
| -rw-r--r-- | include/linux/pci_regs.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index 5b7e6b1ba54f..be01380f798a 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h | |||
| @@ -223,7 +223,7 @@ | |||
| 223 | #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ | 223 | #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ |
| 224 | #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ | 224 | #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ |
| 225 | #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ | 225 | #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ |
| 226 | #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */ | 226 | #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxiliary power support mask */ |
| 227 | #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ | 227 | #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ |
| 228 | #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ | 228 | #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ |
| 229 | #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ | 229 | #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ |
| @@ -435,7 +435,7 @@ | |||
| 435 | #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ | 435 | #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ |
| 436 | #define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ | 436 | #define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ |
| 437 | #define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* L1 Clock Power Management */ | 437 | #define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* L1 Clock Power Management */ |
| 438 | #define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Suprise Down Error Reporting Capable */ | 438 | #define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Surprise Down Error Reporting Capable */ |
| 439 | #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ | 439 | #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ |
| 440 | #define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */ | 440 | #define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */ |
| 441 | #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ | 441 | #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ |