diff options
author | Bjorn Helgaas <bhelgaas@google.com> | 2012-08-23 20:31:58 -0400 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2012-08-23 20:31:58 -0400 |
commit | e1c171b86baaccab983ded5dfa1663c0981d2520 (patch) | |
tree | 648ad71d7bd2838678f66d055fcaae654b5e4ddc /include/linux/pci.h | |
parent | 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee (diff) | |
parent | 479e0d485eaab452cf248cd1a9520015023b35b2 (diff) |
Merge branch 'pci/jiang-pcie-cap' into next
* pci/jiang-pcie-cap: (40 commits)
rtl8192e: Use PCI Express Capability accessors
et131x: Use PCI Express Capability accessors
rapdio/tsi721: Use PCI Express Capability accessors
drm/radeon: Use PCI Express Capability accessors
[SCSI] qla4xxx: Use PCI Express Capability accessors
[SCSI] qla4xxx: Use PCI Express Capability accessors
IB/qib: Use PCI Express Capability accessors
IB/mthca: Use PCI Express Capability accessors
rtlwifi: Use PCI Express Capability accessors
iwlwifi: Use PCI Express Capability accessors
iwlegacy: Use PCI Express Capability accessors
ath9k: Use PCI Express Capability accessors
atl1c: Use PCI Express Capability accessors
cxgb4: Use PCI Express Capability accessors
cxgb3: Use PCI Express Capability accessors
myri10ge: Use PCI Express Capability accessors
niu: Use PCI Express Capability accessors
mlx4: Use PCI Express Capability accessors
vxge: Use PCI Express Capability accessors
igb: Use PCI Express Capability accessors
...
Diffstat (limited to 'include/linux/pci.h')
-rw-r--r-- | include/linux/pci.h | 44 |
1 files changed, 43 insertions, 1 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h index 5faa8310eec9..b8667e0548e0 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h | |||
@@ -254,10 +254,10 @@ struct pci_dev { | |||
254 | u8 revision; /* PCI revision, low byte of class word */ | 254 | u8 revision; /* PCI revision, low byte of class word */ |
255 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ | 255 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
256 | u8 pcie_cap; /* PCI-E capability offset */ | 256 | u8 pcie_cap; /* PCI-E capability offset */ |
257 | u8 pcie_type:4; /* PCI-E device/port type */ | ||
258 | u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ | 257 | u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ |
259 | u8 rom_base_reg; /* which config register controls the ROM */ | 258 | u8 rom_base_reg; /* which config register controls the ROM */ |
260 | u8 pin; /* which interrupt pin this device uses */ | 259 | u8 pin; /* which interrupt pin this device uses */ |
260 | u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */ | ||
261 | 261 | ||
262 | struct pci_driver *driver; /* which driver has allocated this device */ | 262 | struct pci_driver *driver; /* which driver has allocated this device */ |
263 | u64 dma_mask; /* Mask of the bits of bus address this | 263 | u64 dma_mask; /* Mask of the bits of bus address this |
@@ -816,6 +816,39 @@ static inline int pci_write_config_dword(const struct pci_dev *dev, int where, | |||
816 | return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); | 816 | return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); |
817 | } | 817 | } |
818 | 818 | ||
819 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); | ||
820 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); | ||
821 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); | ||
822 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); | ||
823 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, | ||
824 | u16 clear, u16 set); | ||
825 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, | ||
826 | u32 clear, u32 set); | ||
827 | |||
828 | static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, | ||
829 | u16 set) | ||
830 | { | ||
831 | return pcie_capability_clear_and_set_word(dev, pos, 0, set); | ||
832 | } | ||
833 | |||
834 | static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, | ||
835 | u32 set) | ||
836 | { | ||
837 | return pcie_capability_clear_and_set_dword(dev, pos, 0, set); | ||
838 | } | ||
839 | |||
840 | static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, | ||
841 | u16 clear) | ||
842 | { | ||
843 | return pcie_capability_clear_and_set_word(dev, pos, clear, 0); | ||
844 | } | ||
845 | |||
846 | static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, | ||
847 | u32 clear) | ||
848 | { | ||
849 | return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); | ||
850 | } | ||
851 | |||
819 | /* user-space driven config access */ | 852 | /* user-space driven config access */ |
820 | int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); | 853 | int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); |
821 | int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); | 854 | int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); |
@@ -1650,6 +1683,15 @@ static inline bool pci_is_pcie(struct pci_dev *dev) | |||
1650 | return !!pci_pcie_cap(dev); | 1683 | return !!pci_pcie_cap(dev); |
1651 | } | 1684 | } |
1652 | 1685 | ||
1686 | /** | ||
1687 | * pci_pcie_type - get the PCIe device/port type | ||
1688 | * @dev: PCI device | ||
1689 | */ | ||
1690 | static inline int pci_pcie_type(const struct pci_dev *dev) | ||
1691 | { | ||
1692 | return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4; | ||
1693 | } | ||
1694 | |||
1653 | void pci_request_acs(void); | 1695 | void pci_request_acs(void); |
1654 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); | 1696 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); |
1655 | bool pci_acs_path_enabled(struct pci_dev *start, | 1697 | bool pci_acs_path_enabled(struct pci_dev *start, |