PCI/PM: add PCIe runtime D3cold support

This patch adds runtime D3cold support and corresponding ACPI platform
support.  This patch only enables runtime D3cold support; it does not
enable D3cold support during system suspend/hibernate.

D3cold is the deepest power saving state for a PCIe device, where its main
power is removed.  While it is in D3cold, you can't access the device at
all, not even its configuration space (which is still accessible in D3hot).
Therefore the PCI PM registers can not be used to transition into/out of
the D3cold state; that must be done by platform logic such as ACPI _PR3.

To support wakeup from D3cold, a system may provide auxiliary power, which
allows a device to request wakeup using a Beacon or the sideband WAKE#
signal.  WAKE# is usually connected to platform logic such as ACPI GPE.
This is quite different from other power saving states, where devices
request wakeup via a PME message on the PCIe link.

Some devices, such as those in plug-in slots, have no direct platform
logic.  For example, there is usually no ACPI _PR3 for them.  D3cold
support for these devices can be done via the PCIe Downstream Port leading
to the device.  When the PCIe port is powered on/off, the device is powered
on/off too.  Wakeup events from the device will be notified to the
corresponding PCIe port.

For more information about PCIe D3cold and corresponding ACPI support,
please refer to:

- PCI Express Base Specification Revision 2.0
- Advanced Configuration and Power Interface Specification Revision 5.0

[bhelgaas: changelog]
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Originally-by: Zheng Yan <zheng.z.yan@intel.com>
Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

1 files changed, 12 insertions, 4 deletions

diff --git a/include/linux/pci.h b/include/linux/pci.h
index d8c379dba6ad..002cfd3e33ca 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -132,9 +132,10 @@ static inline const char *pci_power_name(pci_power_t state)
         return pci_power_names[1 + (int) state];
 }
 
-#define PCI_PM_D2_DELAY 200
-#define PCI_PM_D3_WAIT  10
-#define PCI_PM_BUS_WAIT 50
+#define PCI_PM_D2_DELAY         200
+#define PCI_PM_D3_WAIT          10
+#define PCI_PM_D3COLD_WAIT      100
+#define PCI_PM_BUS_WAIT         50
 
 /** The pci_channel state describes connectivity between the CPU and
  *  the pci device.  If some PCI bus between here and the pci device
@@ -278,11 +279,18 @@ struct pci_dev {
         unsigned int    pme_poll:1;     /* Poll device's PME status bit */
         unsigned int    d1_support:1;   /* Low power state D1 is supported */
         unsigned int    d2_support:1;   /* Low power state D2 is supported */
-        unsigned int    no_d1d2:1;      /* Only allow D0 and D3 */
+        unsigned int    no_d1d2:1;      /* D1 and D2 are forbidden */
+        unsigned int    no_d3cold:1;    /* D3cold is forbidden */
+        unsigned int    d3cold_allowed:1;       /* D3cold is allowed by user */
         unsigned int    mmio_always_on:1;       /* disallow turning off io/mem
                                                    decoding during bar sizing */
         unsigned int    wakeup_prepared:1;
+        unsigned int    runtime_d3cold:1;       /* whether go through runtime
+                                                   D3cold, not set for devices
+                                                   powered on/off by the
+                                                   corresponding bridge */
         unsigned int    d3_delay;       /* D3->D0 transition time in ms */
+        unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
 
 #ifdef CONFIG_PCIEASPM
         struct pcie_link_state  *link_state;    /* ASPM link state. */