diff options
author | Vipin Kumar <vipin.kumar@st.com> | 2012-03-14 02:17:19 -0400 |
---|---|---|
committer | David Woodhouse <David.Woodhouse@intel.com> | 2012-03-26 20:00:30 -0400 |
commit | 2a5dbead29a7c081a47133eb428440147a6d8d5a (patch) | |
tree | 75a021aeeac80fa720375a7845d27ba412d3b12f /include/linux/mtd | |
parent | 4774fb0a48aacfec206e6d54ecf58706f6a5320a (diff) |
mtd: nand/fsmc: Remove sparse warnings and errors
This patch removes the sparse below warnings and errors for nand/fsmc driver
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
warning: incorrect type in initializer (different address spaces)
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
expected struct fsmc_regs *regs
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
got void [noderef] <asn:2>*regs_va
[...]
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'include/linux/mtd')
-rw-r--r-- | include/linux/mtd/fsmc.h | 143 |
1 files changed, 66 insertions, 77 deletions
diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h index 18f9127a6631..823359c0f5a1 100644 --- a/include/linux/mtd/fsmc.h +++ b/include/linux/mtd/fsmc.h | |||
@@ -32,88 +32,77 @@ | |||
32 | #define FSMC_FLASH_WIDTH8 1 | 32 | #define FSMC_FLASH_WIDTH8 1 |
33 | #define FSMC_FLASH_WIDTH16 2 | 33 | #define FSMC_FLASH_WIDTH16 2 |
34 | 34 | ||
35 | struct fsmc_nor_bank_regs { | 35 | /* fsmc controller registers for NOR flash */ |
36 | uint32_t ctrl; | 36 | #define CTRL 0x0 |
37 | uint32_t ctrl_tim; | 37 | /* ctrl register definitions */ |
38 | }; | 38 | #define BANK_ENABLE (1 << 0) |
39 | 39 | #define MUXED (1 << 1) | |
40 | /* ctrl register definitions */ | 40 | #define NOR_DEV (2 << 2) |
41 | #define BANK_ENABLE (1 << 0) | 41 | #define WIDTH_8 (0 << 4) |
42 | #define MUXED (1 << 1) | 42 | #define WIDTH_16 (1 << 4) |
43 | #define NOR_DEV (2 << 2) | 43 | #define RSTPWRDWN (1 << 6) |
44 | #define WIDTH_8 (0 << 4) | 44 | #define WPROT (1 << 7) |
45 | #define WIDTH_16 (1 << 4) | 45 | #define WRT_ENABLE (1 << 12) |
46 | #define RSTPWRDWN (1 << 6) | 46 | #define WAIT_ENB (1 << 13) |
47 | #define WPROT (1 << 7) | 47 | |
48 | #define WRT_ENABLE (1 << 12) | 48 | #define CTRL_TIM 0x4 |
49 | #define WAIT_ENB (1 << 13) | 49 | /* ctrl_tim register definitions */ |
50 | 50 | ||
51 | /* ctrl_tim register definitions */ | 51 | #define FSMC_NOR_BANK_SZ 0x8 |
52 | |||
53 | struct fsmc_nand_bank_regs { | ||
54 | uint32_t pc; | ||
55 | uint32_t sts; | ||
56 | uint32_t comm; | ||
57 | uint32_t attrib; | ||
58 | uint32_t ioata; | ||
59 | uint32_t ecc1; | ||
60 | uint32_t ecc2; | ||
61 | uint32_t ecc3; | ||
62 | }; | ||
63 | |||
64 | #define FSMC_NOR_REG_SIZE 0x40 | 52 | #define FSMC_NOR_REG_SIZE 0x40 |
65 | 53 | ||
66 | struct fsmc_regs { | 54 | #define FSMC_NOR_REG(base, bank, reg) (base + \ |
67 | struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS]; | 55 | FSMC_NOR_BANK_SZ * (bank) + \ |
68 | uint8_t reserved_1[0x40 - 0x20]; | 56 | reg) |
69 | struct fsmc_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS]; | 57 | |
70 | uint8_t reserved_2[0xfe0 - 0xc0]; | 58 | /* fsmc controller registers for NAND flash */ |
71 | uint32_t peripid0; /* 0xfe0 */ | 59 | #define PC 0x00 |
72 | uint32_t peripid1; /* 0xfe4 */ | 60 | /* pc register definitions */ |
73 | uint32_t peripid2; /* 0xfe8 */ | 61 | #define FSMC_RESET (1 << 0) |
74 | uint32_t peripid3; /* 0xfec */ | 62 | #define FSMC_WAITON (1 << 1) |
75 | uint32_t pcellid0; /* 0xff0 */ | 63 | #define FSMC_ENABLE (1 << 2) |
76 | uint32_t pcellid1; /* 0xff4 */ | 64 | #define FSMC_DEVTYPE_NAND (1 << 3) |
77 | uint32_t pcellid2; /* 0xff8 */ | 65 | #define FSMC_DEVWID_8 (0 << 4) |
78 | uint32_t pcellid3; /* 0xffc */ | 66 | #define FSMC_DEVWID_16 (1 << 4) |
79 | }; | 67 | #define FSMC_ECCEN (1 << 6) |
68 | #define FSMC_ECCPLEN_512 (0 << 7) | ||
69 | #define FSMC_ECCPLEN_256 (1 << 7) | ||
70 | #define FSMC_TCLR_1 (1) | ||
71 | #define FSMC_TCLR_SHIFT (9) | ||
72 | #define FSMC_TCLR_MASK (0xF) | ||
73 | #define FSMC_TAR_1 (1) | ||
74 | #define FSMC_TAR_SHIFT (13) | ||
75 | #define FSMC_TAR_MASK (0xF) | ||
76 | #define STS 0x04 | ||
77 | /* sts register definitions */ | ||
78 | #define FSMC_CODE_RDY (1 << 15) | ||
79 | #define COMM 0x08 | ||
80 | /* comm register definitions */ | ||
81 | #define FSMC_TSET_0 0 | ||
82 | #define FSMC_TSET_SHIFT 0 | ||
83 | #define FSMC_TSET_MASK 0xFF | ||
84 | #define FSMC_TWAIT_6 6 | ||
85 | #define FSMC_TWAIT_SHIFT 8 | ||
86 | #define FSMC_TWAIT_MASK 0xFF | ||
87 | #define FSMC_THOLD_4 4 | ||
88 | #define FSMC_THOLD_SHIFT 16 | ||
89 | #define FSMC_THOLD_MASK 0xFF | ||
90 | #define FSMC_THIZ_1 1 | ||
91 | #define FSMC_THIZ_SHIFT 24 | ||
92 | #define FSMC_THIZ_MASK 0xFF | ||
93 | #define ATTRIB 0x0C | ||
94 | #define IOATA 0x10 | ||
95 | #define ECC1 0x14 | ||
96 | #define ECC2 0x18 | ||
97 | #define ECC3 0x1C | ||
98 | #define FSMC_NAND_BANK_SZ 0x20 | ||
99 | |||
100 | #define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \ | ||
101 | (FSMC_NAND_BANK_SZ * (bank)) + \ | ||
102 | reg) | ||
80 | 103 | ||
81 | #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ) | 104 | #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ) |
82 | 105 | ||
83 | /* pc register definitions */ | ||
84 | #define FSMC_RESET (1 << 0) | ||
85 | #define FSMC_WAITON (1 << 1) | ||
86 | #define FSMC_ENABLE (1 << 2) | ||
87 | #define FSMC_DEVTYPE_NAND (1 << 3) | ||
88 | #define FSMC_DEVWID_8 (0 << 4) | ||
89 | #define FSMC_DEVWID_16 (1 << 4) | ||
90 | #define FSMC_ECCEN (1 << 6) | ||
91 | #define FSMC_ECCPLEN_512 (0 << 7) | ||
92 | #define FSMC_ECCPLEN_256 (1 << 7) | ||
93 | #define FSMC_TCLR_1 (1) | ||
94 | #define FSMC_TCLR_SHIFT (9) | ||
95 | #define FSMC_TCLR_MASK (0xF) | ||
96 | #define FSMC_TAR_1 (1) | ||
97 | #define FSMC_TAR_SHIFT (13) | ||
98 | #define FSMC_TAR_MASK (0xF) | ||
99 | |||
100 | /* sts register definitions */ | ||
101 | #define FSMC_CODE_RDY (1 << 15) | ||
102 | |||
103 | /* comm register definitions */ | ||
104 | #define FSMC_TSET_0 0 | ||
105 | #define FSMC_TSET_SHIFT 0 | ||
106 | #define FSMC_TSET_MASK 0xFF | ||
107 | #define FSMC_TWAIT_6 6 | ||
108 | #define FSMC_TWAIT_SHIFT 8 | ||
109 | #define FSMC_TWAIT_MASK 0xFF | ||
110 | #define FSMC_THOLD_4 4 | ||
111 | #define FSMC_THOLD_SHIFT 16 | ||
112 | #define FSMC_THOLD_MASK 0xFF | ||
113 | #define FSMC_THIZ_1 1 | ||
114 | #define FSMC_THIZ_SHIFT 24 | ||
115 | #define FSMC_THIZ_MASK 0xFF | ||
116 | |||
117 | /* | 106 | /* |
118 | * There are 13 bytes of ecc for every 512 byte block in FSMC version 8 | 107 | * There are 13 bytes of ecc for every 512 byte block in FSMC version 8 |
119 | * and it has to be read consecutively and immediately after the 512 | 108 | * and it has to be read consecutively and immediately after the 512 |