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authorKevin Cernekee <cernekee@gmail.com>2010-05-04 23:58:03 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2010-05-13 20:54:44 -0400
commit426c457a3216fac74e3d44dd39729b0689f4c7ab (patch)
treecb250bba8d202484a44c9302caf3717eec5538d2 /include/linux/mtd
parent9ea5973883bbe26372f45d99eb3a500f08d966f9 (diff)
mtd: nand: extend NAND flash detection to new MLC chips
Some of the newer MLC devices have a 6-byte ID sequence in which several field definitions differ from older chips in a manner that is not backward compatible. For instance: Samsung K9GAG08U0M (5-byte sequence): ec d5 14 b6 74 4th byte, bits 1:0 encode the page size: 0=1KiB, 1=2KiB, 2=4KiB, 3=8KiB 4th byte, bits 5:4 encode the block size: 0=64KiB, 1=128KiB, ... 4th byte, bit 6 encodes the OOB size: 0=8B/512B, 1=16B/512B Samsung K9GAG08U0D (6-byte sequence): ec d5 94 29 34 41 4th byte, bits 1:0 encode the page size: 0=2KiB, 1=4KiB, 3=8KiB, 4=rsvd 4th byte, bits 7;5:4 encode the block size: 0=128KiB, 1=256KiB, ... 4th byte, bits 6;3:2 encode the OOB size: 1=128B/page, 2=218B/page This patch uses the new 6-byte scheme if the following conditions are all true: 1) The ID code wraps around after exactly 6 bytes 2) Manufacturer is Samsung 3) 6th byte is zero The patch also extends the maximum OOB size from 128B to 256B. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'include/linux/mtd')
-rw-r--r--include/linux/mtd/nand.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 8bdacb885f90..50f3aa00a452 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -53,7 +53,7 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
53 * is supported now. If you add a chip with bigger oobsize/page 53 * is supported now. If you add a chip with bigger oobsize/page
54 * adjust this accordingly. 54 * adjust this accordingly.
55 */ 55 */
56#define NAND_MAX_OOBSIZE 128 56#define NAND_MAX_OOBSIZE 256
57#define NAND_MAX_PAGESIZE 4096 57#define NAND_MAX_PAGESIZE 4096
58 58
59/* 59/*