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authorThomas Gleixner <tglx@linutronix.de>2005-11-07 06:15:31 -0500
committerThomas Gleixner <tglx@mtd.linutronix.de>2005-11-07 08:32:58 -0500
commit61ecfa8777d0bc8e33dc0e5c2cca9b3247da2d37 (patch)
tree8efec81cd9fc0c00b6ed5ebf749dcfe228e5dda4 /include/linux/mtd/nand.h
parent03ead8427d65f6986a8bf5fd3f29a879348780ad (diff)
[MTD] includes: Clean up trailing white spaces
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include/linux/mtd/nand.h')
-rw-r--r--include/linux/mtd/nand.h54
1 files changed, 27 insertions, 27 deletions
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 2d36413b2f94..da5e67b3fc70 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -24,7 +24,7 @@
24 * bat later if I did something naughty. 24 * bat later if I did something naughty.
25 * 10-11-2000 SJH Added private NAND flash structure for driver 25 * 10-11-2000 SJH Added private NAND flash structure for driver
26 * 10-24-2000 SJH Added prototype for 'nand_scan' function 26 * 10-24-2000 SJH Added prototype for 'nand_scan' function
27 * 10-29-2001 TG changed nand_chip structure to support 27 * 10-29-2001 TG changed nand_chip structure to support
28 * hardwarespecific function for accessing control lines 28 * hardwarespecific function for accessing control lines
29 * 02-21-2002 TG added support for different read/write adress and 29 * 02-21-2002 TG added support for different read/write adress and
30 * ready/busy line access function 30 * ready/busy line access function
@@ -36,21 +36,21 @@
36 * CONFIG_MTD_NAND_ECC_JFFS2 is not set 36 * CONFIG_MTD_NAND_ECC_JFFS2 is not set
37 * 08-10-2002 TG extensions to nand_chip structure to support HW-ECC 37 * 08-10-2002 TG extensions to nand_chip structure to support HW-ECC
38 * 38 *
39 * 08-29-2002 tglx nand_chip structure: data_poi for selecting 39 * 08-29-2002 tglx nand_chip structure: data_poi for selecting
40 * internal / fs-driver buffer 40 * internal / fs-driver buffer
41 * support for 6byte/512byte hardware ECC 41 * support for 6byte/512byte hardware ECC
42 * read_ecc, write_ecc extended for different oob-layout 42 * read_ecc, write_ecc extended for different oob-layout
43 * oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB, 43 * oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB,
44 * NAND_YAFFS_OOB 44 * NAND_YAFFS_OOB
45 * 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL 45 * 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL
46 * Split manufacturer and device ID structures 46 * Split manufacturer and device ID structures
47 * 47 *
48 * 02-08-2004 tglx added option field to nand structure for chip anomalities 48 * 02-08-2004 tglx added option field to nand structure for chip anomalities
49 * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id 49 * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
50 * update of nand_chip structure description 50 * update of nand_chip structure description
51 * 01-17-2005 dmarlin added extended commands for AG-AND device and added option 51 * 01-17-2005 dmarlin added extended commands for AG-AND device and added option
52 * for BBT_AUTO_REFRESH. 52 * for BBT_AUTO_REFRESH.
53 * 01-20-2005 dmarlin added optional pointer to hardware specific callback for 53 * 01-20-2005 dmarlin added optional pointer to hardware specific callback for
54 * extra error status checks. 54 * extra error status checks.
55 */ 55 */
56#ifndef __LINUX_MTD_NAND_H 56#ifndef __LINUX_MTD_NAND_H
@@ -120,8 +120,8 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
120#define NAND_CMD_CACHEDPROG 0x15 120#define NAND_CMD_CACHEDPROG 0x15
121 121
122/* Extended commands for AG-AND device */ 122/* Extended commands for AG-AND device */
123/* 123/*
124 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 124 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
125 * there is no way to distinguish that from NAND_CMD_READ0 125 * there is no way to distinguish that from NAND_CMD_READ0
126 * until the remaining sequence of commands has been completed 126 * until the remaining sequence of commands has been completed
127 * so add a high order bit and mask it off in the command. 127 * so add a high order bit and mask it off in the command.
@@ -145,7 +145,7 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
145#define NAND_STATUS_READY 0x40 145#define NAND_STATUS_READY 0x40
146#define NAND_STATUS_WP 0x80 146#define NAND_STATUS_WP 0x80
147 147
148/* 148/*
149 * Constants for ECC_MODES 149 * Constants for ECC_MODES
150 */ 150 */
151 151
@@ -191,12 +191,12 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
191#define NAND_CACHEPRG 0x00000008 191#define NAND_CACHEPRG 0x00000008
192/* Chip has copy back function */ 192/* Chip has copy back function */
193#define NAND_COPYBACK 0x00000010 193#define NAND_COPYBACK 0x00000010
194/* AND Chip which has 4 banks and a confusing page / block 194/* AND Chip which has 4 banks and a confusing page / block
195 * assignment. See Renesas datasheet for further information */ 195 * assignment. See Renesas datasheet for further information */
196#define NAND_IS_AND 0x00000020 196#define NAND_IS_AND 0x00000020
197/* Chip has a array of 4 pages which can be read without 197/* Chip has a array of 4 pages which can be read without
198 * additional ready /busy waits */ 198 * additional ready /busy waits */
199#define NAND_4PAGE_ARRAY 0x00000040 199#define NAND_4PAGE_ARRAY 0x00000040
200/* Chip requires that BBT is periodically rewritten to prevent 200/* Chip requires that BBT is periodically rewritten to prevent
201 * bits from adjacent blocks from 'leaking' in altering data. 201 * bits from adjacent blocks from 'leaking' in altering data.
202 * This happens with the Renesas AG-AND chips, possibly others. */ 202 * This happens with the Renesas AG-AND chips, possibly others. */
@@ -219,8 +219,8 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
219/* Use a flash based bad block table. This option is passed to the 219/* Use a flash based bad block table. This option is passed to the
220 * default bad block table function. */ 220 * default bad block table function. */
221#define NAND_USE_FLASH_BBT 0x00010000 221#define NAND_USE_FLASH_BBT 0x00010000
222/* The hw ecc generator provides a syndrome instead a ecc value on read 222/* The hw ecc generator provides a syndrome instead a ecc value on read
223 * This can only work if we have the ecc bytes directly behind the 223 * This can only work if we have the ecc bytes directly behind the
224 * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */ 224 * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
225#define NAND_HWECC_SYNDROME 0x00020000 225#define NAND_HWECC_SYNDROME 0x00020000
226/* This option skips the bbt scan during initialization. */ 226/* This option skips the bbt scan during initialization. */
@@ -252,7 +252,7 @@ struct nand_chip;
252 252
253/** 253/**
254 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices 254 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
255 * @lock: protection lock 255 * @lock: protection lock
256 * @active: the mtd device which holds the controller currently 256 * @active: the mtd device which holds the controller currently
257 * @wq: wait queue to sleep on if a NAND operation is in progress 257 * @wq: wait queue to sleep on if a NAND operation is in progress
258 * used instead of the per chip wait queue when a hw controller is available 258 * used instead of the per chip wait queue when a hw controller is available
@@ -265,8 +265,8 @@ struct nand_hw_control {
265 265
266/** 266/**
267 * struct nand_chip - NAND Private Flash Chip Data 267 * struct nand_chip - NAND Private Flash Chip Data
268 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device 268 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
269 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device 269 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
270 * @read_byte: [REPLACEABLE] read one byte from the chip 270 * @read_byte: [REPLACEABLE] read one byte from the chip
271 * @write_byte: [REPLACEABLE] write one byte to the chip 271 * @write_byte: [REPLACEABLE] write one byte to the chip
272 * @read_word: [REPLACEABLE] read one word from the chip 272 * @read_word: [REPLACEABLE] read one word from the chip
@@ -289,7 +289,7 @@ struct nand_hw_control {
289 * be provided if a hardware ECC is available 289 * be provided if a hardware ECC is available
290 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support 290 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
291 * @scan_bbt: [REPLACEABLE] function to scan bad block table 291 * @scan_bbt: [REPLACEABLE] function to scan bad block table
292 * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines 292 * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
293 * @eccsize: [INTERN] databytes used per ecc-calculation 293 * @eccsize: [INTERN] databytes used per ecc-calculation
294 * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step 294 * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
295 * @eccsteps: [INTERN] number of ecc calculation steps per page 295 * @eccsteps: [INTERN] number of ecc calculation steps per page
@@ -301,7 +301,7 @@ struct nand_hw_control {
301 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 301 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
302 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 302 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
303 * @chip_shift: [INTERN] number of address bits in one chip 303 * @chip_shift: [INTERN] number of address bits in one chip
304 * @data_buf: [INTERN] internal buffer for one page + oob 304 * @data_buf: [INTERN] internal buffer for one page + oob
305 * @oob_buf: [INTERN] oob buffer for one eraseblock 305 * @oob_buf: [INTERN] oob buffer for one eraseblock
306 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized 306 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
307 * @data_poi: [INTERN] pointer to a data buffer 307 * @data_poi: [INTERN] pointer to a data buffer
@@ -316,22 +316,22 @@ struct nand_hw_control {
316 * @bbt: [INTERN] bad block table pointer 316 * @bbt: [INTERN] bad block table pointer
317 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup 317 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
318 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 318 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
319 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan 319 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
320 * @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices 320 * @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices
321 * @priv: [OPTIONAL] pointer to private chip date 321 * @priv: [OPTIONAL] pointer to private chip date
322 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks 322 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
323 * (determine if errors are correctable) 323 * (determine if errors are correctable)
324 */ 324 */
325 325
326struct nand_chip { 326struct nand_chip {
327 void __iomem *IO_ADDR_R; 327 void __iomem *IO_ADDR_R;
328 void __iomem *IO_ADDR_W; 328 void __iomem *IO_ADDR_W;
329 329
330 u_char (*read_byte)(struct mtd_info *mtd); 330 u_char (*read_byte)(struct mtd_info *mtd);
331 void (*write_byte)(struct mtd_info *mtd, u_char byte); 331 void (*write_byte)(struct mtd_info *mtd, u_char byte);
332 u16 (*read_word)(struct mtd_info *mtd); 332 u16 (*read_word)(struct mtd_info *mtd);
333 void (*write_word)(struct mtd_info *mtd, u16 word); 333 void (*write_word)(struct mtd_info *mtd, u16 word);
334 334
335 void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len); 335 void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len);
336 void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len); 336 void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len);
337 int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len); 337 int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len);
@@ -396,7 +396,7 @@ struct nand_chip {
396 * @name: Identify the device type 396 * @name: Identify the device type
397 * @id: device ID code 397 * @id: device ID code
398 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 398 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
399 * If the pagesize is 0, then the real pagesize 399 * If the pagesize is 0, then the real pagesize
400 * and the eraseize are determined from the 400 * and the eraseize are determined from the
401 * extended id bytes in the chip 401 * extended id bytes in the chip
402 * @erasesize: Size of an erase block in the flash device. 402 * @erasesize: Size of an erase block in the flash device.
@@ -425,7 +425,7 @@ struct nand_manufacturers {
425extern struct nand_flash_dev nand_flash_ids[]; 425extern struct nand_flash_dev nand_flash_ids[];
426extern struct nand_manufacturers nand_manuf_ids[]; 426extern struct nand_manufacturers nand_manuf_ids[];
427 427
428/** 428/**
429 * struct nand_bbt_descr - bad block table descriptor 429 * struct nand_bbt_descr - bad block table descriptor
430 * @options: options for this descriptor 430 * @options: options for this descriptor
431 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE 431 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
@@ -436,14 +436,14 @@ extern struct nand_manufacturers nand_manuf_ids[];
436 * @version: version read from the bbt page during scan 436 * @version: version read from the bbt page during scan
437 * @len: length of the pattern, if 0 no pattern check is performed 437 * @len: length of the pattern, if 0 no pattern check is performed
438 * @maxblocks: maximum number of blocks to search for a bbt. This number of 438 * @maxblocks: maximum number of blocks to search for a bbt. This number of
439 * blocks is reserved at the end of the device where the tables are 439 * blocks is reserved at the end of the device where the tables are
440 * written. 440 * written.
441 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than 441 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
442 * bad) block in the stored bbt 442 * bad) block in the stored bbt
443 * @pattern: pattern to identify bad block table or factory marked good / 443 * @pattern: pattern to identify bad block table or factory marked good /
444 * bad blocks, can be NULL, if len = 0 444 * bad blocks, can be NULL, if len = 0
445 * 445 *
446 * Descriptor for the bad block table marker and the descriptor for the 446 * Descriptor for the bad block table marker and the descriptor for the
447 * pattern which identifies good and bad blocks. The assumption is made 447 * pattern which identifies good and bad blocks. The assumption is made
448 * that the pattern and the version count are always located in the oob area 448 * that the pattern and the version count are always located in the oob area
449 * of the first block. 449 * of the first block.