diff options
| author | Girish K S <girish.shivananjappa@linaro.org> | 2012-01-11 14:04:52 -0500 |
|---|---|---|
| committer | Chris Ball <cjb@laptop.org> | 2012-01-12 15:17:15 -0500 |
| commit | a4924c71aa43d4f8a3f342b1f71788349472e684 (patch) | |
| tree | 19de11b280fca6718e5e766feaa53a43a9a6cb58 /include/linux/mmc/mmc.h | |
| parent | ee5d19b20a711dca3848450979e3cd20b6b795cc (diff) | |
mmc: core: HS200 mode support for eMMC 4.5
This patch adds the support of the HS200 bus speed for eMMC 4.5 devices.
The eMMC 4.5 devices have support for 200MHz bus speed. The function
prototype of the tuning function is modified to handle the tuning
command number which is different in sd and mmc case.
Signed-off-by: Girish K S <girish.shivananjappa@linaro.org>
Signed-off-by: Philip Rakity <prakity@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'include/linux/mmc/mmc.h')
| -rw-r--r-- | include/linux/mmc/mmc.h | 66 |
1 files changed, 65 insertions, 1 deletions
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h index 665548e639e8..fb9f6e116e1c 100644 --- a/include/linux/mmc/mmc.h +++ b/include/linux/mmc/mmc.h | |||
| @@ -51,6 +51,7 @@ | |||
| 51 | #define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ | 51 | #define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ |
| 52 | #define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ | 52 | #define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ |
| 53 | #define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */ | 53 | #define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */ |
| 54 | #define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */ | ||
| 54 | 55 | ||
| 55 | /* class 3 */ | 56 | /* class 3 */ |
| 56 | #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ | 57 | #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ |
| @@ -339,13 +340,76 @@ struct _mmc_csd { | |||
| 339 | 340 | ||
| 340 | #define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */ | 341 | #define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */ |
| 341 | #define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */ | 342 | #define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */ |
| 342 | #define EXT_CSD_CARD_TYPE_MASK 0xF /* Mask out reserved bits */ | 343 | #define EXT_CSD_CARD_TYPE_MASK 0x3F /* Mask out reserved bits */ |
| 343 | #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */ | 344 | #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */ |
| 344 | /* DDR mode @1.8V or 3V I/O */ | 345 | /* DDR mode @1.8V or 3V I/O */ |
| 345 | #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */ | 346 | #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */ |
| 346 | /* DDR mode @1.2V I/O */ | 347 | /* DDR mode @1.2V I/O */ |
| 347 | #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ | 348 | #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ |
| 348 | | EXT_CSD_CARD_TYPE_DDR_1_2V) | 349 | | EXT_CSD_CARD_TYPE_DDR_1_2V) |
| 350 | #define EXT_CSD_CARD_TYPE_SDR_1_8V (1<<4) /* Card can run at 200MHz */ | ||
| 351 | #define EXT_CSD_CARD_TYPE_SDR_1_2V (1<<5) /* Card can run at 200MHz */ | ||
| 352 | /* SDR mode @1.2V I/O */ | ||
| 353 | |||
| 354 | #define EXT_CSD_CARD_TYPE_SDR_200 (EXT_CSD_CARD_TYPE_SDR_1_8V | \ | ||
| 355 | EXT_CSD_CARD_TYPE_SDR_1_2V) | ||
| 356 | |||
| 357 | #define EXT_CSD_CARD_TYPE_SDR_ALL (EXT_CSD_CARD_TYPE_SDR_200 | \ | ||
| 358 | EXT_CSD_CARD_TYPE_52 | \ | ||
| 359 | EXT_CSD_CARD_TYPE_26) | ||
| 360 | |||
| 361 | #define EXT_CSD_CARD_TYPE_SDR_1_2V_ALL (EXT_CSD_CARD_TYPE_SDR_1_2V | \ | ||
| 362 | EXT_CSD_CARD_TYPE_52 | \ | ||
| 363 | EXT_CSD_CARD_TYPE_26) | ||
| 364 | |||
| 365 | #define EXT_CSD_CARD_TYPE_SDR_1_8V_ALL (EXT_CSD_CARD_TYPE_SDR_1_8V | \ | ||
| 366 | EXT_CSD_CARD_TYPE_52 | \ | ||
| 367 | EXT_CSD_CARD_TYPE_26) | ||
| 368 | |||
| 369 | #define EXT_CSD_CARD_TYPE_SDR_1_2V_DDR_1_8V (EXT_CSD_CARD_TYPE_SDR_1_2V | \ | ||
| 370 | EXT_CSD_CARD_TYPE_DDR_1_8V | \ | ||
| 371 | EXT_CSD_CARD_TYPE_52 | \ | ||
| 372 | EXT_CSD_CARD_TYPE_26) | ||
| 373 | |||
| 374 | #define EXT_CSD_CARD_TYPE_SDR_1_8V_DDR_1_8V (EXT_CSD_CARD_TYPE_SDR_1_8V | \ | ||
| 375 | EXT_CSD_CARD_TYPE_DDR_1_8V | \ | ||
| 376 | EXT_CSD_CARD_TYPE_52 | \ | ||
| 377 | EXT_CSD_CARD_TYPE_26) | ||
| 378 | |||
| 379 | #define EXT_CSD_CARD_TYPE_SDR_1_2V_DDR_1_2V (EXT_CSD_CARD_TYPE_SDR_1_2V | \ | ||
| 380 | EXT_CSD_CARD_TYPE_DDR_1_2V | \ | ||
| 381 | EXT_CSD_CARD_TYPE_52 | \ | ||
| 382 | EXT_CSD_CARD_TYPE_26) | ||
| 383 | |||
| 384 | #define EXT_CSD_CARD_TYPE_SDR_1_8V_DDR_1_2V (EXT_CSD_CARD_TYPE_SDR_1_8V | \ | ||
| 385 | EXT_CSD_CARD_TYPE_DDR_1_2V | \ | ||
| 386 | EXT_CSD_CARD_TYPE_52 | \ | ||
| 387 | EXT_CSD_CARD_TYPE_26) | ||
| 388 | |||
| 389 | #define EXT_CSD_CARD_TYPE_SDR_1_2V_DDR_52 (EXT_CSD_CARD_TYPE_SDR_1_2V | \ | ||
| 390 | EXT_CSD_CARD_TYPE_DDR_52 | \ | ||
| 391 | EXT_CSD_CARD_TYPE_52 | \ | ||
| 392 | EXT_CSD_CARD_TYPE_26) | ||
| 393 | |||
| 394 | #define EXT_CSD_CARD_TYPE_SDR_1_8V_DDR_52 (EXT_CSD_CARD_TYPE_SDR_1_8V | \ | ||
| 395 | EXT_CSD_CARD_TYPE_DDR_52 | \ | ||
| 396 | EXT_CSD_CARD_TYPE_52 | \ | ||
| 397 | EXT_CSD_CARD_TYPE_26) | ||
| 398 | |||
| 399 | #define EXT_CSD_CARD_TYPE_SDR_ALL_DDR_1_8V (EXT_CSD_CARD_TYPE_SDR_200 | \ | ||
| 400 | EXT_CSD_CARD_TYPE_DDR_1_8V | \ | ||
| 401 | EXT_CSD_CARD_TYPE_52 | \ | ||
| 402 | EXT_CSD_CARD_TYPE_26) | ||
| 403 | |||
| 404 | #define EXT_CSD_CARD_TYPE_SDR_ALL_DDR_1_2V (EXT_CSD_CARD_TYPE_SDR_200 | \ | ||
| 405 | EXT_CSD_CARD_TYPE_DDR_1_2V | \ | ||
| 406 | EXT_CSD_CARD_TYPE_52 | \ | ||
| 407 | EXT_CSD_CARD_TYPE_26) | ||
| 408 | |||
| 409 | #define EXT_CSD_CARD_TYPE_SDR_ALL_DDR_52 (EXT_CSD_CARD_TYPE_SDR_200 | \ | ||
| 410 | EXT_CSD_CARD_TYPE_DDR_52 | \ | ||
| 411 | EXT_CSD_CARD_TYPE_52 | \ | ||
| 412 | EXT_CSD_CARD_TYPE_26) | ||
| 349 | 413 | ||
| 350 | #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ | 414 | #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ |
| 351 | #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ | 415 | #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ |