diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-08-08 12:33:47 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-08-08 14:18:18 -0400 |
commit | 097d9eb537ff4d88b74c3fe67392e27c478ca3c5 (patch) | |
tree | 9034d676d9096857a380aab9d99e3e88fccb6bfe /include/linux/mlx4 | |
parent | c41107c2d4fd31924533f4dbc4c3428acc2b5894 (diff) | |
parent | aeee90dfa01844168cd7f8051d0a0f969c573067 (diff) |
Merge Linus' latest into master
Conflicts:
drivers/watchdog/at91rm9200_wdt.c
drivers/watchdog/davinci_wdt.c
drivers/watchdog/ep93xx_wdt.c
drivers/watchdog/ixp2000_wdt.c
drivers/watchdog/ixp4xx_wdt.c
drivers/watchdog/ks8695_wdt.c
drivers/watchdog/omap_wdt.c
drivers/watchdog/pnx4008_wdt.c
drivers/watchdog/sa1100_wdt.c
drivers/watchdog/wdt285.c
Diffstat (limited to 'include/linux/mlx4')
-rw-r--r-- | include/linux/mlx4/cq.h | 36 |
1 files changed, 24 insertions, 12 deletions
diff --git a/include/linux/mlx4/cq.h b/include/linux/mlx4/cq.h index 071cf96cf01f..6f65b2c8bb89 100644 --- a/include/linux/mlx4/cq.h +++ b/include/linux/mlx4/cq.h | |||
@@ -39,17 +39,18 @@ | |||
39 | #include <linux/mlx4/doorbell.h> | 39 | #include <linux/mlx4/doorbell.h> |
40 | 40 | ||
41 | struct mlx4_cqe { | 41 | struct mlx4_cqe { |
42 | __be32 my_qpn; | 42 | __be32 vlan_my_qpn; |
43 | __be32 immed_rss_invalid; | 43 | __be32 immed_rss_invalid; |
44 | __be32 g_mlpath_rqpn; | 44 | __be32 g_mlpath_rqpn; |
45 | u8 sl; | 45 | __be16 sl_vid; |
46 | u8 reserved1; | ||
47 | __be16 rlid; | 46 | __be16 rlid; |
48 | __be32 ipoib_status; | 47 | __be16 status; |
48 | u8 ipv6_ext_mask; | ||
49 | u8 badfcs_enc; | ||
49 | __be32 byte_cnt; | 50 | __be32 byte_cnt; |
50 | __be16 wqe_index; | 51 | __be16 wqe_index; |
51 | __be16 checksum; | 52 | __be16 checksum; |
52 | u8 reserved2[3]; | 53 | u8 reserved[3]; |
53 | u8 owner_sr_opcode; | 54 | u8 owner_sr_opcode; |
54 | }; | 55 | }; |
55 | 56 | ||
@@ -64,6 +65,11 @@ struct mlx4_err_cqe { | |||
64 | }; | 65 | }; |
65 | 66 | ||
66 | enum { | 67 | enum { |
68 | MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29, | ||
69 | MLX4_CQE_QPN_MASK = 0xffffff, | ||
70 | }; | ||
71 | |||
72 | enum { | ||
67 | MLX4_CQE_OWNER_MASK = 0x80, | 73 | MLX4_CQE_OWNER_MASK = 0x80, |
68 | MLX4_CQE_IS_SEND_MASK = 0x40, | 74 | MLX4_CQE_IS_SEND_MASK = 0x40, |
69 | MLX4_CQE_OPCODE_MASK = 0x1f | 75 | MLX4_CQE_OPCODE_MASK = 0x1f |
@@ -86,13 +92,19 @@ enum { | |||
86 | }; | 92 | }; |
87 | 93 | ||
88 | enum { | 94 | enum { |
89 | MLX4_CQE_IPOIB_STATUS_IPV4 = 1 << 22, | 95 | MLX4_CQE_STATUS_IPV4 = 1 << 6, |
90 | MLX4_CQE_IPOIB_STATUS_IPV4F = 1 << 23, | 96 | MLX4_CQE_STATUS_IPV4F = 1 << 7, |
91 | MLX4_CQE_IPOIB_STATUS_IPV6 = 1 << 24, | 97 | MLX4_CQE_STATUS_IPV6 = 1 << 8, |
92 | MLX4_CQE_IPOIB_STATUS_IPV4OPT = 1 << 25, | 98 | MLX4_CQE_STATUS_IPV4OPT = 1 << 9, |
93 | MLX4_CQE_IPOIB_STATUS_TCP = 1 << 26, | 99 | MLX4_CQE_STATUS_TCP = 1 << 10, |
94 | MLX4_CQE_IPOIB_STATUS_UDP = 1 << 27, | 100 | MLX4_CQE_STATUS_UDP = 1 << 11, |
95 | MLX4_CQE_IPOIB_STATUS_IPOK = 1 << 28, | 101 | MLX4_CQE_STATUS_IPOK = 1 << 12, |
102 | }; | ||
103 | |||
104 | enum { | ||
105 | MLX4_CQE_LLC = 1, | ||
106 | MLX4_CQE_SNAP = 1 << 1, | ||
107 | MLX4_CQE_BAD_FCS = 1 << 4, | ||
96 | }; | 108 | }; |
97 | 109 | ||
98 | static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd, | 110 | static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd, |